Datasheet std70n02l_std70n02l-1 Datasheet

N-channel 25V - 0.0068Ω - 60A - DPAK - IPAK

3

Features

Type V

STD70N02L 25V <0.008Ω 60A

STD70N02L-1 25V <0.008Ω 60A

DSS

R

DS(on)

STD70N02L

STD70N02L-1

STripFET™ III Power MOSFET

I

D

■ R

■ Conduction losses reduced

■ Switching losses reduced

■ Low threshold device

* Qg industry’s benchmark

DS(ON)

Application

■ Switching applications

Description

This series of products utilizes the latest
advanced design rules of ST’s proprietary
STripFET™ technology. This is suitable for the
most demanding DC-DC converter application
where high efficiency is to be achieved.

3

DPAK

1

IPAK

1

Figure 1. Internal schematic diagram

2

Table 1. Device summary

Order codes Marking Package Packaging

STD70N02L-1 D70N02L IPAK Tube

STD70N02L D70N02L DPAK Tape & reel

October 2007 Rev 5 1/17

www.st.com

17

Contents STD70N02L - STD70N02L-1

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2/17

STD70N02L - STD70N02L-1 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

(1)

V

spike

V

V

DGR

V

I

D

I

DM

P

E

AS

T

1. Guaranted when external Rg=4.7Ω and Tf<Tfmax

2. Value limited by wire bonding

3. Pulse width limited by safe operating area

4. Starting Tj =25°C, Id = 30A, VDD = 15V

Drain-source voltage rating 30 V

Drain-source voltage (VGS = 0)

DS

Drain-gate voltage (RGS = 20kΩ)

Gate-source voltage ± 20 V

GS

(2)

Drain current (continuous) at TC = 25°C

I

Drain current (continuous) at TC = 100°C

D

(3)

Drain current (pulsed) 240 A

Total dissipation at TC = 25°C

TOT

25 V

25 V

60 A

42 A

60 W

Derating factor 0.4 W/°C

(4)

Single pulse avalanche energy 280 mJ

T

Operating junction temperature

j

Storage temperature

stg

-55 to 175 °C

Table 3. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case Max 2.5 °C/W

Rthj-amb Thermal resistance junction-amb Max 100 °C/W

T

Maximum lead temperature for soldering purpose 275 °C

l

3/17

Electrical characteristics STD70N02L - STD70N02L-1

2 Electrical characteristics

(Tcase =25°C unless otherwise specified)

Table 4. On /off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

Drain-source breakdown
voltage

Zero gate voltage drain
current (VGS = 0)

Gate body leakage
current (V

DS

= 0)

Gate threshold voltage

Static drain-source on
resistance

= 25mA, VGS= 0

I

D

V

= 20V,

DS

V

= 20V,Tc = 125°C

DS

= ±20V

V

GS

V

= VGS, ID = 250µA

DS

VGS= 10V, ID= 30A

V

= 5V, ID= 15A

GS

25 V

1

10µAµA

±100 nA

11.8 V

0.0068

0.090

0.008

0.014ΩΩ

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Forward

(1)

g

fs

C

C

C

Q

Q

Q

R

Q

OSS

1. Pulsed: pulse duration = 300µs, duty cycle 1.5%

2. Q

oss.

transconductance

Input capacitance

iss

Output capacitance

oss

Reverse transfer

rss

capacitance

g

Total gate charge
Gate-source charge

gs

Gate-drain charge

gd

Gate input resistance

G

(2)

Output charge

= C

* D Vin, C

oss

= Cgd + C

oss

V

=15V, ID = 30A

DS

=16V, f=1MHz, VGS=0

V

DS

=10V, ID = 60A

V

DD

=10V

V

GS

(see Figure 8)

f=1MHz Gate DC Bias =0
test signal level =20mV
open drain

=16V, V

V

DS

(see Appendix A)

gd.

GS

=0V

27 S

1400

400

55

24

32 nC

5

3.4

0.5 1.5 3 Ω

9.4 nC

pF
pF
pF

nC
nC

4/17

STD70N02L - STD70N02L-1 Electrical characteristics

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max Unit

t

d(on)

t

d(off)

Turn-on delay time

t

Rise time

r

Turn-off delay time

t

Fall time

f

=10V, ID=30A,

V

DD

=4.7Ω, VGS=10V

R

G

(see Figure 18)

10

130

27
16 21.6

Table 7. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

I

SDM

VSD

Q

I

RRM

1. Pulsed: pulse duration = 300µs, duty cycle 1.5%

Source-drain current

SD

Source-drain current (pulsed)

(1)

Forward on voltage

t

rr

Reverse recovery time
Reverse recovery charge

rr

Reverse recovery current

=30A, VGS=0

I

SD

=60A, di/dt = 100A/µs,

I

SD

=20V, Tj=150°C

V

DD

(see Figure 21)

50

200AA

1.3 V

36
36

2

ns
ns
ns
ns

ns

nC

A

5/17

Electrical characteristics STD70N02L - STD70N02L-1

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance

Figure 4. Output characterisics Figure 5. Transfer characteristics

Figure 6. Transconductance Figure 7. Static drain-source on resistance

6/17

STD70N02L - STD70N02L-1 Electrical characteristics

Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations

Figure 10. Normalized gate threshold voltage

vs temperature

Figure 12. Source-drain diode forward

characteristics

Figure 11. Normalized on resistance vs

temperature

Figure 13. Normalized B

vs temperature

VDSS

7/17

Electrical characteristics STD70N02L - STD70N02L-1

Figure 14. Allowable I

vs time in avalanche

AV

The previous curve gives the single pulse safe operating area for unclamped inductive
loads, under the following conditions:

P

E

=0.5*(1.3*B

D(AVE)

AS(AR) =PD(AVE)

*t

VDSS

AV

*IAV )

Where:

I

is the allowable current in avalanche

AV

P

t

AV

is the average power dissipation in avalanche (single pulse)

D(AVE)

is the time in avalanche

8/17

STD70N02L - STD70N02L-1 Buck convert

Appendix A Buck convert

Figure 15. Synchronous buck converter

The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the wotking
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.

The low side (SW2) device requires:

Very low R

Small Q

Small C

Small Q

The C

gls

oss

rr

gd/Cgs

to reduce losses on SW1 during its turn-on

to reduce conduction losses

DS(on)

to reduce the gate charge losses

to reduce losses due to output capacitance

ratio lower than Vth/Vgg ratio especially with low drain to source voltage to

avoid the cross conduction phenomenon.

The high side (SW1) device requires:

Small R

and LG to allow higher gate current peak and to limit the voltage feedback on the

G

gate

Small Q

Low R

to have a faster commutation and to reduce gate charge losses

g

to reduce the conduction losses

DS(on)

9/17

Buck convert STD70N02L - STD70N02L-1

Table 8. Power losses

High side switch (SW1) Low side switch (SW2)

P

conduction

R

DS on()IL

2

•δ•

R

DS on()IL

2

• 1 δ–()•

P

switching

inQgsth SW1()Qgd SW1()

recovery Not applicable

P

diode

conduction Not applicable

P

gate(Qg)

P

Qoss

Q

gSW1()Vgg

VinQ

• f•

oss SW1()

------------------------------------------------- -

Table 9. Power losses parameters

Paramter Meaning

d Duty-cycle

Q

gsth

Q

gls

Pconduction On state losses

Post threshold gate charge

Third quadrant gate charge

+()• f

• f•

2

I

L

----

••

I

g

Zero voltage switching

1

V

• f•

in

V

fSW2()ILtdeadtime

Q

gls SW2()Vgg

V

• f•

inQoss SW2()

------------------------------------------------- -

Q

rr SW2()

• f•

2

f•••

Pswitching On-off transition losses

Pdiode Conduction and reverse recovery diode losses

Pgate Gate driver losses

P

Qoss

Output capacitance losses

10/17

STD70N02L - STD70N02L-1 Test circuits

3 Test circuits

Figure 16. Switching times test circuit for

resistive load

Figure 18. Test circuit for inductive load

switching and diode recovery times

Figure 17. Gate charge test circuit

Figure 19. Unclamped inductive load test

circuit

Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform

11/17

Package mechanical data STD70N02L - STD70N02L-1

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at : www.st.com

12/17

STD70N02L - STD70N02L-1 Package mechanical data

TO-251 (IPAK) MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

mm inch

A 2.2 2.4 0.086 0.094

A1 0.9 1.1 0.035 0.043

A3 0.7 1.3 0.027 0.051

B 0.64 0.9 0.025 0.031

B2 5.2 5.4 0.204 0.212

B3 0.85 0.033

B5 0.3 0.012

B6 0.95 0.037

C 0.45 0.6 0.017 0.023

C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244

E 6.4 6.6 0.252 0.260

G 4.4 4.6 0.173 0.181

H 15.9 16.3 0.626 0.641

L 9 9.4 0.354 0.370

L1 0.8 1.2 0.031 0.047

L2 0.8 1 0.031 0.039

H

C

A

E

= =

C2

L2

B2

= =

D

B3

2

1 3

L1

B6

A1

A3

L

B

B5

G

= =

0068771-E

13/17

Package mechanical data STD70N02L - STD70N02L-1

DPAK MECHANICAL DATA

DIM.

A 2.2 2.4 0.086 0.094
A1 0.9 1 .1 0.035 0.043
A2 0.03 0.23 0.001 0.009

B 0.64 0 .9 0.025 0.035
b4 5.2 5.4 0.204 0.212

C 0.45 0 .6 0.017 0.023
C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244
D1 5.1 0.200

E 6.4 6.6 0.252 0.260
E1 4.7 0.185

e 2.28 0.090
e1 4.4 4.6 0.173 0.181

H 9.35 10.1 0.368 0.397

L 1 0.039

(L1) 2.8 0.110

L2 0.8 0 .031
L4 0.6 1 0.023 0.039

R 0.2 0.008
V2 0° 8° 0° 8°

MIN. TYP MA X. MIN. TYP. MAX.

mm. inch

14/17

0068772-F

STD70N02L - STD70N02L-1 Package mechanical data

5 Package mechanical data

DPAK FOOTPRINT

All dimensions are in millimeters

TAPE AND REEL SHIPMENT

REEL MECHANICAL DATA

DIM.

A 330 12.992

B 1.5 0.059

C 12.8 13.2 0.504 0.520

D 20.2 0.795

G 16.4 18.4 0.645 0.724

N 50 1.968

T 22.4 0.881

mm inch

MIN. MAX. MIN. MAX.

TAPE MECHANICAL DATA

DIM.

A0 6.8 7 0.267 0.275

B0 10.4 10.6 0.409 0.417

B1 12.1 0.476

D 1.5 1.6 0.059 0.063

D1 1.5 0.059

E 1.65 1.85 0.065 0.073

F 7.4 7.6 0.291 0.299

K0 2.55 2.75 0.100 0.108

P0 3.9 4.1 0.153 0.161

P1 7.9 8.1 0.311 0.319

P2 1.9 2.1 0.075 0.082

R 40 1.574

W 15.7 16.3 0.618 0.641

mm inch

MIN. MAX. MIN. MAX.

BASE QTY BULK QTY

2500 2500

15/17

Revision history STD70N02L - STD70N02L-1

6 Revision history

Table 10. Document revision history

Date Revision Changes

29-Aug-2005 1 First release

02-Dec-2005 2 Modified Appendix A

07-Apr-2006 3 New template

03-May-2006 4 New value in Tab l e 4, new curve (see Figure 14)

25-Oct-2007 5 Updated BV

dss

value

16/17

STD70N02L - STD70N02L-1

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