Datasheet std55nh2ll_std55nh2ll-1 Datasheet

N-channel 24V - 0.010Ω - 40A - DPAK/IPAK

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Obsolete Product(s) - Obsolete Product(s)

Ultra low gate charge STripFET™ Power MOSFET

General features

Type V

STD55NH2LL-1 24V <0.011Ω 40A

STD55NH2LL 24V <0.011Ω 40A

1. Value limited by wire bonding

DSS

R

DS(on)

STD55NH2LL

STD55NH2LL-1

I

D

(1)

(1)

2

1

3

1

■ R

■ Conduction losses reduced

■ Switching losses reduced

■ Low threshold device

* Qg industry’s benchmark

DS(ON)

Description

The STD55NH2LL is based on the latest
generation of ST's proprietary STripFET™
technology. An innovative layout enables the
device to also exhibit extremely low gate charge
for the most demanding requirements as high­side switch in high-frequency DC-DC converters.
It's therefore ideal for high-density converters in
Telecom and Computer applications.

Applications

■ Switching application

iPAK

DPAK

Internal schematic diagram

Order codes

Part number Marking Package Packaging

STD55NH2LL-1 D55NH2LL IPAK Tube

STD55NH2LLT4 D55NH2LL DPAK Tape & reel

July 2006 Rev 5 1/16

www.st.com

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Contents STD55NH2LL - STD55NH2LL-1

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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STD55NH2LL - STD55NH2LL-1 Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

(1)

V

spike

V

DS

V

DGR

V

GS

(2)

I

D

(2)

I

D

(3)

I

DM

P

tot

(4)

E

AS

T

stg

T

j

1. Garanted when external Rg=4.7 Ω and tf < t

2. Value limited by wire bonding

3. Pulse width limited by safe operating area.

4. Starting Tj = 25 °C, ID = 20A, VDD = 15V

Drain-source voltage rating 30 V

Drain-source voltage (VGS = 0) 24 V

Drain-gate voltage (RGS = 20 kΩ)24V

Gate- source voltage ± 16 V

Drain current (continuous) at TC = 25°C 40 A

Drain current (continuous) at TC = 100°C 28 A

Drain current (pulsed) 160 A

Total dissipation at TC = 25°C 60 W

Derating Factor 0.4 W/°C

Single pulse avalanche energy 600 mJ

Storage temperature

-55 to 175 °C

Max. operating junction temperature

.

fmax

Table 2. Thermal data

Rthj-case Thermal resistance junction-case max 2.5 °C/W

Rthj-amb Thermal resistance junction-ambient max 100 °C/W

T

J

Maximum lead temperature for soldering purpose 275 °C

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Electrical characteristics STD55NH2LL - STD55NH2LL-1

2 Electrical characteristics

(T

=25°C unless otherwise specified)

CASE

Table 3. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

Drain-source
breakdown voltage

Zero gate voltage
drain current (V

GS

Gate-body leakage
current (V

DS

= 0)

= 0)

ID = 25mA, VGS =0 24 V

V

= max rating

DS

VDS = max rating

= 125°C

T

C

1

10

VGS = ± 16V ±100 nA

Gate threshold voltage VDS = VGS, ID = 250µA 1 V

Static drain-source on
resistance

= 10V, ID = 20A

V

GS

= 4.5V, ID = 20A

V

GS

0.010

0.012

0.011

0.0135ΩΩ

Table 4. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Forward

(1)

g

fs

transconductance

V

= 10V, ID=10A 18 S

DS

µA
µA

C

C

C

Input capacitance

iss

Output capacitance

oss

Reverse transfer

rss

capacitance

= 25V, f = 1MHz,

V

DS

VGS = 0

990
385

40

pF
pF
pF

f = 1 MHz Gate

R

Gate Input Resistance

G

DC Bias = 0 Test Signal
Level = 20 mV Open

1.3 Ω

Drain

t

d(on)

t

t

d(off)

t

Q
Q
Q

Q

oss

1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

2. Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Chapter 4: Appendix A

Turn-on delay time
Rise time

r

Turn-off delay time
Fall time

f

Total gate charge

g

Gate-source charge

gs

Gate-drain charge

gd

(2)

Output charge VDS= 16 V, VGS= 0 V 7.6 nC

= 10V, ID = 20A

V

DD

RG=4.7Ω VGS = 4.5V
(see Figure 13)

0.44V ≤ VDD ≤ 10V,
ID = 40A,

= 4.5V, RG=4.7Ω

V

GS

(see Figure 14)

15
56
13
10

8.7

4.2

2.4

ns
ns
ns
ns

11 nC

nC
nC

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STD55NH2LL - STD55NH2LL-1 Electrical characteristics

Table 5. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

SD

I

SDM

V

SD

t

Q

I

RRM

1. Pulse width limited by safe operating area.

2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

Source-drain current
Source-drain current

(1)

(pulsed)

(2)

Forward on voltage ISD = 20A, VGS = 0 1.3 V

Reverse recovery time

rr

Reverse recovery charge

rr

Reverse recovery current

= 40A, di/dt = 100A/µs,

I

SD

= 15V, Tj = 150°C

V

DD

(see Figure 15)

32.5
28

1.7

40

160

A
A

ns

nC

A

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Electrical characteristics STD55NH2LL - STD55NH2LL-1

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance

Figure 3. Output characterisics Figure 4. Transfer characteristics

Figure 5. Transconductance Figure 6. Static drain-source on resistance

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STD55NH2LL - STD55NH2LL-1 Electrical characteristics

Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations

Figure 9. Normalized gate threshold voltage

vs temperature

Figure 11. Source-drain diode forward

characteristics

Figure 10. Normalized on resistance vs

temperature

Figure 12. Normalized breakdown voltage vs

temperature

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Test circuit STD55NH2LL - STD55NH2LL-1

3 Test circuit

Figure 13. Switching times test circuit for

resistive load

Figure 15. Test circuit for inductive load

switching and diode recovery times

Figure 14. Gate charge test circuit

Figure 16. Unclamped Inductive load test

circuit

Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform

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STD55NH2LL - STD55NH2LL-1 Appendix A

4 Appendix A

Figure 19. Buck converter: power losses estimation

The power losses associated with the FETs in a synchronous buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.

● The low side (SW2) device requires:

● Very low R

● Small Qgls to reduce the gate charge losses

● Small Coss to reduce losses due to output capacitance

● Small Qrr to reduce losses on SW1 during its turn-on

● The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source

● voltage to avoid the cross conduction phenomenon;

● The high side (SW1) device requires:

● Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on

the gate

● Small Qg to have a faster commutation and to reduce gate charge losses

● Low R

DS(on)

to reduce conduction losses

DS(on)

to reduce the conduction losses.

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Appendix A STD55NH2LL - STD55NH2LL-1

V

Table 6. Power losses calculation

High side switching (SW1) Low side switch (SW2)

Pconduction

Pswitching Zero Voltage Switching

Pdiode

Pgate(Q

Conductio

P

Qoss

Recovery

(1)

n

)

G

Not applicable

Not applicable

2

δ

*I *R

LDS(on)SW1

I

+

gd(SW1)gsth(SW1)in

f*V*Q

ggg(SW1)

oss(SW1)in

f*Q*V

L

*f*)Q(Q*

I

g

2

1. Dissipated by SW1 during turn-on

Table 7. Paramiters meaning

2
LDS(on)SW2

rr(SW2)in

deadtimeLf(SW2)

gggls(SW2)

oss(SW2)in

)1(*I *R

δ

−

f*Q*V

f*t*I*V

f*V*Q

f*Q*V

2

Parameter Meaning

d Duty-cycle

Q

gsth

Q

gls

Pconduction On state losses

Pswitching On-off transition losses

Pdiode Conduction and reverse recovery diode losses

Pgate Gate drive losses

P

Qoss

Post threshold gate charge

Third quadrant gate charge

Output capacitance losses

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STD55NH2LL - STD55NH2LL-1 Package mechanical data

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com

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Package mechanical data STD55NH2LL - STD55NH2LL-1

TO-251 (IPAK) MECHANICAL DATA

DIM.

A 2.2 2.4 0.086 0.094

A1 0.9 1.1 0.035 0.043

A3 0.7 1.3 0.027 0.051

B 0.64 0.9 0.025 0.031

B2 5.2 5.4 0.204 0.212

B3 0.85 0.033

B5 0.3 0.012

B6 0.95 0.037

C 0.45 0.6 0.017 0.023

C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244

E 6.4 6.6 0.252 0.260

G 4.4 4.6 0.173 0.181

H 15.9 16.3 0.626 0.641

L 9 9.4 0.354 0.370

L1 0.8 1.2 0.031 0.047

L2 0.8 1 0.031 0.039

MIN. TYP. MAX. MIN. TYP. MAX.

A

mm inch

H

C

B5

A3

G

= =

E

= =

C2

L2

B2

= =

D

B3

2

1 3

L1

B6

A1

L

B

0068771-E

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STD55NH2LL - STD55NH2LL-1 Package mechanical data

DPAK MECHANICAL DATA

DIM.

A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009

B 0.64 0.9 0.025 0.035

b4 5.2 5.4 0.204 0.212

C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244
D1 5.1 0.200

E 6.4 6.6 0.252 0.260
E1 4.7 0.185

e 2.28 0.090

e1 4.4 4.6 0.173 0.181

H 9.35 10.1 0.368 0.397

L 1 0.039

(L1) 2.8 0.110

L2 0.8 0.031
L4 0.6 1 0.023 0.039

R 0.2 0.008
V2 0° 8° 0 ° 8°

MIN. TYP MA X. MIN. TYP. MAX.

mm. inch

0068772-F

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Packing mechanical data STD55NH2LL - STD55NH2LL-1

6 Packing mechanical data

DPAK FOOTPRINT

All dimensions are in millimeters

TAPE AND REEL SHIPMENT

REEL MECHANICAL DATA

DIM.

A 330 12.992

B 1.5 0.059

C 12.8 13.2 0.504 0.520

D 20.2 0.795

G 16.4 18.4 0.645 0.724

N 50 1.968

T 22.4 0.881

mm inch

MIN. MAX. MIN. MAX.

TAPE MECHANICAL DATA

DIM.

A0 6.8 7 0.267 0.275

B0 10.4 10.6 0.409 0.417

B1 12.1 0.476

D 1.5 1.6 0.059 0.063

D1 1.5 0.059

E 1.65 1.85 0.065 0.073

F 7.4 7.6 0.291 0.299

K0 2.55 2.75 0.100 0.108

P0 3.9 4.1 0.153 0.161

P1 7.9 8.1 0.311 0.319

P2 1.9 2.1 0.075 0.082

R 40 1.574

W 15.7 16.3 0.618 0.641

mm inch

MIN. MAX. MIN. MAX.

BASE QTY BULK QTY

2500 2500

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STD55NH2LL - STD55NH2LL-1 Revision history

7 Revision history

Table 8. Revision history

Date Revision Changes

22-Jun-2004 2 Preliminary datasheet

21-Jul-2005 3 Complete version

13-Jun-2006 4 Packing mechanical data inserted

16-Jul-2006 5 New template, no content change

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STD55NH2LL - STD55NH2LL-1

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