Datasheet std50n03l_std50n03l-1 Datasheet

Page 1
N-CHANNEL 30V - 9.2mΩ - 40A - DPAK/IPAK
3
General features
Type V
STD50N03L
STD50N03L-1
■ R
DS(on)*Qg
■ Conduction losses reduced
■ Switching losses reduced
■ Low threshold device
industry’s benchmark
DSS
30V 30V
Description
This product utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved.
R
DS(on)
10.5mΩ
10.5mΩ
I
D
40A 40A
STD50N03L
STD50N03L-1
STripFET™ III Power MOSFET
2
1
IPAK
Internal schematic diagram
1
DPAK
3
Applications
■ Switching applications
Order codes
Part number Marking Package Packaging
STD50N03L D50N03L DPAK Tape & reel
STD50N03L-1 D50N03L IPAK Tube
October 2006 Rev 2 1/16
www.st.com
16
Page 2
Contents STD50N03L - STD50N03L-1
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Page 3
STD50N03L - STD50N03L-1 Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
I
V
V
I
D
DM
P
DS
GS
I
D
TOT
Drain-source voltage (VGS = 0) 30 V
Gate-source voltage ±20 V
(1)
Drain current (continuous) at TC = 25°C 40 A
Drain current (continuous) at TC=100°C 36 A
(2)
Drain current (pulsed) 160 A
Total dissipation at TC = 25°C 60 W
Derating factor 0.4 W/°C
(3)
E
AS
T
T
stg
1. Limited by wire bonding
2. Pulse width limited by safe operating area
3. Starting Tj = 25°C, ID =20A, VDD =15V
Single pulse avalanche energy 230 mJ
Operating junction temperature
J
Storage temperature
-55 to 175 °C
Table 2. Thermal data
Symbol Parameter Value Unit
R
thJ-Case
R
thJ-Amb
T
Thermal resistance junction-case max 2.5 °C/W
Thermal resistance junction-ambient max 100 °C/W
Maximum lead temperature for soldering
j
purpose
275 °C
3/16
Page 4
Electrical characteristics STD50N03L - STD50N03L-1

2 Electrical characteristics

(T
=25°C unless otherwise specified)
CASE
Table 3. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source breakdown voltage
Zero gate voltage drain current (VGS = 0)
Gate body leakage current
= 0)
(V
DS
Gate threshold voltage
Static drain-source on resistance
= 250µA, VGS= 0
I
D
V
= 30V
DS
V
= 30V, Tc=125°C
DS
= ±20V
V
GS
= VGS, ID = 250µA
V
DS
= 10V, ID= 20A
V
GS
= 5V, ID= 20A
V
GS
30 V
1
10
±100 nA
1V
9.2
0.012
10.5
0.019mΩΩ
Table 4. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
g
Total gate charge Gate-source charge
gs
Gate-drain charge
gd
(1)
Output charge
Gate input resistance
G
=25V, f=1MHz,
V
DS
V
=0
GS
= 15V, ID = 40A
V
DD
= 5V
V
GS
(see Figure 13)
V
DS
= 24V ; V
GS
=0
f=1MHz Gate Bias Bias=0 Test signal Level=20mV
open drain
1434
294
48
10.4
14 nC
5.1
3.7
12.6 nC
1.1 Ω
Q
C
C
C
Q
Q
Q
OSS
R
µA µA
pF pF pF
nC nC
1. Q
OSS=COSS
*D Vin; C
= Cgd + Cgd. See Appendix A
OSS
4/16
Page 5
STD50N03L - STD50N03L-1 Electrical characteristics
Table 5. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
=15V, ID= 25A,
V
t
d(on)
t
d(off)
Turn-on delay time
t
Rise time
r
Turn-off delay time
t
Fall time
f
DD
= 4.7Ω, VGS= 4.5V
R
G
(see Figure 12)
V
= 15V, ID= 25A,
DD
= 4.7Ω, VGS= 4.5V
R
G
(see Figure 12)
15
125
14 45
ns ns
ns ns
Table 6. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
I
SDM
V
SD
Q
I
RRM
Q
I
RRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Source-drain current
SD
Source-drain current
(1)
(pulsed)
(2)
Forward on voltage
t
rr
Reverse recovery time Reverse recovery charge
rr
Reverse recovery current
t
rr
Reverse recovery time Reverse recovery charge
rr
Reverse recovery current
I
SD
I
SD
V
(see Figure 17)
I
SD
V
(see Figure 17)
= 20A, VGS=0
= 40A, di/dt = 100A/µs,
= 10 V, Tj = 25°C
DD
= 40A, di/dt = 100A/µs,
= 10V, Tj= 150°C
DD
26
15.6
1.2
26.4
18.1
1.4
40
160AA
1.3 V
ns
nC
A
ns
nC
A
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Page 6
Electrical characteristics STD50N03L - STD50N03L-1

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance
Figure 3. Output characteristics Figure 4. Transfer characteristics
Figure 5. Normalized B
vs temperature Figure 6. Static drain-source on resistance
VDSS
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Page 7
STD50N03L - STD50N03L-1 Electrical characteristics
Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Figure 10. Normalized on resistance vs
temperature
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Page 8
Test circuit STD50N03L - STD50N03L-1

3 Test circuit

Figure 12. Switching times test circuit for
resistive load
Figure 14. Test circuit for inductive load
switching and diode recovery times
Figure 13. Gate charge test circuit
Figure 15. Unclamped Inductive load test
circuit
Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform
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Page 9
STD50N03L - STD50N03L-1 Buck converter
Appendix A Buck converter
Figure 18. Power losses estimation
The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature.
The low side (SW2) device requires:
■ Very low R
■ Small Qgls to reduce the gate charge losses
■ Small Coss to reduce losses due to output capacitance
■ Small Qrr to reduce losses on SW1 during its turn-on
■ The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
■ voltage to avoid the cross conduction phenomenon;
to reduce conduction losses
The high side (SW1) device requires:
■ Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the
gate
■ Small Qg to have a faster commutation and to reduce gate charge losses
Low R
to reduce the conduction losses.
9/16
Page 10
Buck converter STD50N03L - STD50N03L-1
Table 7. Power losses
High side switching (SW1) Low side switch (SW2)
P
conduction
P
switching
Recovery
(1)
P
diode
Conduction Not applicable
P
1. Dissipated by SW1 during turn-on
gate(QG
P
Qoss
)
Table 8. Paramiters meaning
2 LDS(on)SW1
+
gd(SW1)gsth(SW1)in
Not applicable
ggg(SW1)
oss(SW1)in
2
δ
*I *R
I
L
*f*)Q(Q*V
I
g
Zero Voltage Switching
f*V*Q
f*Q*V
2 LDS(on)SW2
rr(SW2)in
deadtimeLf(SW2)
gggls(SW2)
oss(SW2)in
)1(*I *R
δ
−
f*Q*V
f*t*I*V
f*V*Q
f*Q*V
2
Parameter Meaning
d Duty-cycle
Q
gsth
Q
gls
P
conduction
P
switching
P
diode
P
gate
P
Qoss
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Gate drive losses
Output capacitance losses
10/16
Page 11
STD50N03L - STD50N03L-1 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com
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Page 12
Package mechanical data STD50N03L - STD50N03L-1
0068771-E
TO-251 (IPAK) MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
mm inch
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A3 0.7 1.3 0.027 0.051
B 0.64 0.9 0.025 0.031
B2 5.2 5.4 0.204 0.212
B3 0.85 0.033
B5 0.3 0.012
B6 0.95 0.037
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 15.9 16.3 0.626 0.641
L 9 9.4 0.354 0.370
L1 0.8 1.2 0.031 0.047
L2 0.8 1 0.031 0.039
H
C
A
C2
D
E
= =
L2
B2
= =
12/16
A1
L
B3
B6
B
2
1 3
L1
B5
A3
G
= =
Page 13
STD50N03L - STD50N03L-1 Package mechanical data
DPAK MECHANICAL DATA
DIM.
A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035 b4 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244 D1 5.1 0.200
E 6.4 6.6 0.252 0.260 E1 4.7 0.185
e 2.28 0.090
e1 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397
L 1 0.039
(L1) 2.8 0.110
L2 0.8 0.031 L4 0.6 1 0.023 0.039
R 0.2 0.008 V2 0° 8° 0° 8°
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
0068772-F
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Page 14
Packaging mechanical data STD50N03L - STD50N03L-1

5 Packaging mechanical data

DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM.
A 330 12.992
B 1.5 0.059
C 12.8 13.2 0.504 0.520
D 20.2 0.795
G 16.4 18.4 0.645 0.724
N 50 1.968
T 22.4 0.881
mm inch
MIN. MAX. MIN. MAX.
TAPE MECHANICAL DATA
DIM.
A0 6.8 7 0.267 0.275
B0 10.4 10.6 0.409 0.417
B1 12.1 0.476
D 1.5 1.6 0.059 0.063
D1 1.5 0.059
E 1.65 1.85 0.065 0.073
F 7.4 7.6 0.291 0.299
K0 2.55 2.75 0.100 0.108
P0 3.9 4.1 0.153 0.161
P1 7.9 8.1 0.311 0.319
P2 1.9 2.1 0.075 0.082
R 40 1.574
W 15.7 16.3 0.618 0.641
mm inch
MIN. MAX. MIN. MAX.
14/16
BASE QTY BULK QTY
2500 2500
Page 15
STD50N03L - STD50N03L-1 Revision history

6 Revision history

Table 9. Revision history
Date Revision Changes
31-Jul-2006 1 Initial release.
27-Oct-2006 2 Modified Figure 1.: Safe operating area on page 6
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Page 16
STD50N03L - STD50N03L-1
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