This product utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology.
This is suitable for the most demanding DC-DC
converter application where high efficiency is to
be achieved.
vs temperatureFigure 6.Static drain-source on resistance
VDSS
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Page 7
STD50N03L - STD50N03L-1Electrical characteristics
Figure 7.Gate charge vs gate-source voltage Figure 8.Capacitance variations
Figure 9.Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Figure 10. Normalized on resistance vs
temperature
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Page 8
Test circuitSTD50N03L - STD50N03L-1
3 Test circuit
Figure 12. Switching times test circuit for
resistive load
Figure 14. Test circuit for inductive load
switching and diode recovery times
Figure 13. Gate charge test circuit
Figure 15. Unclamped Inductive load test
circuit
Figure 16. Unclamped inductive waveformFigure 17. Switching time waveform
8/16
Page 9
STD50N03L - STD50N03L-1Buck converter
Appendix A Buck converter
Figure 18. Power losses estimation
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
The low side (SW2) device requires:
■ Very low R
■ Small Qgls to reduce the gate charge losses
■ Small Coss to reduce losses due to output capacitance
■ Small Qrr to reduce losses on SW1 during its turn-on
■ The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
■ voltage to avoid the cross conduction phenomenon;
to reduce conduction losses
DS(on)
The high side (SW1) device requires:
■ Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the
gate
■ Small Qg to have a faster commutation and to reduce gate charge losses
Low R
to reduce the conduction losses.
DS(on)
9/16
Page 10
Buck converterSTD50N03L - STD50N03L-1
Table 7.Power losses
High side switching (SW1)Low side switch (SW2)
P
conduction
P
switching
Recovery
(1)
P
diode
ConductionNot applicable
P
1. Dissipated by SW1 during turn-on
gate(QG
P
Qoss
)
Table 8.Paramiters meaning
2
LDS(on)SW1
+
gd(SW1)gsth(SW1)in
Not applicable
ggg(SW1)
oss(SW1)in
2
δ
*I *R
I
L
*f*)Q(Q*V
I
g
Zero Voltage Switching
f*V*Q
f*Q*V
2
LDS(on)SW2
rr(SW2)in
deadtimeLf(SW2)
gggls(SW2)
oss(SW2)in
)1(*I *R
δ
−
f*Q*V
f*t*I*V
f*V*Q
f*Q*V
2
ParameterMeaning
dDuty-cycle
Q
gsth
Q
gls
P
conduction
P
switching
P
diode
P
gate
P
Qoss
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Gate drive losses
Output capacitance losses
10/16
Page 11
STD50N03L - STD50N03L-1Package mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at : www.st.com
27-Oct-20062Modified Figure 1.: Safe operating area on page 6
15/16
Page 16
STD50N03L - STD50N03L-1
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