The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding application.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh™ products.
Rthj-caseThermal resistance junction-case max 2.78°C/W
Rthj-ambThermal resistance junction-ambient max 100°C/W
T
J
Maximum lead temperature for soldering purpose300°C
Table 3.Avalanche characteristics
SymbolParameterValueUnit
I
AS
E
AS
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj Max)
Single pulse avalanche energy
(starting Tj=25°C, Id=Iar, Vdd=50V)
1.6A
110mJ
3/16
Page 4
Electrical ratingsSTD2NK70Z - STD2NK70Z-1
Table 4.Gate-source zener diode
SymbolParameterTest ConditionMin.Typ.Max Unit
BV
Gate-source
GSO
breakdown voltage
Igs= ± 1mA (open drain)30A
1.1 Protection features of gate-to-source zener diodes
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
4/16
Page 5
STD2NK70Z - STD2NK70Z-1Electrical characteristics
2 Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 5.On/off states
SymbolParameterTest conditionsMin.Typ.Max.Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source breakdown
voltage
Zero gate voltage drain
current (VGS = 0)
Gate body leakage current
= 0)
(V
DS
Gate threshold voltage
Static drain-source on
resistance
= 1mA, VGS= 0
I
D
V
= Max rating,
DS
V
= Max rating @125°C
DS
= ±20V
V
GS
= VGS, ID = 50µA
V
DS
VGS= 10V, ID= 0.8A
700V
1
50
±10nA
33.754.5 V
67Ω
Table 6.Dynamic
SymbolParameterTest conditionsMin.Typ.Max.Unit
(1)
g
fs
C
C
C
C
oss eq
t
d(on)
t
d(off)
Q
Q
Q
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. C
inceases from 0 to 80% V
Forward transconductance
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
(2)
Equivalent output
.
capacitance
Turn-on delay time
t
Rise time
r
Turn-off delay time
Fall time
t
f
g
Total gate charge
Gate-source charge
gs
Gate-drain charge
gd
is defined as a constant equivalent capacitance giving the same charging time as C
Figure 5.TransconductanceFigure 6.Static drain-source on resistance
7/16
Page 8
Electrical characteristicsSTD2NK70Z - STD2NK70Z-1
Figure 7.Gate charge vs gate-source voltage Figure 8.Capacitance variations
Figure 9.Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Figure 10. Normalized on resistance vs
temperature
Figure 12. Normalized B
vs temperature
VDSS
8/16
Page 9
STD2NK70Z - STD2NK70Z-1Electrical characteristics
Figure 13. Maximum avalanche energy vs
temperature
9/16
Page 10
Test circuitSTD2NK70Z - STD2NK70Z-1
3 Test circuit
Figure 14. Switching times test circuit for
resistive load
Figure 16. Test circuit for inductive load
switching and diode recovery times
Figure 15. Gate charge test circuit
Figure 17. Unclamped Inductive load test
circuit
Figure 18. Unclamped inductive waveformFigure 19. Switching time waveform
10/16
Page 11
STD2NK70Z - STD2NK70Z-1Package mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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