Page 1
STB80NF10
N-CHANNEL 100V - 0.012Ω - 80A D2PAK
LOW GATE CHARGE STripFET™ POWER MOSFET
TYPE V
DSS
STB80NF10 100 V < 0.015
■ TYPICAL R
■ EXCEPTIONA L dv/d t CAPABILITY
■ 100% AVALANCHE TESTED
■ APPLICATION ORIENTED
(on) = 0.012Ω
DS
R
DS(on)
I
D
Ω
80 A
CHARACTERIZATION
DESCRIPTION
This Power MOSFET series realized with STM icroelectronics unique STripFET process has specifically been designed to minimize input capacitance and
gate charge. It is therefore suitable as primary
switch in advanced high-efficiency isolated D C-DC
converters for T el ecom and Computer application. It
is also intended for any application with low gate
charge drive requirements.
APPLICATIONS
■ HIGH-EFFICIENCY DC-DC CONVERTERS
■ UPS AND MOTOR CONTROL
3
1
D2PAK
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
(*) Drain Current (continuos) at TC = 25°C
D
I
D
I
DM
P
TOT
dv/dt (1) Peak Diode Recovery voltage slope 9 V/ns
E
AS
T
stg
T
j
(●) Pulse width limited by safe operating area
(*) Limited by Package
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
100 V
100 V
Gate- source Voltage ±20 V
80 A
Drain Current (continuos) at TC = 100°C
(●)
Drain Current (pulsed) 320 A
Total Dissipation at TC = 25°C
50 A
300 W
Derating Factor 2 W/°C
(2)
Single Pulse Avalanche Energy 245 mJ
Storage Temperature –65 to 175 °C
Max. Operating Junction Temperature 175 °C
(1) ISD ≤80A, di/dt ≤300A/µs, VDD ≤ V
(2) Starting Tj = 25°C, ID = 80A, VDD = 50V
(BR)DSS
, Tj ≤ T
JMAX.
1/8February 2001
Page 2
STB80NF10
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 0.5 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
ON
(1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Maximum Lead Temperature For Soldering Purpose 300 °C
Drain-source
ID = 250 µA, VGS = 0 100 V
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ±20V ±100 nA
GS
V
= VGS, ID = 250µA
DS
VGS = 10V, ID = 40 A
234V
0.012 0.015
1µA
10 µA
Resistance
Ω
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 600 pF
Reverse Transfer
Capacitance
ID=40 A
V
DS
D(on)
x R
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
20 S
4300 pF
230 pF
2/8
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STB80NF10
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time 145 ns
Total Gate Charge
Gate-Source Charge 23 nC
Gate-Drain Charge 51 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
d(off)
t
f
t
f
t
c
Turn-off-Delay Time VDD = 50V, ID = 40A,
Fall Time 115 ns
Off-voltage Rise Time
Fall Time (see test circuit, Figure 5) 125 ns
Cross-over Time 185 ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (2)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µs, duty cyc l e 1.5 %.
2. Pulse width li mited by safe operating ar ea.
Source-drain Current 80 A
(1)
Source-drain Current (pulsed) 320 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
= 50V, ID = 40A
DD
R
= 4.7Ω VGS = 10V
G
(see test circuit, Figure 3)
V
= 80V, ID = 80A,
DD
VGS = 10V
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 3)
Vclamp =80V, I
R
=4.7Ω, V
G
GS
=80A
D
= 10V
ISD = 80A, VGS = 0
= 80A, di/dt = 100A/µs,
I
SD
V
= 50V, Tj = 150°C
DD
(see test circuit, Figure 5)
40 ns
140 189 nC
134 ns
111 ns
1.3 V
155 ns
Safe Operating Area Ther m al Imp e d ence
3/8
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STB80NF10
Output Characteristics
Transconductance Static Drain-source On Resistance
Transfer Characteristics
4/8
Capacitance VariationsGate Charge vs Gate-source Voltage
Page 5
Source-drain Diode Forward Characteristics
STB80NF10
Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.
5/8
Page 6
STB80NF10
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/8
Page 7
2
D
PAK MECH ANICAL DATA
STB80NF10
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
A1 2.49 2.69 0.098 0.106
A2 0.03 0.23 0.001 0.009
B 0.7 0.93 0.027 0.036
B2 1.14 1.7 0.044 0.067
C 0.45 0.6 0.017 0.023
C2 1.23 1.36 0.048 0.053
D 8.95 9.35 0.352 0.368
D1 8 0.315
E 10 10.4 0.393
E1 8.5 0.334
G 4.88 5.28 0.192 0.208
L 15 15.85 0.590 0.625
L2 1.27 1.4 0.050 0.055
L3 1.4 1.75 0.055 0.068
mm. inch
M 2.4 3.2 0.094 0.126
R 0.4 0.015
V2 0º8º
3
7/8
1
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STB80NF10
8/8
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of use of such informa tion n or for an y infring ement of patent s or other rig hts of third part ies which may resu lt from its use . No l i cen se i s
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subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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