Datasheet STA002 Datasheet (SGS Thomson Microelectronics)

®

FRON T_ END INT ERFACE:

IF input carrier frequency: f = 1.84 MHz
Single internal 6 bit A/D converter
QPSK demodulation
Input symbol frequency: Fs = 1.84 Msymbols/s
Digital Nyquist root filter:

- roll-off value of 0.4
Digital carrier loop:

- on-chip quadrature demodulator and tracking
loop

- lock detector

- C/N indicator
Digital timing recovery:

- internal timing error evaluation, filter and
correction

Digital AGC:

- internal signal power estimation and filter

- output control signal for AGC (1 bit PWM)

FORWARD ERROR CORRECTION :

Inner decoder:

- Viterbi soft decoder for convolutional codes,
constraint length M=7, Rate 1/2

Deinterleaver block
Outer decoder:

- Reed-Solomon decoder for 32 parity bytes;
correction of up to 16 byte errors

- Block lengths: 255

- Energy dispersal descrambler

BACK_END INTERFACE:

Broadcast Channel selection
Audio Service Component selection to MPEG

decoder
Service Component selection

CONTROL:

I2C serial Bus control interface

STA002

STARMAN CHANNEL DECO DE R

TQFP44

DECRYPTION:

WES scheme supported

DESCRIPTION

Designed for World Space satellites digital audio
receivers, the STA002 Digital Receiver Front-end
integrates all the blocks needed to demodulate
incoming digital satellite audio signals from the
tuner: analog to digital converter, QPSK demodu­lator, signal power estimator, automat ic gain con­trol, Viterbi decoder, deinterleaver, Reed-Solo­mon decoder and energy dispersal descrabler. Its
advanced error correction functions guarantees a
low error rate even with small low gain receiver
antennas.
Additional functions include the selection of
broadcast channel, service components and
audio components for source decoding:

- The MPEG Audio bitstream is provided at the
serial audio output port.

- The Broadcast Channel is provided to the serial
data output port.

- The Service Component is provided at the SC
output interface.

World Space encryption scheme is supported for
pay programs and paging.

January 2002

1/43

STA002

Fig. 1: Channel Decoder Block Diagram

LOCK

AGC

RXI

RNXI

M_CLK

A/D

PLL/CLOCK

DISTRIBUTION

MICROPROCESSOR

INTRRESET MINTR

Fig. 2: Pin Connection

QPSK

FRAME

SYNC.

INTERFACE

SCL

TDM_CLK

SDA

TDM

TDM FRAME

CONTROLLER

PRC

MANAGEMENT

BC_CLK

TSCC

MANAGEMENT

VITERBI

BC

MANGEMENT

DE-INTERLEAVER

BC

DATA

INTERFACE

SC

DATA

INTERFACE

SC

SOURCE

DECODER

INTERFACE

REED

SOLOMON

D96AU541C

BCCK

BCDO

BCSYNC

BCDIN

SCEN

SCDO

SCCK

SCK

SDO

SEN

BC/TSCC

2/43

TEST 1

AGC

VDD

A_VDD

RXI

NRXI

A_GND

GND

M_CLK

CLK_TEST

TEST 2

SCEN

VDD

BCDO

BCCK

TEST 8

TEST 9

SCDO

GND

SCCK

VDD

GND

44 43 42 41 3940 38 37 36 35 34

1
2
3
4
5
6
7
8
9

10

12 13 14 15 16

VDD

LOCK

TEST 3

171118 19 20 21 22

SCL

SDA

GND

INTR

GND

VDD

RESET

TEST 4

33
32
31
30
29
28
27
26
25
24
23

TEST 7
BCDIN
BCSYNC
GND
SDO
SCK
SEN
VDD
TEST 6
MINTR
TEST 5

D97AU671A

PIN DESCRIPTION

Type Pin Name Type Function PAD Description

1, 11, 12 TEST (1:3) I Test Pin CMOS Input Pad Buffer with Pull-Down

22 23 , 25 , 3 3, 3 4 , 44 TEST

2 AGC O AGC Output CMOS 2mA Output Driver

3, 14, 21,

VDD Positive Supply Voltage

26, 38, 40

4 A_VDD Analog Positive Supply Voltage
5 RXI I IF Signal Input Analog Pad Buffer
6 NRXI I IF Signal Input Analog Pad Buffer
7 A_GND Analog Ground

9 M_CLK I Master Clock Analog Pad Buffer with Comparator
10 CLK_TEST Not Connected CMOS Input Pad Buffer
13 LOCK O Carrrier Lock Indicator CMOS 2mA Output Driver
15 SDA I/O Data + ACK CMOS Schmitt Trigger Bdir Pad Bufer
16 SCL I Serial Clock CMOS Input Pad Schmitt Triggered

8, 17, 19,

GND Negative Supply Voltage

30, 35, 42

18 INTR O Interrupt CMOS 2mA Output Driver
20 RESET I Master Reset CMOS Input Pad Buffer with Pull-Up
24 MINTR O MPEG Interrupt CMOS 2mA Output Driver
27 SEN O MPEG Enable CMOS 2mA Output Driver
28 SCK O MPEG Clock CMOS 2mA Output Driver
29 SDO O MPEG Bit Output CMOS 2mA Output Driver
31 BCSYNC O Broadcast Channel Sync CMOS 2mA Output Driver
32 BCDIN I Broadcast Channel Data Input CMOS Input Pad Buffer
36 BCCK O Broadcast Channel Clock CMOS 2mA Output Driver
37 BCDO O Broadcast Channel Data Output CMOS 2mA Output Driver
39 SCEN O Service Component Enable CMOS 2mA Output Driver
41 SCCK O Service Component Clock CMOS 2mA Output Driver
43 SCDO O Service Component Data Output CMOS 2mA Output Driver

Note: pin 1, 11, 12 and 22 must be connected to ground in functional mode.

I Test Pin

(4:9)

STA002

THERMAL DATA

Symbol Parameter Value Unit

R

th j-amb

Thermal resistance Junction to Ambient 85 °C/W

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DD

V

i

V

O

T

stg

T

oper

Power Supply -0.3 to 4 V
Voltage on Input pins -0.3 to VDD +0.3 V
Voltage on output pins -0.3 to VDD +0.3 V
Storage Temperature -40 to +150 °C
Operative ambient temp -20 to +85 °C

3/43

STA002

ELECTRICAL CHARACTERISTICS:

DD

= 3.3V ±0.3V; T

V

amb

= 0 to 70°C; Rg = 50Ω unless otherwise

specified

DC OPERATING CONDITIONS

Symbol Parameter Value

V

T

GENERAL INTERFACE ELECTRICAL CHARACTER IST ICS

Power Supply Voltage 2.7 to 3.6V

DD

Operating Junction Temperature -20 to 125°C

j

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

I

IL

Low Level Input Current

Vi = 0V -10 10

A1

µ

Without pull-up device

I

IH

High Level Input Current

Vi = V

DD

-10 10

A1

µ

Without pull-up device

V

esd

The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress

Note 1 :

on the pin.

Human Body Model.

Note 2:

Electrostatic Protection Leakage < 1µA 2000 V 2

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

V

IL

V

IH

V

ol

V

oh

Low Level Input Voltage 0.2*V
High Level Input Voltage 0.8*V
Low Level Output Voltage I

= Xma 0.4V V 1, 2

ol

High Level Output Voltage 0.85*V

DD

DD

DD

V
V

V 1, 2

Takes into account 200mV voltage drop in both supply lines.

Note 1:

X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.

Note 2:

PULL_UP & PULL_DOWN CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

I

pu

Pull-up current Vi = 0V -25 -66 -125

IpuPull-up current Vi = V

RpuEquivalent Pull-up

Vi = 0V 50 k

DD

25 66 125

A1

µ

A1

µ

Ω

Resistance

R

pu

Equivalent Pull-down

Vi = V

DD

50 k

Ω

Resistance

Min. condition: V

Note 1:

Max. condition: V

DD

= 2.7V, 125°C Min process

DD

= 3.6V, -20°C Max.

M_ CLK Electrical Characteristics (Pin number 9)

Symbol Parameter Min. Typ. Max. Unit

V

il

V

ih

V

ref

Low Level Input Voltage VDD -1.7 V
High Level Input Voltage VDD -0.9 V
Input Reference Voltage VDD -1.3 V

POWER DISSIPATION

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

PD Power Dissipation

= 3V

@ V

DD

M_CLK = 39,0269MHz 80 mW

4/43

Fig. 3: Test Circuit

STA002

VDD

VDD

VDD

VDD

VDD

VDD

AVDD

TEST1

RXI

NRXI

M_CLK

TEST_CLK

TEST2

100nF

100nF

100nF

100nF

100nF

100nF

3

8

14

17

21

19

26

30

38

35

40

42

4
7

1
5
6
9
10
11

44
34 TEST8
33 TEST7
32 BCDIN
25 TEST6
23 TEST5
22 TEST4
20 RESET
16 SCL
15 SDA
12 TEST3

200

43

200

41 SCCK

200

39 SEN

200

37 BCDO

200

36 BCCK

200

31

200

29 SDI

200

28 SCK

200

27 SEN

200

24 MINTR

200

18 INTR

200

2

200

13

TEST9

SCDI

BCSYNC

AGC

LOCK

VDD

4.7µF 4.7µF100nF 100nF 100nF 100nF 100nF

Figure 4.

OUTPUT

V

SS

Test Load Circuit

C

L

V

SS

V

SS

V

DD

I

OL

V

REF

I

OH

D98AU967

AVDD

4.7µF 4.7µF100nF

AV

SS

AV

SS

100nF 100nF 100nF 100nF

AV

SS

D99AU1011

Test Load

Output I

OL

SDA 5mA 100pF 3.6V
Other Outputs 100µA 100µA 100pF 1.5V

I

OH

C

L

V

REF

5/43

STA002

FUNCTIONAL DESCRIPTION
The STA002 integrates all the functions needed

to demodulate the signal coming from the RF FE;
with reference to the block diagram (Fig 1),
STA002 includes the following functions:

Microprocessor interface
Data transmission from microcontroller to the de-

vice takes place through the 2 wires (SDA and
SCL) I2C bus interface. STA002 acts always as a
slave in all its communications.

Interface to the Front-end
This block receives from the RF front-end the

QPSK modulated signal, centered at 1.84 MHz
(2nd IF frequency). This signal is over sampled
using the Master Clock and converted to digital
on 6 bits in 2’s complement format. The same fre­quency is also used to provide the clock signal for
the QPSK demodulator block.

QPSK
This block is composed by:

- AGC1

- quadrature demodulator

- carrier recovery

- timing recovery

- frequency sweep generator

- AGC2

- lock indicator

- carrier to noise estimator
To assure flexibility and to cover different working

conditions most of the parameters of each func­tion can be programmed through the I2C inter­face.

TDM Demultiplexer
The TDM frame is divided into 3 fields.
The first is the Master Frame Preamble (MFP)

which contains the synchronisation word. The
second, the Time Slot Control Channel (TSCC),
contains information about the or ganiz ation of the
Prime Rate Channel data which follows. The
third, is the data field; it contains 96 Prime Rate
Channels of 16 Kbit/s each; up to 8 Prime Rate
Channels are grouped into one Broadcast Chan­nel.

The TDM demultiplexer executes the extraction
and decoding of one Broadcast Channel from the
TDM stream, according to the instructions com­ing from the microcontroller. The decoding flow is
the following:

- TDM synchronization
The master frame synchronization block receives

the demodulated symbol stream from the QPSK
demodulator and performs the alignment detect­ing the Master Frame Preamble.

The known syncronization word is also used to
correct the phase ambiguity intrinsic in QPSK de­modulation.

- TSCC extraction
The information of the Prime Rate Channels to

Broadcast Channels allocation are contained in
the TSCC field which is synchronised with the
MFP.

In this stage all the information related to the
TSCC are extracted and made available for the
microcontroller via the I2C interface.

- PRC extraction and BC recovery
This block, after the Broadcast Channel (BC) se-

lection, performs the extrac tion and synchronisa­tion of the Prime Rate Channels (PRC) belonging
to the selected BC.

The extracted PRCs are aligned and grouped into
one BC data stream.

- FEC decoder
The extracted BC is decoded using a concate-

nated Forward Error Correction approach.
The FEC circuitry utilizes three error correction

stages: a rate 1/2 Viterbi decoder, a 255x4 bytes
convolutional deinterleaver and a 255/223 Reed
Solomon decoder.

The RS input blocks are 255 bytes long with 32
parity bytes.

Up to 16 errored bytes can be fixed in each RS
block.

BC demultiplexer
Every BC contains up to 8 Service Components;

the Service Control Header (SCH) field contains
all the information related to the organization of
the Service Components. This stage provides the
extraction of the SCH from the BC.

The SCH is available through I2C bus to the mi­crocontroller for the selection of the desired Audio
Service Component, which is then supplied di­rectly to the MPEG Source decoder via the audio
Service Component Interface.

DEVICE OPERATION

2

1. I

C BUS SPECIFICATION

The STA002 supports the I2C protocol. This pro­tocol defines any device that sends data on to the
bus as a transmitter and any device that reads
the data as a receiver. The device that controls
the data transfer is known as the master and the
others as the slave. The master will always initi­ate the transfer and will provide the serial clock

6/43

STA002

for synchronisation. The STA002 is always a
slave device in all its communications.

COMMUNICATION PROTOCOL

1. 1

1.1.0 Data transition or change
Data changes on the SDA line must only occur

when the SCL clock is low. SDA transitions while
the clock is high are used to identify START or
STOP condition.

1.1.1 Start condition
START is identified by a high to low t ransition of

the data bus SDA signal while the clock signal
SCL is stable in the high state. A START condi­tion must precede any command for data transfer.

1.1.2 Stop condition
STOP is identified by low to high transition of the

data bus SDA signal while the clock signal SCL is
stable in the high state. A STOP condition termi­nates communications between STA002 and the
bus master.

1.1.3 Acknowledge bit
An acknowledge bit is used to indicate a success-

ful data transfer. The bus transmitter, either mas­ter or slave, will r elease the SDA bus aft er send­ing 8 bits of data.

During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.

Some registers do not give acknowledge when
the data is not available.

(RW; set to 1 in read mode and to 0 in write
mode). After a START condition the STA002
identifies on the bus the device address and if
matching it will acknowledges the identification on
SDA bus during the 9th bit time.

The following 2 bytes after t he device identifica­tion byte are the internal space address.

1.3 WRITE OPERATION (see fig. 5)
Following a START condition the master sends a

device select code with the RW bit set to 0.
The STA002 gives the acknowledge and waits for

the 2 bytes of internal address. The least signifi­cant 10 bits of t he 2 bytes address provides ac­cess to any of the internal registers. The most
significant bit means incremental mode (1 =
autoincremental, 0 = no) and the other bits are
set to zero.

After the receiption of each of the internal bytes
address the STA002 again responds with an ac­knowledge.

1.3.1 Byte write
In the byte write mode the master sends one data

byte and this is acknowledged by STA002. The
master then terminates the transfer by generating
a STOP condition.

1.3.2 Multibyte write
The multibyte write mode can start from any inter-

nal address. The master sends the data and each
one is acknowledged by t he STA002. The trans­fer is terminated by the master generating a
STOP condition.

1.1.4 Data input
During the data input the STA002 samples the

SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can change only when the SCL line
is low.

1.2 DEVICE ADDRESSING
To start communication between the master and

the STA002, the master must initiate with a start
condition. Following this the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.

The 7 most significant bits are the device address
identifier, corresponding to the I2C bus definition.
For the STA002 these are fixed as 1101010.

The 8th bit (LSB) is the read or write operation bit

1.4 READ OPERATION (see Fig. 6)

1.4.1 Current byte address read

The STA002 has an internal byte address
counter. Each time a byte is written or read, this
counter, according to the autoincremental bit set­ting, is incremented or not.

For the current byte address read mode, follow­ing a START condition the master sends the de­vice address with the RW bit set to 1. The
STA002 acknowledges this and outputs the byte
addressed by the internal byte address counter.

The counter is then incremented or not depend­ing on the autoincremental bit. The master does
not acknowledge the received byte, but termi­nates the transfer with a STOP condition.

1.4.2 Random byte address read
A dummy write is performed to load the byte ad-

dress into the internal address register.

7/43

STA002

Fig. 5: Write Mode Sequence

BYTE

WRITE

MULTIBYT

WRITE

START

START

DEV

DEV

ACK

RW

ACK

RW

BYTE

BYTE

ACK

ACK

Fig. 6: Read Mode Sequence

CURRENT
ADDRESS

READ

RANDOM
ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

START

START

START

START

ACK

DEV

RW

ACK

DEV

RW

RW=

ACK

HIGH

DEV

ACK

DEV

RW

DATA

BYTE

DATA

BYTE

NO ACK

ACK

ACK

ACK

STOP

ACK

BYTE

DATA

ACK

BYTE

This is followed by another START condition from
the master and the device address repeated with
the RW bit set to 1. The STA002 acknowledges
this and outputs the byte addressed by the inter­nal byte address counter.

The master does not acknowledge the received
byte, but terminates the transfer with a STOP
condition.

BYTE

BYTE

START RW

START RW

ACK

ACK

DEV

DEV

DATA IN

DATA IN

ACK

ACK

ACK

DATA

DATA

DATA

ACK

ACK

NO ACK

NO ACK

ACK

STOP

STOP

STOP

DATA IN

D97AU669

ACK NO ACK

DATA

D97AU670

1.4.3 Sequential address read
This mode can be initiated with either a current

address read or a random address read. How­ever in this case the master does acknowledge
the data byte output and the STA002 continues to
output the next byte in sequence.
To terminate the stream of bytes the master does
not acknowledge the last received byte, but termi­nates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after each byte output.

ACK

STOP

DATA

STOP

1.5 REGISTER MAP (8 BIT REGISTER)

1.5.1 Register address List (by function)

FUNCTION START ADDRESS END ADDRESS

HEX_COD BIN HEX_COD BIN

SCH 000H 0000000000 03FH 0000111111
RFU 040H 0000111111 07FH 0001111111
QPSK 080H 0010000000 09FH 0010011111
RFU 0A0H 0010100000 0FFH 0011111111
SCH_MEM 100H 0100000000 1EBH 0111101011
RFU 1ECH 0111101100 1FFH 0111111111
TDM_MULTIPLEX 200H 1000000000 23FH 1000111111
RFU 240H 1001000000 2FFH 1011111111
TSCC_MEM 300H 1100000000 3C1H 1111000001
RFU 3C2H 1111000010 3FFH 1111111111

8/43

1.5.2 SCH Registers

STA002

HEX_COD DEC_COD REGISTER NAME TYPE

000H 0 BRI_REG & NSC_REG (note 1) R
001H 1 EC_REG (note 1) R
002H 2 AFCI 1_REG (note 1) R
003H 3 AFCI 2_REG (note 1) R
004H 4 SOF_SF_REG (note 1) R
005H 5 ADF1_REG (7:0) (note 1) R
006H 6 ADF1_REG (15:8) (note 1) R
007H 7 ADF2_REG (7:0) (note 1) R
008H 8 ADF2_REG (15:8) (note 1) R

009H 9 ADF2_REG (23:16) (note 1) R
00AH 10 ADF2_REG (31:24) (note 1) R
00BH 11 ADF2_REG (39:32) (note 1) R
00CH 12 ADF2_REG (47:40) (note 1) R
00DH 13 ADF2_REG (55:48) (note 1) R
00EH 14 ADF2_REG (63:56) (note 1) R
00FH 15 SEL_SC_REG R/W 98H
010H 16 IW_REG (7:0) (note 2) W 41H
011H 17 IW_REG (15:8) (note 2) W 42H
012H 18 IW_REG (23:16) (note 2) W 43H
013H 19 IW_REG (31:24) (note 2) W 44H
014H 20 IW_REG(39:32) (note 2) W 45H
015H 21 IW_REG (47:40) (note 2) W 46H
016H 22 IW_REG (55:48) (note 2) W 47H
017H 23 IW_REG (63:56) (note 2) W 48H
018H 24 EM_REG R/W 00H
019H 25 PIWE_REG (7:0) (note 2) R/W 00H
01AH 26 PIWE_REG (15:8) (note 2) R/W 00H
01BH 27 BCIN_DELAY_REG R/W 00H
01CH 28 BC_ALARM_REG R/W 20H
01DH 29 TEST_PURPOSE R/W
01EH 30 RFU
01FH 31 RFU
020H 32 TEST PURPOSE R/W
021H 33 TEST PURPOSE R/W
022H 34 TEST PURPOSE R/W
023H 35 TEST PURPOSE R/W
024H 36 TEST PURPOSE R/W
025H 37 TEST PURPOSE R/W
026H 38 TEST PURPOSE R/W
027H 39 TEST PURPOSE R/W
028H 40 TEST PURPOSE R/W
029H 41 TEST PURPOSE R/W

Note 1: no acknowledge when data is not available
Note 2: when updated all bytes must be written

RESET
VALUE

9/43

STA002

1.5.2 SCH Registers

HEX_COD DEC_COD REGISTER NAME TYPE

02AH 42 TEST PURPOSE R/W
02BH 43 TEST PURPOSE R/W
02CH 44 TEST PURPOSE R/W
02DH 45 TEST PURPOSE R/W
02EH 46 TEST PURPOSE R/W
02FH 47 TEST PURPOSE R/W
030H 48 TEST PURPOSE R/W
031H 49 TEST PURPOSE R/W
032H 50 TEST PURPOSE R/W
033H 51 TEST PURPOSE R/W
034H 52 TEST PURPOSE R/W
035H 53 TEST PURPOSE R/W
036H 54 TEST PURPOSE R/W
037H 55 TEST PURPOSE R/W
038H 56 PIW_RAM (7:0) (note1) W 00H
039H 57 PIW_RAM (15:8) (note1) W 00H
03AH 58 PIW_RAM (23:16) (note1) W 00H
03BH 59 PIW_RAM (31:24) (note1) W 00H
03CH 60 PIW_RAM (39:32) (note1) W 00H
03DH 61 PIW_RAM (47:40) (note1) W 00H
03EH 62 PIW_RAM (55:48) (note1) W 00H
03FH 63 PIW_RAM (63:56) (note1) W 00H

Note 1: when updated all bytes must be written

RESET
VALUE

10/43

1.5.3 QPSK Registers

STA002

HEX_COD DEC_COD REGISTER NAME TYPE

080H 128 QPSK_CONTROL1 R/W 10H
081H 129 QPSK_CONTROL2 R/W 90H
082H 130 AGC1 _REF1 (note 1) R/W 06H
083H 131 AGC1 _REF2 (note 1) R/W 01H
084H 132 AGC1_BETA R/W 00H
085H 133 AGC1_INTG R/W 7FH
086H 134 AGC2 _REF R/W 16H
087H 135 AGC2 _BETA R/W 00H
088H 136 AGC2_INTG R/W 23H
089H 137 CN_CNT R/W FFH
08AH 138 SYMFREQ1 (note 1) R/W D3H
08BH 139 SYMFREQ2 (note 1) R/W 11H
08CH 140 SYMFREQ3 (note 1) R/W 0CH
08DH 141 TIMFLTPAR R/W 48H
08EH 142 TIMINTG R/W 00H
08FH 143 CARFLTPAR R/W 57H
090H 144 IFFREQ1 (note 1) R/W 37H
091H 145 IFFREQ2 (note 1) R/W 1DH
092H 146 IFFREQ3 (note 1) R/W C1H
093H 147 IFFREQ4 (note 1) R/W 00H
094H 148 CARINTG R/W 00H
095H 149 RAMPCTRL R/W 01H
096H 150 CARFREQ1 R
097H 151 CARFREQ2 R
098H 152 CARFREQ3 R
099H 153 FLAG R
09AH 154 RFU
09BH 155 RFU
09CH 156 RFU
09DH 157 RFU
09EH 158 RFU
09FH 159 RFU

Note 1: when updated all bytes must be written

RESET
VALUE

11/43

STA002

1.5.4 SCH_MEM Registers

HEX_COD DEC_COD REGISTER NAME TYPE

100H 256 SC1_LENGHT & SC1_TYPE R
101H 257 SC1_EC & SC1_PT R
102H 258 SC1_PT R
103H 259 LANGUAGE 1 R
104H 260 SC2_LENGHT & SC2_TYPE R
105H 261 SC2_EC & SC2_PT R
106H 262 SC2_PT R
107H 263 LANGUAGE 2 R
108H 264 SC3_LENGHT & SC3_TYPE R
109H 265 SC3_EC & SC3_PT R
10AH 266 SC3_PT R
10BH 267 LANGUAGE 3 R
10CH 268 SC4_LENGHT & SC4_TYPE R
10DH 269 SC4_EC & SC4_PT R
10EH 270 SC4_PT R
10FH 271 LANGUAGE 4 R
110H 272 SC5_LENGHT & SC5_TYPE R
111H 273 SC5_EC & SC5_PT R
112H 274 SC5_PT R
113H 275 LANGUAGE 5 R
114H 276 SC6_LENGHT & SC6_TYPE R
115H 277 SC6_EC & SC6_PT R
116H 278 SC6_PT R
117H 279 LANGUAGE 6 R
118H 280 SC7_LENGHT & SC7_TYPE R
119H 281 SC7_EC & SC7_PT R
11AH 282 SC7_PT R
11BH 283 LANGUAGE 7 R
11CH 284 SC8_LENGHT & SC8_TYPE R
11DH 285 SC8_EC & SC8_PT R
11EH 286 SC8_PT R
11FH 287 LANGUAGE8 R
120H 288 DYNAMIC LABEL R
121H 289 DYNAMIC LABEL R
122H 290 DYNAMIC LABEL R
123H 291 DYNAMIC LABEL R
124H 292 DYNAMIC LABEL R

RESET
VALUE

1E7H 487 DYNAMIC LABEL R
1E8H 488 DYNAMIC LABEL R
1E9H 489 DYNAMIC LABEL R

1EAH 490 DYNAMIC LABEL R
1EBH 491 DYNAMIC LABEL R

Note: no acknowledge when data is not available for all the SCH_MEM registers

12/43

1.5.5 TDM_MULTIPLEX Registers

STA002

HEX_COD DEC_COD REGISTER NAME TYPE

200H 512 TDM_TRSH 1 R/W 4BH
201H 513 TDM_TRSH 2 R/W 43H
202H 514 PRC_TRSH 1 R/W 2AH
203H 515 PRC_TRSH 2 R/W 23H
204H 516 VITERBI_ERROR_CONTROL R/W 00H
205H 517 SP_TRSH 2 R/W 13H
206H 518 PRC_MAXDELAY R/W 06H
207H 519 TDM_ALARM R/W 00H
208H 520 PRC_ALARM R/W 00H
209H 521 BC_SEL 1 (note) R/W 01H
20AH 522 BC_SEL2 (note) R/W 00H
20BH 523 CONTROL R/W 00H
20CH 524 INT_MASK R/W 00H
20DH 525 ERROR_ REG R/W 00H
20EH 526 STATUS REG R
20FH 527 PRC_ACTIVE_REG R
210H 528 PRC_ LOCK_REG R
211H 529 PRC_DELAY_REG R
212H 530 RS_ERROR_CONTROL R/W 00H
213H 531 VIT_ERROR1 R/W
214H 532 VIT_ERROR2 R/W
215H 533 RS_BYTE_ERROR1 R/W
216H 534 RS_BYTE_ERROR2 R/W
217H 535 RS_BLOCK_ERROR R/W
218H 536 TEST_PURPOSE R/W
219H 537 TEST_PURPOSE R/W
21AH 538 TEST_PURPOSE R/W
21BH 539 TEST_PURPOSE R/W
21CH 540 TEST_PURPOSE R/W
21DH 541 TEST_PURPOSE R/W
21EH 542 PLL_INT_REG R/W 00H
21FH 543 TEST_PURPOSE R/W
220H 544 RESERVED R/W 07H
221H 545 RESERVED R/W 1CH
222H 546 RESERVED R/W 4AH
223H 547 RESERVED R/W 03H
224H 548 RESERVED R/W 18H
225H 548 RESERVED R/W 25H
226H 550 RESERVED R/W 2EH
227H 551 RESERVED R/W 3EH
228H 552 RESERVED R/W 18H
229H 553 RESERVED R/W 0DH
22AH 554 RESERVED R/W 18H
22BH 555 RESERVED R/W 12H
22CH 556 RESERVED R/W 0AH
22DH 557 RESERVED R/W 0CH

Note: when updated all bytes must be written

RESET
VALUE

13/43

STA002

1.5.5 TDM_MULTIPLEX Registers (continued)

HEX_COD DEC_COD REGISTER NAME TYPE

22EH 558 RESERVED R 0EH
22FH 559 RESERVED R 12H
230H 560 RESERVED R 32H
231H 561 RESERVED R 0CH
232H 562 RESERVED R 1CH
233H 563 RESERVED R 2FH
234H 564 RESERVED R 0AH
235H 565 RESERVED R 0BH
236H 566 RESERVED R 2AH
237H 567 RESERVED R 09H
23CH 568 TEST_PURPOSE R 09H
23DH 569 TEST_PURPOSE R 09H

237EH 570 TEST_PURPOSE R 09H

1.5.6 TSCC_MEM Registers

HEX_COD DEC_COD REGISTER NAME TYPE

300H 768 TSCW 1 (7:0) R
301H 769 TSCW 1 (15:8) R
302H 770 TSCW 2 (7:0) R
303H 771 TSCW 2 (15:8) R
304H 772 TSCW 3 (7:0) R
305H 773 TSCW 3 (15:8) R
306H 774 TSCW 4 (7:0) R
307H 775 TSCW 4 (15:8) R

RESET
VALUE

RESET
VALUE

3BCH 956 TSCW 95 (7:0) R
3BDH 957 TSCW 95 (15:8) R
3BEH 958 TSCW 96 (7:0) R

3BFH 959 TSCW 96 (15:8) R
3C0H 960 TSCW ID (7:0) R
3C1H 961 TSCW ID (15:8) R

2. IF INTERFACE
The Master Clock (M_CLK) is the source of all

the STA002 internal timings.

the VCO.
The PLL output frequency F

2

C interface according to the PLL_INT_REG.

I

M_CLK is internally divided to drive the A/D con­verter and to provide the clock signal for the
QPSK block.

The IF input signal, center ed at 1. 84MHz, is over-

ck

sampled at a frequency F

of M_CLK/4 or

M_CLK/2 according to STA002 presettings.

2.1 PLL
This fully integrated PLL includes the phase/fre-

quency detector, the charge pump, the f ilter and

14/43

Reg. name: PLL_INT_REG
Internal address: 21E H
Reset Value : 00H
Type: R/W

MSB LSB

X X b5 b4 b3 b2 b1 b0

Description: PLL and INTR pin control register

ck

can be selected via

b1 b0 PLL output clock (ADC input)

0
0
1
1

b5 b4 INTR pin control

0
0
1
1

0

M_CLK (pin 9)

1

2XM_CLK (pin9)

0

Test purpose

1

Test purpose

Normal function (from ERROR_REG)

0

BC_LOCK signal on INTR pin

1

MFP_LOCK signal on INTR pin

0

PRCP_ALL_LOCK on INTR pin

1

b3, b2: Test purpose

2.2 A/D CONVERTER
This block performs the analog to digital conver-

sion of the incoming IF input signal.
The ADC has a resolution of 6 bit and is based

on the so called Half Flash architecture to reduce
both area and power consumption.

The sampling rate depends on the M_CLK (Mas­ter Clock) frequency and on the PLL presetting.

3. QPSK DEMODULATOR

3.1 QUADRATURE DEMODULATOR
The final base-band demodulation is performed in

this block.
The samples of the IF input signal are multiplied

by the sine and cosine functions to get the two in­phase (I) and quadrature (Q) components of the
QPSK signal. The phase ambiguity inherent in
QPSK is solved in the frame synchronisation part.

A programmable bit allows to multiply by -1 the
quadrature component in order to accomodate
QPSK modulation with another convention of ro­tation sense (this is equivalent to a permutation of
I and Q components).

The sine and cosine functions are generated by
an NCO using a phase accumulator and a look­up table.

3.2. INTERPOLATOR NYQUIST FILTER
The I and Q components are filtered by a digital

Nyquist root filter with the following features:
Separate I and Q stream, Fck/Fsym samples per

symbols;
Raised root cosine shape with roll-off factor of

40%;
Separate I and Q output stream, 1 sample per

symbol.
This filter performs both the Nyquist filter function

(matched with the one in the transmission side)
and the interpolation function to compute the opti­mum output sample.

STA002

3.3. TIMING RECOVERY
The timing loop is completely implemented digi-

tally and comprises the timing det ector working at
symbol rate, a loop filt er, the t iming NCO and the
Nyquist/interpolator filters.
The loop is controlled by two parameters, al­pha_tmg and beta_tmg contained in the
TIMFLTPAR register.

3.3.1 Timing loop registers

Timing loop filter parameter register
(TIMFLTPAR)

Internal address: 8D H
Reset Value: 48H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

alpha_tmg beta_tmg

Timing frequency registers (TIMINTG)
Internal address: 8E H
Reset Value: 0AH

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

signed number

The value of this register, when the system is
locked, is an image of the frequency offset.

Timing NCO frequency setting (SYMFREQ)
Internal address: 8C H 8B H 8A H
Reset Value : 0CH 11H D3H

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SYMFR EQ3

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

SYMFR EQ2

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

SYMFR EQ1

This register is divided into three bytes. The LSB
byte is named SYMFREQ1, the MSB is named
SYMFREQ3.

15/43

STA002

The 22 bits value to be written into this register is
given by:

Phase Detector Gain

SYMFREQ = INT



sym



F





22

2



ck



F

for example if
M_CLK = 39,02687179MHz, Fck = M_CLK/4

SYMFREQ = 790995 = (C11D3)HEX

which is the Reset Value.

3.3.2 Loop equations

This timing loop is a second order one. The natu­ral frequency and the damping factor may be cal­culated by the following formulas:

Ko KD

√

=

f

n

m

β ⋅

2

π

where β is programmed by the timing register
beta_tmg:

b = 2

beta_tmg-14

⋅ Fsym (Fsym = 1.84MHz)

where m is the reference value of the AGC2 loop

D

(see AGC2_REF register), K

is the timing detec-

tor gain and Ko is the constant of the timing NCO:

2

π

K

F

=

o

ck

22

2

The damping factor is:

ξ =

α

√

2

K

o KD

β

m

⋅

where α is programmed by the timing register al­pha_tmg:

alpha_tmg

α = 2

beta_tmg can only take value from 0 to 15; if
beta_tmg is 0 the loop reduces to a first order
one.
Alpha_tmg can take any value from 0 to 7. If both
alpha_tmg and beta_tmg are 0 then the timing
loop is open.

The timing phase detector gain K

depends on

D

the signal to noise ratio and is given in the follow­ing figure:

(see par. 3.8 for the C/N definition)

= 0.356 for a noise free input signal.

K

D

The natural frequency and the damping factor
can be rewritten as:

K

D

D

⋅ 2

⋅

D97AU724

beta_tmg

alpha_tmg

2

(Kd)

0.3

0.2

0.1

0

0 5 10 C/N(dB)

√

F

CK

F

CK

√

m

⋅

m ⋅ K

 

√

beta_tmg

2

ξ =

f

= 2.064

n

0.0577

√

Table 1 gives the natural frequency and the
damping factor for the nominal amplitude m = 22,

D

= 0.356 and M_CLK = 39.02687179MHz.

K

D

In high noise co nditi ons the valu e of K

may be
reduced up to 25% of its nominal (noise free)
value ; it is recomme nded t o sta rt with a d amping
factor, calculated without noise, greater than the
usual value of 0.7.

3.4. CARRIER RECOVERY
Also the carrier recovery is completely imple-

mented digitally and comprises a phase and fre­quency detector, a loop filter, a NCO and a
sine/cosine look-up table.

The carrier NCO is the local oscillator for the in­put quadrature demodulator.

3.4.1 Carrier loop registers
Carrier loop filter parameter register

(CARFLTPAR)
Internal address: 8F H
Reset Value: 57H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

alpha_car beta_car

16/43

STA002

TABLE 1. Timing loop parameters (m= 22; K

beta_tmg 012345678910

fn(Hz) N A 25 36 51 72 102 144 204 288 408 577

alpha_tmg

NA

0

NA

1

NA

2

NA

3

NA

4

NA

5

NA

6

NA

7

NA

0.71

1.42

2.85

5.70

11.4

22.8

45.6

= 0.356; M_CLK = 39.02687179MHz)

D

NA

0.50

1.01

2.01

4.03

8.06

16.1

32.2

0.36

0.71

1.42

2.85

5.70

11.4

22.8

Carrier frequency registers (CARINTG)
Internal address: 94 H
Reset Value: 00H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

signed number

This register is formed by the 8 integrator MSBs
of the carrier loop filter.
The value of this register, when the system is
locked, is an image of the frequency offset.
It may be read or written at any time by the micro.
When written the integrator LSBs are reset.

Damping factor

NA

NA

0.25

0.50

1.01

2.01

4.03

8.06

16.1

NA

0.18

0.36

0.71

1.42

2.85

5.70

11.4

NA

0.13

0.25

0.50

1.01

2.01

4.03

8.06

NA

0.09

0.18

0.36

0.71

1.42

2.85

5.70

NA

0.06

0.13

0.25

0.50

1.01

2.01

4.02

The 26 bits value to be written into this register is
given by:

IFFREQ = INT

IF



26

2



F

ck



For example if M_CLK = 39.02687179MHz,
Fck = M_CLK/4

IFFREQ = 12655927 = (C11D37)

which is the Reset Value.

Actual Carrier Frequency Register (CARFREQ)
Internal address: 96 H, 97 H, 98 H





NA

0.04

0.09

0.18

0.36

0.71

1.42

2.85

NA

0.03

0.06

0.13

0.25

0.50

1.01

2.01

HEX

Carrier NCO frequency setting register (IFFREQ)
Internal address: 93 H 92 H 91 H 90 H
Reset Value : 00H C1H 1DH 37H

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

IFFREQ4

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

IFFREQ3

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

IFFREQ2

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

IFFREQ1
This register is divided into four bytes.

The LSB byte is named IFFREQ1, the MSB is
named IFFRE Q4 .

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

CAR FREQ 3

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

CAR FREQ 2

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

CAR FREQ 1
This register contains the actual carrier frequency

value when the system is locked.
It is divided into 3 registers: CARFREQ3, down to
1 (CARFREQ3 is the MSB).
This register may be read at any time and it is
useful to store the value of t he recovered carrier.
If the system unlocks (due, to a lack of signal
etc.) the carrier NCO could be initialized with this
value to speed-up the tracking process.

3.4.2 Loop parameters
Like the timing loop the carrier loop is a second

17/43

STA002

TABLE 2. Carrier loop parameters (m = 22; K

beta_car 0 1 2 345678910

fn(KHz)

alpha_car Damping factor

NA 0.38 0.54 0.77 1.09 1.54 2.17 3.07 4.35 6.15 8.69

NA

0

NA

1

NA

2

NA

3

NA

4

NA

5

NA

0.67

1.34

2.69

5.37

10.7

= 1.26; M_CLK = 39.02687179MHz)

D

NA

0.47

0.95

1.90

3.80

7.60

0.34

0.67

1.34

2.69

5.37

order system controlled by two parameters, al­pha-car and beta-car, contained in the
CARFLTPAR register.

The natural frequency and the damping factor are
given in the following formulas:

K

m K

β

o

=

f

√

n

D

2

π

where β is programmed by the carrier register
beta_car:

β

= 2

beta_car-4

Fsym (Fsym = 1.84MHz)

⋅

m is the reference value of the AGC2 loop (see
AGC2_REF register), K

D

is the phase detector

gain and Ko is the constant of the carrier NCO:

NA

NA

0.24

0.47

0.95

1.90

3.80

Phase Detector Gain

(Kd)

1.2

1

0.8

0.6

0

NA

0.17

0.34

0.67

1.34

2.69

NA

0.12

0.24

0.47

0.95

1.90

0 5 10 C/N(dB)

NA

0.08

0.17

0.34

0.67

1.34

NA

0.06

0.12

0.24

0.47

0.95

NA

0.04

0.08

0.17

0.34

0.67

D97AU725

NA

0.03

0.06

0.12

0.24

0.47

2

π

K

=

F

o

CK

26

2

The damping factor is

α

mK

√



o KD

β

ξ =

2

where α is programmed by the carrier register al­pha_car:

alpha_car+6

α = 2

beta_car can only take value from 0 to 15; if
beta_car is 0 the loop becames a first order one.

alpha_car can take any value from 0 to 9. If both
alpha_car and beta_car are 0 then the loop is
open.

D

depends on the signal to noise ratio and is

K
given in the figure in next column.

(see par. 3.8 for C/N definition)

D

= 1.26 for a noise free input signal.

K
The natural frequency and the damping factor

can be rewritten as:

f

n

16.515

=

√

√



m

F

CK

K

⋅

D

2

⋅

beta_car

m

⋅ K

ξ =

0.0289



√

F

CK

alpha_car

2

√

beta_car

2

D

Table 2 gives the natural frequency and the
damping factor for the nominal amplitude m = 22,

D

= 1.26 and M_CLK = 39.02687179MHz.

K
In presence of noise the value of K

D

may be re­duced of up to 60%; it is recommended to start
with a damping fac tor, without noise, greater than
the usual value of 0.7.

3.4.3 Phase and frequency detector parameter

The carrier phase error is calculated by the fol­lowing formula : ε = I sgn(Q) - Q sgn(I).
This value is computed (at symbol rate) if the ac­tual I and Q components are greater than a pro­grammed threshold otherwise the previous value
is mantained. In this way the det ector outputs a
DC value proportional to the frequency off set be­tween the incoming signal and the local oscillator.

The threshold value may be programmed by the
PFDTHR parameter inside the QPSK_CON­TROL2 register:

18/43

STA002

QPSK_CONTROL2 Register
Internal address: 81 H
Reset Value: 90H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

PFDTHR CNTHR SN

The threshold value dep ends on the signal level
at the Nyquist filter out put. A good value for this
parameter is given by: PFDTHR = 0.4 AGC2REF
where AGC2REF is the reference value for the
AGC2 loop.

3.4.4 Internal ramp parameter
In presence of a frequency offset greater than the

pull-in range of the carrier loop or in presence of
low signal to noise ratio t he tracking perform ance
of the loop itself may became rather slow. To
help the loop in tracking this frequency offset an
internal ramp can be activated by I

2

C bus.

This ramp can be switched on or off by setting
the SWON parameter 1 or 0 respectively. When
SWON=0 the output value of the ramp is null.
The sweep rate can be calculated by the f ollow­ing formula:

dF

dt

=

stepper

swstep

2

2

F

ck
26

1

+

2

where swstep can only take 0 and 1 values and
stepper can be programm ed in a range from 0 to 15.

MSB LSB

X X b5 b4 b3 b2 b1 b0

b5 : SWON; 1 = 2 ramp on; 0 = 2 ramp off
b4 : SWS T EP
b3 - b0 : STEPPER

Ramp control register (RAMPCTRL)
Internal address: 95 H
Reset Value: 01H

AGC1

3.5.

3.5.1 AGC1 control
To avoid a degradation of the signal to noise r atio

a constant IF level is necessary at the channel
decoder input.

The AGC1 outputs a signal to control the Variable
Gain Amplifier in the RF Front-End in order to
mantain a fixed level at the ADC input.

The input signal power (computed after the A/D
conversion) is compared to a programmable

threshold; the difference is scaled by the
AGC1BETA coefficient then integrated.

The result is converted into a pulse width modula­tion signal to drive the AGC output pin; it may be
filtered by a simple RC filter to control the gain
command of a variable gain amplifier before the
A to D conversion.
The 8 integrator MSB’s (AGC1_ INTG register)
may be read or written at any time by the micro;
when written, the LSB’s are reset.

The integrator value is the level of the AGC out­put, after low pass filt ering; it gives an image of
the input signal power. The sign of the loop can
be controlled by the AGC1CHS control bit in the
QPSK_CONTROL1 register in order to adapt the
loop to a positive or negative slope of the variable
gain amplifier.

3.5.2 Registers
AGC1 reference level register (AGC1_REF)
Internal address: 83 H 82H
Reset Value : 01H 06H

MSB LSB

XXXXXXb9b8

AGC1_REF2

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

AGC1_REF1
This register is divided into two bytes. The LSB

byte is named AGC1_REF1, the MSB is named
AGC1_REF2.

The reset value of this register (262) maintains
the peak signal input level equal to the half range
of the ADC.

AGC1 integrator gain register (AGC1_BETA)
Internal address: 84 H
Reset Value: 00H

MSB LSB

X X X X X b2 b1 b0

AGC1_BETA
The AGC1 loop gain

AGC1

b

β

AGC1

AGC1_BETA

= 2

is given by:

The parameter AGC1_BETA can only take values
from 0 to 5. When AGC1_BETA is set to "111"
the loop gain is null. This condition is useful to
open the AGC1 loop.

19/43

STA002

AGC1 integrator value register (AGC1_INTG)
Internal address: 85 H
Reset Value: 00H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

signed number

To open the AGC1 loop this register must be re­set and the AGC1_BETA parameter must be
"111".

3.6. AGC2

3.6.1 AGC2 control
The AGC2 loop is used at the output of the

Nyquist / interpolator filter for power optimization
in the signal bandwith.

The modulus of the complex signal a t the output
of the Nyquist filter is compared to a programma­ble threshold and then scaled by the
AGC2_BETA coefficient and integrated.

The integrated error drives two multiplier at the
output of both t he Nyquist filters in order to man­tain constant the level signal at the demodulator
output.

3.6.2 Register
AGC2 reference level register (AGC2_REF)
Internal address: 86 H
Reset Value : 16 H

MSB LSB

X X b5 b4 b3 b2 b1 b0

AGC2_REF
The value written in this register corresponds to

the modulud of the output complex signal (I,Q).

AGC2 integrator gain register (AGC2_BETA)
Internal address: 87 H
Reset Value: 00H

MSB LSB

XXXXXb2b1b0

AGC2_BETA
The AGC2 loop gain

can be controlled by

β

AGC2

this register:

AGC2

β

AGC2_BETA

= 2

The parameter AGC2_BETA can take values
from 0 to 6. When AGC2_BETA is set to "111"
the loop gain is null and the AGC2 ampli fier gain
keeps the last value.

AGC2 integrator value register (AGC2_INTG)
Internal address: 88 H
Reset Value: 00H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

signed number

To open the AGC2 loop this register must be re­set and the AGC2_BETA parameter must be
"111".

The AGC2 reference level value impacts the
value of the following functions:

- Carrier to Noise indicator;

- The carrier loop;

- The timing loop

3.7. LOCK INDICATOR
This 1 bit carrier lock flag may be read at any

time.
This flag is available at the c hip output and can

be also read by the micro in the FLAG register
A low logic level at t he Lock Indicator m eans that
a QPSK signal is found.The lock indicator flag
controls , internally, the ramp block. The sweep
function is disable whenever a lock condition is
detected.

3.8. CARRIER TO NOISE INDICATOR
A register is used to estimate the carrier t o noise

level C/N in a range from 4 to 17dB.
Remark: in the WorldStar system the correspon-

dence between C/N, Eb/No (Energy per net-bit to
noise ratio) and Eb/No|

(Energy per channel-

QPSK

bit to noise ratio) are the following:

C/N = Eb/No|

+ 3dB = Eb/No - 0.6dB

QPSK

The C/N indicator may be used to optimize the
antenna pointing or to give an idea of t he RF si­gal quality. This is based on the measure of the
scattering of the QPSK constellation: a 10 bit
counter is incremented when the scattering is ex­ceeding a certain value. After a programmable
time interval the 8MSB of t he counter are loaded
in the corresponding I

2

C-bus register.
The register value strongly depends on the
AGC2_REF parameter.

3.8.1 C/N Register (CNCNT)
This register contains a value proportional to the

signal to noise ratio at the Nyquist filter output

QPSK

(Eb/No|

).

20/43

TABLE 3. Correspondence between C/N and the CNCNT register contents.

C/N(dB) Eb/No|QPSK CNTHR = 8 CNTHR = 12 CNTHR = 16

m = AGC2_ REF 16 22 26 16 22 26 16 22 26

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

The value are the average of 1000 readings of the CNCNT register.

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

161
155
148
140
132
122
113
105

92
84
71
65
58
49
42
34
32
30

121
112
102

91
79
68
55
46
33
26
20
14

9
5

3.4

2.4

1.5

0.9

101

93
84
73
61
50
38
28
20
13

8
6

3.2

1.6

0.9

0.5

0.25

0.07

NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA

177
173
168
161
155
148
141
134
125
118
112
103

93
84
77
70
66
61

151
145
138
130
120
110
100

89
79
67
57
51
40
32
27
23
19
13

NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA

NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA

STA002

193
192
190
186
184
180
177
174
170
165
161
158
154
149
144
141
137
131

The relation between C/N and the r equired value
(CNCNT) is given in the table 3 for three AGC2
reference levels. A value of 255 means overflow.

3.8.2 Control Register
There are two parameters to control the C/N esti-

mator circuit CNTHR and SN located in the
QPSK _CONTROL 2 register.
The CNTHR parameter (2 bits) sets the threshold
value under which the circuit is activated.
The SN parameter (2bits) sets the m easure time
internal.
Both there two parameters are given in the fol­lowing tables:

CNTHR THRESHOLD

00
01
10
11

SN TIME INTERVAL IN SYMBOLS

00
01
10
11

8
12
16

NA

1024

4096
16384
65536

A suitable value of the threshold and time inter­val must be chosen to have a good level of confi­dence of the C/N estimate.
To increase the measure accuracy is advisable to
average several values.
Before starting the measure the CNCNT register
must be reset and can be read after the selected

time internal.
A flag bit (CNFLAG) is set to 1 to indicate that a
value is available in the CNCNT register.

3.9 CONTROL REGISTERS
QPSK_CONTROL1 register
Internal address: 80 H
Reset Value: 10H

MSB LSB

X b6b5b4b3X X X

b6 : AGC1CHS
b5 : CAR CHS
b4 :TIMCHS
b3 : QCHP
AGC1CHS changes the polarity of the AGC sig-

nal at output pin.
CARCHS and TIMCHS change the sign of the

carrier tracking loop and symbol tracking loop re­spectively.

QCHS inverts the sign of the Q component.

QPSK_CONTROL2 register
Internal address: 81 H
Reset Value: 90H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

PFDTHR CNTHR SN

21/43

STA002

This register controls the Phase and frequency
detector threshold (see par. 3.4.3) and the C/N
indicator (see 3.8.2)

FLAG REGISTER
internal address: 99 H

LOCK CNFLAG

reserved
This is a read only register when the LOCK bit is

0 then the car rier is locked. When the CNFLAG
bit is 1 then the C/N estimation is available.

4. TDM DEMULTIPLEXING

4.1 TDM_MULTIPLEX REGISTERS.

Reg name: TDM_TRSH1
Internal address: 200 H
Type: R/W
Reset Value: 4BH

MSB LSB

X b6b5b4b3b2b1b0

Description: Master frame preamble recognition ­Synchronization threshold level.

Definition of the minimum number of TDM pre­amble bits to be recognized before enabling the
frame synchronization.

MSB LSB

X b6b5b4b3b2b1b0

Description: Master frame preamble recognition ­Warning flag threshold level.

Definition of the minimum number of TDM pre­amble bits to be recognized before setting an
alarm condition.

Reg name: TDM_ALARM
Internal address: 207 H
Type: R/W
Reset Value: 00H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description: TDM finite state machine control reg­ister (see Table 4).

Reg name: PRC_TRSH1
Internal address: 202 H
Type: R/W
Reset Value: 2AH

MSB LSB

X X b5 b4 b3 b2 b1 b0

Reg name: TDM_TRSH2
Internal address: 201 H
Type: R/W
Reset Value: 43H

Description: Prime rate channel preamble recog­nition - Synchronization threshold level.

Definition of the minimum number of PRC pre­amble bits to be recognized before enabling PRC
synchronization.

Table 4: TDM FSM active states

b7 b6 b5 b4 b3 b2 b1 b0 TDM FSM active states

XXXXX000mfp_detection, mfp_presync, mfp_sync,alarm 1 (1 cycle)
XXXXX001mfp_detection, mfp_presync, mfp_sync,alarm 1 (2 cycle)
XXXXX000mfp_detection, mfp_presync, mfp_sync,alarm 1 (3 cycle)
XXXXX001mfp_detection, mfp_presync, mfp_sync,alarm 1 (4 cycle)
000001XXmfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (1 cycles)
000011XXmfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (2 cycles)

-----1XXmfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (n cycles)

111111XXmfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (32 cycles)

22/43

STA002

Reg name: PRC_TRSH2
Internal address: 203 H
Type: R/W
Reset Value: 23H

MSB LSB

X X b5 b4 b3 b2 b1 b0

Description: Prime rate channel preamble recog­nition - Warning flag threshold level.

It defines the minimum number of PRC preamble
bits to be recognized before setting an alarm con­dition.

Reg name: PRC_ALARM
Internal address: 208 H
Type: R/W
Reset Value: 00H

MSB LSB

b7 b6 b5 b4 X X b1 b0

Description: PRC finite state machine control reg­ister (see table 5).

Reg name: PRC_ACTIVE_REG
Internal address: 20F H
Type: R

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description: It gives the li st of active PRC within
one selected BC.

b0 to b7 indicates PRC0 to PRC7 respectively.

Reg name: PRC_LOCK_REG
Internal address: 210 H
Type: R

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description: Lock status of each PRC

b0 to b7 indicates the lock status of PRC0 to
PRC7 respectively.

Reg name: PRC_DELAY_REG
Internal address: 211 H
Type: R

MSB LSB

X X X X b3b2b1b0

Description: PRC maximum number of delay
symbols

It detects the maximum number of delay symbols
among the PRC within the same BC.

Table 5: PRC_ALARM

b7 b6 b5 b4 b1 b0 PRC FSM active states

X X X X 0 0 prcp_detection, prcp_presync, prcp_sync
X X X X 0 1 prcp_detection, prcp_presync, prcp_sync, alarm 1
0 0 0 0 1 0 sp_detection, sp_presync, sp_sync, alarm2
0 0 0 1 1 0 sp_detection, sp_presync, sp_sync, alarm2 (1 cycle)
0 0 1 0 1 0 sp_detection, sp_presync, sp_sync, alarm2 (2 cycles)
0 0 1 1 1 0 sp_detection, sp_presync, sp_sync, alarm2 (3 cycles)

- - - - 1 0 sp_detection, sp_presync, sp_sync, alarm2 (n cycles)
1 1 1 1 1 0 sp_detection, sp_presync, sp_sync, alarm2 (16 cycles)
0 0 0 0 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2
0 0 0 1 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (1 cycle)
0 0 1 0 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (2 cycles)
0 0 1 1 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (3 cycles)

- - - - 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (n cycles)
1 1 1 1 1 1 sp_detection, sp_presync, sp_sync, alarm1, alarm2 (16 cycles)

23/43

STA002

Reg name: PRC_MAXDELAY
Internal address: 206 H
Type: R/W
Reset Value:06H

MSB LSB

XXXXXb2b1b0

Description: Maximum accepted number of de­lay symbols among the prime rate channels be­longing to the same broadcast channel.

Reg name: SP_TRSH2
Internal address: 205 H
Type: R/W
Reset Value: 13H

MSB LSB

X X X b4 b3 b2 b1 b0

Description: Service control header preamble rec­ognition - Warning flag threshold level.

Definition of the minimum number of SCH pre­amble bits to be recognized before enabling SCH
synchronization

4.2 INTERRUPT/STATUS REGISTERS

Reg name: CONTROL
Internal address: 20BH
Type: R/W
Reset Value: 00H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description: Control register
b0 : Software reset on
b1 : Software reset enable
b2 : Set TDM out of frame
b3 : ERROR_REG reset on read enable
b4 : Set PRC out of frame
b5 : Set BC out of frame
b6, b7: Test purpose

Reg name: INT_MASK
Internal address: 20CH
Type: R/W
Reset Value: 00H

Reg name: BC_SEL1, BC_SEL2
Internal address: 209 H , 20AH
Type: R/W
Reset Value: 01H, 00H

BC_SEL1 (LSB)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

BC_SEL2 (MSB)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

Description: Broadcast channel selection

b10 ....b0: BC number selection

b11: Test purpose
b15 ... b12 : Test purpose (must be set at 0 in

functional mode)

MSB LSB

X b6b5b4b3b2b1b0

Description: Enable/Disable interrupt on INTR pin
b0 : SCCF interrupt mask
b1 : Max Delay Alarm mask
b2 : Illegal Address mask
b3 : TDM out of frame mask
b4 : RS block error mask
b5 : SCH interrupt mask
b6 : Test purpose

Reg name: ERROR_REG
Internal address: 20DH
Type: R/W
Reset Value: 00H

MSB LSB

X b6b5b4b3b2b1b0

Description: Interrupt register
b0 : SCCF interrupt on
b1 : Max Delay Alarm on

24/43

STA002

b2 : Illegal Address on
b3 : TDM out of frame on
b4 : RS block error on
b5 : SCH interrupt on
b6 : Test purpose

Reg name: STATUS REG
Internal address: 20EH
Type: R
Reset Value: 00H

MSB LSB

X X b5 b4 b3 b2 b1 b0

Description: Status register:
b0 : TSCC available
b1 : BC lock
b2 : SCH available
b3 : PRC lock
b4 : MFP lock
b5 : SCCF available

tency.
The number of wrong bits is accumulated into a

register according to a given time base ex­pressed in number of bits and, assuming that the
BER at the output of the Viterbi decoder is negli­gible with respect to the input BER, this count can
be read by the system micro controller to evalu­ate the signal quality after QPSK demodulation.

The error rate measurement is programmable
throught the VITERBI_ERROR_CONTROL regis­ter and the error rate is available in the registers:

ERROR
ERROR 2

1

- VIT_

- VIT_

Reg name: VITERBI_ERROR_CONTROL

Internal address: 204 H
Type: R/W
Reset Value: 00H

MSB LSB

X X X X b3b2b1b0

Description: Viterbi input errors measurement
windows length and error mode presetting.

5. VITERBI DE CODER AND SY NCHR ONIZ ATION

A Viterbi decoder has been implemented in the
STA002 in order to extract the most probable
transmitted sequence using a trace back proce­dure.

This Viterbi decoder has been realized using 64­bit trace back depth and the soft decision ap­proach on the six-bit I and Q components coming
from the QPSK demodulator.

The convolutive codes are generated by the poly­nomials Gx = 171

and Gy = 133

oct

oct

.
The Viterbi decoder computes for each symbol
the metrics of the four possible paths, propor­tional to the square of t he Euclidian distance be­tween the recived I and Q and the theoretical
symbol value.

Four logical RAM banks (implemented with eight
RAM blocks of 32x64 bits) have been used for
the path memory.

The decoding latency is 256 bits.
A bit error (BER) estimator has been integrated in

the Viterbi block.
Corrected data bits at Viterbi out put are encoded

according to the t ransmission convolutional code
so that a "good" stream is obtained. These data
are compared with the data stream coming fr om
the QPSK demodulator after having stored it into
a memory buffer to compensate the Viterbi la-

Monitor windows length (bits)

b1b0 = 00

b2 = 0 Single acquisition mode
b2 = 1 Continuous acquisition mode
b3 = 0 End measurement (single /continuous

b3 = 1 Single acquisition start

1024

01

4096

10

16384

11

65536

Error Measurement Mode

acquisition )

Reg name: VIT_ERR0R1, VIT_ERROR2
Internal address: 213 H , 214H
Type: R/W

VIT_ERROR 1 (ERROR COUNTER LOW)

MSB LSB

A7 A6 A5 A4 A3 A2 A1 A0

VIT_ERROR 2 (ERROR COUNTER HIGH)

MSB LSB

A15 A14 A13 A12 A11 A10 A9 A8

Description: Viterbi error counter register

25/43

STA002

6. REED SOLOMON DECODER
The STA 002 performs a real time block decoding

operation both on the Time Slot Control Channel
(TSCC) field and on the Broadcast Channel (BC)
stream by means of a programmable Reed-Solo­mon (RS) decoder.

This decoder works on blocks of 255 words of 8
bit symbols where the first 223 words represent
the information and the last 32 the code redun­dancy.

The synchrobyte is the first byte of the block.
All the correction capability of the code is used so

it is possible the correction of blocks containing
up to 16 errors while blocks with greater number
of errors are flagged as corrupted.

The RS decoder is programmable to support two
different Galois field generat or polynomials as re­quired by WorldSpace specifications and includes
an integrated BER estimator.

Monitoring the number of wrong words in each
block and correlating this number with the block
length, it is possible, provided that no corrupted
blocks are present, to get an estimation of the
signal quality at the Viterbi decoder output.

6.1 TSCC REED SOLOMON DECODER
The code generator polynomial is:

MSB LSB

X X X X b3b2b1b0

Description: Reed Solomon input errors measure­ment windows length and error mode presettings

Monitor windows length (blocks)

b1b0 = 00

b2 = 0 Single acquisition mode
b2 = 1 Continuous acquisition mode
b3 = 0 End measurement (single /continuous

b3 = 1 Single acquisition start

3

01

64

10

256

11

1024

Error Measurement Mode

acquisition

Reg name: RS_BYTE_ERROR1,
RS_BYTE_ERROR2

Internal address: 215 H , 216H
Type: R/W

RS_BYTE_ERR0R1 (ERROR COUNT ER LOW)

143

g(X) =

∏

J

= 112

generated by X

(x −

11J

over the Galois Field

)

α

8+X7+X2

+X+1.

6.2 BROADCAST CHANNEL RS DECODER
AND DESCRAMBLER.

The code generator polynomial is:
g(x) = (x-ω°) (x-

1

) (...) (x-

ω

31

)

ω

over the Galois Field generated by:

8+X4+X3+X2

X

+1=0

6.3 ENERGY DISPERSAL DESCRAMBLE R
The descrambler generator polynomial is:

9+X5

X

+1
Reg name: RS_ERROR_CONTROL
Internal address: 212H
Type: R/W
Reset Value: 00H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

RS_BYTE_ERROR 2 (ERROR COUNTER
HIGH)

MSB LSB

X X b13 b12 b11 b10 b9 b8

Description: RS byte error counter register

Reg name: RS_BLOCK_ERROR
Internal address: 217H
Type: R/W

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description: RS block error counter register

26/43

STA002

7. BROADCAST CHANNEL DEMULTIPLEX ER

7.1 SCH REGISTER

Reg name: BRI_REG & NSC_REG
Internal address: 000H
Type: R

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description:
b7 to b4 indicate the bit rate of the BC
(BRI field in the SCH)
0000: no valid data
0001: 16Kbps

..............................

1000 : 128Kbps
1001 - 1111: RFU
b3 = 0
b2 to b0 indicate the number of service compo-

nents (NSC field in the SCH)
000: one Service Component
001: two Service Component

...............................................

111: eight Service Component

Reg name: EC_REG
Internal address: 001H
Type: R

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Reg name: AFCI1_REG
Internal address: 002H
Type: R

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description :
b7 to b5 = 000
b4 to b0 indicate the Auxiliary field content indica-

tor 1 (ACI1l field in the SCH)
00000: not used
00001: 16 bit encryption key selector
00010: RDS PI code
00011: Associated Broadcast Channel reference

(PS flag and ASP)
else: RFU

Reg name: AFCI2_REG
Internal address: 003H
Type: R

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description:
b7 : 0
b6 to b0 indicate the Auxiliary field content indica-

tor 2 (ACI2 field in the SCH)
00000: not used
00001:64 bit encryption key selector
00010: Service Label
else: RFU

Description:
b7 to b4 = 0000
b3 to b0 indicate the encryption strategy (Encryp-

tion Control field in the SCH)
0000: no encryption
0001: static Key
0010: ESI, common key, subscription period A
0100: ESI, broadcast channel specific key for

subscription period A
0101: ESI, broadcast channel specific key for

subscription period B
else: RFU

Reg name: SOF_SF_REG
Internal address: 0041H
Type: R

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description:
b7 to b5 = 000
b4 indicate the ADF2 multiframe start flag (SF

field in the SCH)
1: first segment of multiframe or no multiframe
0: intermediate segment of multiframe
b3 to b0 indicate the segment offset and lenght

field (SFT field in the SCH) if SF = 1 SOLF con­tains the total number of multiframe segments minus 1.

27/43

STA002

0000: one segment multiframe
0001: two segment multiframe

.................................................

1111: 16 segment multiframe
if SF = 0 SOLF contains the segment offset.

Reg name: ADF1_REG
Internal address: 006H, 005H
Type: R

ADF1 (15:8) ( addr 006H)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

ADF1 (7:0) ( addr 005H)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description:
b15 to A0 contain the Auxiliary data field1 (ADF1

field in the SCH) with content defined by
AFCI1_REG)

Reg name: ADF2_REG
Internal address: 00EH,00DH, 00CH, 00BH,

00AH, 009H, 008H, 007H,
Type: R
ADF2(63:56) (addr 00EH)

ADF2(31:24) (addr 00AH)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

ADF2(23:16) (addr 009H)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

ADF2(15:8) (addr 008H)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

ADF2(7:0) (addr 007H)

MSB LSB

A7 A6 A5 A4 A3 A3 A1 A0

Description:
b64 to b0 contain the Auxiliary data field2 (ADF2

field in the SCH) with content defined by
AFCI2_REG)

Reg name: SEL_SC_REG

Internal address: 00FH
Type: R/W

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

b63 b62 b61 b60 b59 b58 b57 b56

ADF2(55:48) (addr 00DH)

MSB LSB

b55 b54 b53 b52 b51 b50 b49 b48

ADF2(47:40) (addr 00CH)

MSB LSB

b47 b46 b45 b44 b43 b42 b41 b40

ADF2(39:32) (addr 00BH)

MSB LSB

b39 b38 b37 b36 b35 b34 b33 b32

28/43

Description :
b7: =1 Enable service component selection A

= 0 Disable
b6 to b4 contain the Service Component selec-

tion A
000: SC1
001: SC2

...............

111: SC8
b3: =1 Enable service component selection B

= 0 Disable
b2 to b0 contain the Service Component selec-

tion B
000: SC1
001: SC2

...............

111: SC8

STA002

Reg name: PIW_ RAM
Internal address: 03F,03E, 03D, 03C,

03B, 03A, 039, 038,
Type: W
PIW_RAM (63:56) (addr 03F)

MSB LSB

b63 b62 b61 b60 b59 b58 b57 b56

PIW_RAM (55:48) (addr 03E)

MSB LSB

b55 b54 b53 b52 b51 b50 b49 b48

PIW_RAM (47:40) (addr 03D)

MSB LSB

b47 b46 b45 b44 b43 b42 b41 b40

PIW_RAM (39:32) (addr 03C)

MSB LSB

b39 b38 b37 b36 b35 b34 b33 b32

Reg name: EM_REG
Internal address: 018H
Type: R/W

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description :
Encryption mode register
b7 to b1 = not used RFU
b0 indicate the encryption mode (1)
1: normal encryption mode
0: enable blocking
(1) for more information refer to document

number WST-WSG-DDS-003-500000
Chipset Encryption Impleme ntation S pecifica tion
for World space receiver

Reg name: PIWE_REG
Internal address: 01AH, 019H
Type: R/W
PIWE (15:8) (addr 01AH)

PIW_RAM (31:24) (addr 03B)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

PIW_RAM (23:16) (addr 03A)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

PIW_RAM (15:8) (addr 039)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

PIW_RAM (7:0) (addr 038)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description:
b63 tob0 contain t he prestored initialization word

0 which is the only one downloadable by the
processor.

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

PIWE (7:0) (addr 019H)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description :
b15 to b0 contain the 16 BIT static key selector

word. Each bit PIWE enables a certain static key.
If bit A0 of PIWE is set, the static key 0 will be en­abled for read out and so forth.

Reg name: BCIN_DELAY_REG
Internal address: 01BH
Type: R/W
Default 00H

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description : BC input delay and BC input enable
register

b0: enables external BC input

29/43

STA002

BC input delay (bytes)

b2b1 = 00

01
10
11

1
2
3
4

b3: Test purpose (must be set at 0 in functional
mode)

b7 to b4: test purpose

Reg name: BC_ALARM_REG
Internal address: 01CH
Type: R/W
Default:20H

MSB LSB

X X b5 b4 b3 b2 b1 b0

Description: BC finite state machine control regis­ter (see table 6)

b5 indicates the BC synchronization mode
1: SP preamble detection
0: Synch from PRC
Reg name: IW_REG
Internal address: 017, 016, 015, 014,

013, 012, 011, 010,
Type: W
IW_REG (63:56) (addr 017)

MSB LSB

b63 b62 b61 b60 b59 b58 b57 b56

IW_REG (55:48) (addr 016)

IW_REG (47:40) (addr 015)

MSB LSB

b47 b46 b45 b44 b43 b42 b41 b40

IW_REG (39:32) (addr 014)

MSB LSB

b39 b38 b37 b36 b35 b34 b33 b32

IW_REG (31:24) (addr 013)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

IW_REG (23:16) (addr 012)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

IW_REG (15:8) (addr 011H)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

IW_REG (7:0) (addr 010H)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

Description:
b63 to b0 contain the initialization word IW.

MSB LSB

b55 b54 b53 b52 b51 b50 b49 b48

Table 6: BC_ALARM_REG

b4 b3 b2 b1 b0 BC FSM active states

0 0 0 0 0 sp_detection, sp_presync, sp_sync
1 0 0 0 0 sp_detection, sp_presync, sp_sync, alarm_state (1 cycle)
1 0 0 0 1 sp_detection, sp_presync, sp_sync, alarm_state (2 cycles)
1 0 0 1 0 sp_detection, sp_presync, sp_sync, alarm_state (3 cycles)
1 0 0 1 1 sp_detection, sp_presync, sp_sync, alarm_state (4 cycles)
1 - - - - sp_detection, sp_presync, sp_sync, alarm_state (n cycles)
1 1 1 1 0 sp_detection, sp_presync, sp_sync, alarm_state (15 cycles)
1 1 1 1 1 sp_detection, sp_presync, sp_sync, alarm_state (16 cycles)

30/43

STA002

SCH_MEM REGISTERS
Service Component Control Field (SCCF)
Reg name: SERVICE COMPONENT 1
Internal address: 100H, 101H, 102H, 103H
Type: R
Description :
Contains information about the service compo-

nent of the broadcast channel

SC1_LENGHT & SC1_TYPE (addr 100H)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

SC1_EC & SC1_PT (addr 101H)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SC1_PT (addr 102H)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

b7 to b0 = SC language

Reg name: SERVICE COMPONENT 2
Internal address: 104H, 105H, 106H, 107H
Type: R
Description :
Contains information about the service compo-

nent of the broadcast channel

SC2 _LENGHT & SC2_TYPE(addr 104H)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

SC2 _EC & SC2_PT (addr 105H)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SC2_PT (addr 106H)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

LANGUAGE 1 (addr 103H)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:

0000: 8 kbps
0001: 16 kbps

...............

1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100:JPEG
0101: MPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type

LANGUAGE 2 (addr 107H)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:

0000: 8 kbps
0001: 16 kbps

...............

1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100:JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language

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STA002

Reg name: SERVICE COMPONENT 3
Internal address: 108H, 109H, 10AH, 10BH
Type: R
Description :
Contains information about the service compo-

nent of the broadcast channel

SC3_LENGHT & SC3_TYPE (addr 108H)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

SC3 _EC & SC3_PT(addr 109H)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SC3_PT (addr 10AH)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

LANGUAGE 3 (addr 10BH)

Reg name: SERVICE COMPONENT 4
Internal address: 10CH, 10DH, 10EH, 10FH
Type: R
Description :
Contains information about the service compo-

nent of the broadcast channel

SC4_LENGHT & SC3_TYPE (addr 10CH)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

SC4_EC & SC3_PT (addr 10DH)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SC4 _PT(addr 10EH)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

LANGUAGE 4 (addr 10FH)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:

0000: 8 kbps
0001: 16 kbps

...............

1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100:JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:

0000: 8 kbps
0001: 16 kbps

...............

1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language

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STA002

Reg name: SERVICE COMPONENT 5
Internal address: 110H, 111H, 112H, 113H
Type: R
Description :
Contains information about the service compo-

nent of the broadcast channel

SC5 _LENGHT & SC5_TYPE(addr 110H)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

SC5_EC & SC5_PT(addr 111H)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SC5_PT (addr 112H)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

LANGUAGE 5(addr 113H)

Reg name: SERVICE COMPONENT 6
Internal address: 114H, 115H, 116H, 117H
Type: R
Description :
Contains information about the service compo-

nent of the broadcast channel

SC6 _LENGHT & SC6_TYPE(addr 114H)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

SC6 _EC & SC6_PT(addr 115H)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SC6_PT (addr 116H)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

LANGUAGE6 (addr 117H)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:

000: 8 kbps
001: 16 kbps

...............

1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:

0000: 8 kbps
0001: 16 kbps

...............

1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
7 to b0 = SC language

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STA002

Reg name: SERVICE COMPONENT 7
Internal address: 118H, 119H, 11AH, 11BH
Type: R
Description :
Contains information about the service compo-

nent of the broadcast channel

SC7_LENGHT & SC7_TYPE (addr 118H)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

SC7 _EC & SC7_PT(addr 119H)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SC7_PT (addr 11AH)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

LANGUAGE7 (addr 11BH)

Reg name: SERVICE COMPONENT 8
Internal address: 11CH, 11DH, 11EH, 11FH
Type: R
Description :
Contains information about the service compo-

nent of the broadcast channel

SC8 _LENGHT & SC38_TYPE(addr 11CH)

MSB LSB

b31 b30 b29 b28 b27 b26 b25 b24

SC8 _EC & SC8_PT(addr 11DH)

MSB LSB

b23 b22 b21 b20 b19 b18 b17 b16

SC8 _PT (addr 11EH)

MSB LSB

b15 b14 b13 b12 b11 b10 b9 b8

LANGUAGE8 (addr 11FH)

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:

0000: 8 kbps
0001: 16 kbps

...............

1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:

0000: 8 kbps
0001: 16 kbps

...............

1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language

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STA002

8. GENERAL INFORMATION

8.1 DECRIPTION
The STA002 supports a crypto-scheme named

WES (World Space Encrypton Scheme)
It is composed of two functional blocks:

- CSG (Crypto Sequence Generator)
implemented in the STA002 decoder

- IWG (Initialization Word Generator) processed
by external hardware such as a microcontroller
or a smart card.

The CSG module produces the pseudo-casual
sequence by an algorithm based on the galois ar­rithmetic.

This algorithm is derived in 2 phases:

1) Key expansion

2) Pseudo casual sequence generation
In the expansion phase activated every frame the

IWG 8 bytes key is used t o initialize a 16 bytes
array.
The scrambling procedure, invoked every byte,
implements a pseudo random algorithm.
The XOR operation between the output of the
module the encrypted bytes completes the de­cryption procedure.
The 8 bytes keyword is loaded bef ore the s tart of
the new frame to the I

2

C bus interface.

8.2. BROADCAST CHANNEL INTERFACE
The Broadcast Channel interface consists of 4

wires: output clock (BCCK), output BC data
(BCDO), output BC frame sync. (BCSYNC) and
input BC data (BCDIN).

The data trasmitted and recived via the broadcast
channel interface are 8 bit bursts.

The most significant bit is transmitted first.

Fig.7 shows the broadcast channel serial data out
(BCDO) burst of 8 bit (MSB first). The data bits
are valid at the negative slope of the clock line
(BCCK).

The BCSYNC signal indicates the first byte of the
broadcast channel Service preamble (04H) allow­ing an easy syncronization to external modules
using the BC data.
The input BC line (BCDI) must have the same
format of the BC output (BCDO). The data bit
must be valid on the negative edge of the output
clock line (BCCK).
The maximum delay allowed from the output data
and the input data is 4 bytes (4 bursts of 8 bits).
The input delay is programmable via I2C bus with
the BCIN_DELAY_REG register (01BH).

8.3 SERVICE COMPONENT INTERFACES

The STA002 provides two service component in­terfaces which support the same protocol:

- SC DATA INT E R F ACE (SCEN, SCDO , SC CK)

- SOURCE DECODER INTERFACE (SEN, SDO, SCK)
The service component interfaces consists of 3

wires each. Output clock (SCCK/SCK), SC data
(SCDO/SDO) and SC byte sync (SCEN/SEN).

The data transmitted via the service component
interface are 8 bit bursts.
The most significant bit is transmitted first.
As shown in fig.8 the service component serial
data out (SCDO/SDO) combines burst of 8 bit
length (MSB first). The data bit are valid at the
negative edge of the clock line (SCCK/ SCK).

The slope change of the SCEN/SEN indicates the
most significative bit of the 8 bit service compo­nent burst.

The SCEN/SEN signal is used if required for the
data bits alignement only.

Fig. 7: Format Of The Broadcast Channel Interface (BC)

BCCK

BCDO

BCSYNC

BCDI

t

clk

76543210 76543210 76543210 76543210

ABCD

76543210 76543210 76543210 76543210

XYAB

PROGRAMMABLE DELAY FROM BC-OUT DATA

TO BC-IN DATA MAX 4 BYTE

t

clk-off

t

clk-off < 1.2ms

t

clk ~ 6.5µs

D97AU744A

35/43

STA002

Fig. 8: Format Of The Service Component Interface

SCCK/SCK

SCDO/SDO

SCEN/SEN

t

clk

76543210 76543210 76543210 76543210

ABCD

t

clk-off < 15ms

t

clk ~ 6.5µs

t

clk-off

CHANNEL DECODER INTERFACES BLOCK DIAGRAM

IIC

D97AU745

µP

36/43

RF

FRONT

END

RXI

RNXI

M_CLK

AGC

LOCK

INTERFACE

INTERFACE

SCCK

CHANNEL

DECODER

RF

SCDO

SCEN

SCL SDA INTR RESET

MICRO

INTERFACE

SOURCE

SCK

SDI

DECODER

INTERFACE

BC DATA

SEN

MINTRSC DATA

INTERFACE

BCCK

BCDO BCSYNC

BCDIN

MPEG

DECODER

D96AU547C

y

8.4 FRAME SYNCRONIZATION TIMES

FRAME SYNCRONIZATION

STA002

96 SY

MFP

MFP

Tx

MFP DETE CTION

MFP DETECTION

START INTERNAL TIMING

SYNC FOR MFP VERIFICATION

TSCC AVAILABLE

MFP LOCK

MFP LOCK

ALL PRC EXTRACTED LOCK

I2C INTERFACE

BC FRAME SYNC

CASE 1

NORMAL

SP LOCK

SYNC

CASE 2

HW

SP LOCK

SYNC

TSCC

TSCC
READ

Ta

DATA MULTIPLEX

PRE SY N C

DATA READ

TSCC

VITERBI & RS

DECODED

TSCC

AVAILABLE

TDM FRAME 138 ms

DATA MULTIPLEXMFP DATA MULTIPLE X

TSCC

TSCC

MFP

DATA READ

FIELD

VER

DATA FIELD

PRCP DETECTION

BC

SELECTION

DATA FIELD SP

VITERBI & RS & DEINTELEAVER

DATA FIELD DATA FIELD

SP DETECTION

SP DETECTION

MFP

MFP
VER

T

PRC
EXTRACTION
from 1 to8 PRC

CHANNELS

CHANNELS

MULTIPEXING

TSCC

2112 SY MBOLS

TSCC

TSCC
FIELD

PRC

TDM SYNCHRONISATION STATE MACHINE

DATA READ

PRCP

PRC SYNCHRONISATION STATE MACHINE

TDM SYNCHRONISATION STATE MACHINE

DATA MULTIPLEX

251712 SYMBOLS

TSCC

DATA MULTIPLEX

MFP DATA MULTIPLE X

TDM STATE MACHINE

TSCC

MFP

DATA READ

FIELD

VER

PRC FRAME 432 ms

Tdec

MFP

MFP
VER

DATA FIELD

PRE SY NC

PROTECTED BC FRAME 432 ms

DATA FIELD

SCH

SP

TSCC MFPTSCC

SYNC

TSCC
FIELD

MFP

MFP

DATA READ

VER

DECODE D BC FRAM E 432 ms

PRE SY N C

TSCC
FIELD

DATA MULTIPLEX

DATA READ

PRCP

SYNC

SP

MFP
VER

DATA FIELD

SYNC

TSCC

TSCC
FIELD

DATA FIELD

DATA READ

SP

SYNC

Tx = MFP detection time: 0 to 138ms
Ta = TSCC decodification time:= < 2ms
Ty = PRCP detection time: 0 to 432ms
Tdec = VITERBI decoding +

REED SOLOMON error correction +
deinterleaving: ~55ms x PRC number

TDM SYNCRONIZATION TIME
TDM lock = QPSK lock + Tx + 138ms

PRC SYNCRONIZATION TIME
PRC lock = QPSK lock +TDM lock + Ty + 432 ms

BC SYNCRONIZATION TIME
CASE 1 ( SW sy n c):
the BC synchronization FSM asserts the lock sig-

nal when the SP is detected two consecutive
times.

BC lock = QPSK lock + TDM lock + Ty + Tdec +
432 ms

CASE 2 ( HW sync):
the BC synchronization FSM asserts the lock sig-

nal when the BC FRAME SYNC signal is as­serted by the PRC alignment FSM and the SP is
valid.

BC lock = QPSK lock + TDM lock + Ty + Tdec
Note :

About the BC synchronisation, the selection be­tween SW sync and HW syn is achievable
through the register BC_ALARM add 01CH bit
b5.
Bit b5 = 1 indicates the SW sync Bit b5 = 0 indi­cates HW sync.

37/43

p

p

STA002

SCH & SCCF INTERRUPT

20 bit

Tx

SP
DETECTION

SP
DETECTION

SCCF interrupt

SCH interrupt

SCCF avai lable

SCH available

DATA MU LTI PL EX

SCH

SP

PRE SYNC

DATA FIELD

Service Component multiplex

BC FRAME 432 ms

DATA MU LTI PL EX

SP

Service Control Data

SP BRI EC ACI1 ACI2 Nsc ADF1

Tm

DATA MU LTI PL EX

SCH

TDM SYNCHRONISATION STATE MACHINE ( CASE 1)

TDM SYNCHRONISATION STATE MACHINE (CASE 2)

SF SOLF

Tm = SCCF/ SCH not available setup ~ 32 ms
Tsch = SCH interrupt time ~ 1 3.5 ms
Tsccf = SCCF interrupt time ~

432

7136

⋅ 128 + Nsc ⋅ 32ms

⋅ BRI

SCH

DATA MU LTI PL EXSP

SCHSCH

SP

ADF2

SCCF-1 SCCF-8

Tsccf

Tsch

BRI = Bit Rate Index ( from 1 to 8)
Nsc = number of Service Component ( from1 to

8)

Service Com

Control Field

DATA MU LTI PL EX

SCH

SP

SYNC

SYNC

onent

SP

Dynamic Labels

SCH DATA MULTIPLEX

SP

Service Com

reset by SW

SCH

DATA FIELD

onent multiplex

8.5 LOSS OF SYNC TABLE

MPF PRC BC TSCC available SCH available SCCF available
TDM Out of Frame
PRC Out of Frame

BC Out of Frame

unlocked unlocked unlocked not available * *

locked unlocked unlocked available * *
locked locked unlocked availabl e * *

CONTROL REGISTER STATUS REGISTER

TDM OOFb2PRC OOFb4BC OOF

b5

0
1
0
0

0

X

1
0

0
X
X
1

MFP

lock

b4

1
0
1
1

PRC

lock

b3

1
0
0
1

BC

lock

b1

1
0
0
0

TSCC

available

b0

1
0
1
1

SCH

available

b2

1

*
*
*

* Meaningful only if all the sync levels (MFP, PRC, BC) are locked otherwise not significant

SCCF

available

b5

1
*
*
*

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STA002

8.6 I/O CELL DESCRIPTION

1) CMOS Output Pad Buffer, 2mA, with Slew Rate Control / Pins number 2, 13, 18, 24, 27, 28, 29, 31,
36, 37, 39, 41, 43

OUTPUT PIN MAX LOAD

A

Z

D98AU920

2) CMOS Schmitt Trigger Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin number 10

EN

IO

A

INPUT PIN CAPACITANCE

IO 5pF IO 100pF

ZI

D98AU921

3) CMOS Schmitt Trigger Input Pad Buffer / Pin number 16

Z 50pF

OUTPUT

PIN

MAX

LOAD

A

Z

INPUT PIN CAPACITANCE

A 3.5pF

D98AU923

4) CMOS Input Pad Buffer with Active Pull-Down / Pins number 11, 11, 12

A

D98AU923

Z

INPUT PIN CAPACITANCE

A 3.5pF

5) CMOS Input Pad Buffer / Pins number 10, 22, 23, 25, 32, 33, 34, 44

A

D98AU906

Z

OUTPUT PIN CAPACITANCE

A 3.5pF

6) CMOS Input Pad Buffer with Active Pull-Up / Pin number 20

A

Z

OUTPUT PIN CAPACITANCE

A 3.5pF

D98AU907

39/43

STA002

I/O CELL DESCRIPTION (Continued)

7) Analog Pad Buffer / Pins number 5, 6

A

Z

D98AU924

8) M_CKL Input Stage / Pin number 9

V

REF

A

Z

D98AU925

9) RXI/NRXI Input Stage / Pins number 5, 6

OUTPUT PIN CAPACITANCE

A 4pF

OUTPUT PIN TOTAL CAPACITANCE

A 4pF

RXI

COMPARATOR 1

NRXI

40/43

A

BZ

D98AU926

Z

RXI

NRXI

RXI

NRXI

COMPARATOR 2

COMPARATOR 7

STA002

INPUT PIN CAPACITANCE

A/AI 4pF

NRXI Electrical Characteristics

Symbol Parameter Min. Typ. Max. Unit Note

C

m

C

mr

D

iV

Note 1: VA = VB Open circuit voltage
Note 2; VA = VB

8.7 APPLICATION NOTE (Registers preset)

Common Mode Voltage VDD -0.5 V 1
Common Mode Voltage Range VDD -2 VDD -0.3 V 2
Differential Input Voltage 1V Peak to Peak V

According to the choosen M_CLK frequency
some registers values must be changed.

Table 7 shows two different presets for M_CLK =

39.0268MHz and M_CLK = 14.72MHz

Table 7:

HEX_COD DEC_COD

80H 128 QPSK_CONTROL1 38H 38H
81H 129 QPSK_CONTROL2 50H 50H
82H 130 AGC1_REF1 C8H C8H
83H 131 AGC1_REF2 00H 00H
84H 132 AGC1_BETA 05H 05H
8AH 138 SYM_FREQ1 D3H 00H

8BH 139 SYM_FREQ2 11H 00H
8CH 140 SYM_FREQ_ 0CH 10H
8DH 141 TIM_FLT_PAR 44H 44H

8FH 143 CAR_FLT_PAR 22H 22H

90H 144 IF_FREQ1 37H 00H

91H 145 IF_FREQ2 1DH 00H

92H 146 IF_FREQ3 C1H 00H

93H 147 IF_FREQ4 00H 01H

95H 149 RAMP_CTRL 20H 20H

200H 512 TDM_TRSH1 3CH 3CH
201H 513 TDM_TRSH2 3CH 3CH
202H 514 PRC_TRSH1 20H 20H
203H 515 PRC_TRSH2 20H 20H

21EH 542 PLL_INT_REG 00H 01H

220H 544 RESERVED1 06H 06H
223H 547 RESERVED4 02H 02H

REGISTER NAME

M_CLK = 39.0268MHz

PRESET

M_CLK = 14.72MHz

PRESET

41/43

STA002

42/43

STA002

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are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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