Datasheet ST95P08 Datasheet (SGS Thomson Microelectronics)

8 Kbit Serial SPI EEPROM with Positive Clock Strobe

1 MILLION ERASE/WRITE CYCLES
40 YEARS DA TA RETE NT ION
SINGLE 3V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
2 MHz CLOCK RA TE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CY CLE
E.S.D.PROTECTION GREATER than 4000V
SUPPO RTS POSITIVE CLOCK SPI MODES

8

1

PSDIP8 (B)

0.25mm Frame

ST95P08

8

1

SO8 (M)

150mil Width

DESCRIPTION

The ST95P08 is an 8 Kbit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology. The 8 Kbit memory
is organised as 64 pages of 16 by tes. The memory
is accessed by a simple SPI bus c ompatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q). The device connected to t he bus is selected
when the chip select input (

S) goes low. Commu­nications with the chip can be interrupted with a
hold input (
by a write protect input (

HOLD). The write operation is disabled

W).

T ab le 1. Signal Names

C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect

Figure 1. Logic Diagram

V

CC

D
C
S

W

HOLD

ST95P08

V

SS

Q

AI01315

HOLD Hold
V

CC

V

SS

February 1999 1/16

Supply Voltage
Ground

ST95P08

Figure 2A. DIP Pin Connections

ST95P08

1

SV

2
3

W

4

SS

T ab le 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

T

T

A

STG

LEAD

Ambient Operating Temperature
Storage Temperature –65 to 150 °C
Lead Temperature, Soldering (SO8 package) 40 sec

8
7
6
5

AI01316

CC

HOLDQ
C
DV

(1)

(2)

(PSDIP8 package) 10 sec

Figure 2B. SO Pin Connections

ST95P08

1

SV

2
3

W

SS

4

8
7
6
5

AI01317B

–40 to 85 °C

215
260

CC

HOLDQ
C
DV

°C

V

O

V

V

CC

V

ESD

Notes:

1. Except for the rating "Operating T emperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

2. Depends on range.

3. MIL-STD-883C, 3015.7 (100pF, 1500Ω)

4. EIAJ IC-121 (Condition C) (200pF , 0Ω)

SIGNALS DESCRIPTION
Serial Output (Q ).

fer data serially out of the ST95P08. Data is shifted
out on the falling edge of the serial clock.

Serial Input (D) .

data serially into the device. It receives instructions,
addresses, and data to be written. Input is latched
on the rising edge of the serial clock.

Serial Clock (C).

timing of the serial interface. Instructions, ad­dresses, or data present at the input pin are latched

Output Voltage –0.3 to VCC +0.6 V
Input Voltage –0.3 to 6.5 V

I

Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.

(3)

(4)

4000 V

500 V

the Q pin changes after the falling edge of the clock

The output pin is used to trans-

input.

Chip Select (

S).

This input is used to select the

ST95P08. The chip is selected by a high to low

The input pin is used to transfer

transition on the
time, the chip is deselected by a low t o high t ransi­tion on the

S pin when C is at ’0’ state. At any

S pin when C is at ’0’ state. As soon as
the chip is deselected, the Q pin is at high imped­ance state. This pin allows multiple ST95P08 to

The serial clock provides the

share the same SPI bus. After power up, the chip
is at the deselect state. T r ansition of
when C is at ’1’ state.

on the rising edge of the clock input, while data on

S are ignored

2/16

Figure 3. Block Diagram

ST95P08

HOLD

W

S

C

D

Q

Control Logic

I/O Shift Register

Address Register

and Counter

Y Decoder

High Voltage

Generator

Data

Register

Status

Block
Protect

16 Bytes

X Decoder

AI01272

3/16

ST95P08

T able 3. AC Measurement Conditions

Figure 4. AC Testing Input Output Waveforms

Input Rise and Fall Times ≤ 50ns

0.8V

0.2V

CC

CC

Input Pulse Voltages 0.2V
Input and Output Timing

Reference Voltages

Note that Output Hi-Z is defined as the point where data is no
longer driven.

T able 4. Input Parameters

(1)

(TA = 25 °C, f = 1 MHz )

0.3V

to 0.8V

CC

to 0.7V

CC

CC

CC

Symbol Parameter Min Max Unit

C

IN

C

IN

t

LPF

Note:

1. Sampled only, not 100% tested.

Input Capacitance (D) 8 pF
Input Capacitance (other pins) 6 pF
Input Signal Pulse Width 10 ns

Tabl e 5. DC Characteristics

(T

= 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V)

A

0.7V

0.3V

AI00825

CC

CC

Symbol Parameter Test Condition Min Max Unit

I

LI

I

LO

I

CC

I

CC1

V

IL

V

IH

V

OL

V

OH

Input Leakage Current 2 µA
Output Leakage Current ±2 µA

VCC Supply Current (Active)

C = 0.1 V

@ 2 MHz, Q = Open

S = VCC, VIN = VSS or VCC,

VCC Supply Current (Standby)

S = VCC, VIN = VSS or VCC,

Input Low Voltage – 0.3 0.3 V
Input High Voltage 0.7 V
Output Low Voltage IOL = 2mA 0.2 V
Output High Voltage IOH = –2mA 0.8 V

V

V

= 5.5V

CC

CC

/0.9 VCC ,

CC

= 3V

CC

CC

2mA

50 µA

10 µA

CC

V

VCC + 1 V

CC

V
V

4/16

ST95P08

Table 6. AC Characteristics

(T

= 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V)

A

Symbol Alt Parameter Test Condition Min Max Unit

f

C

t

SLCH

t

CLSH

t

CH

t

CL

t

CLCH

t

CHCL

t

DVCH

t

CHDX

t

DLDH

t

DHDL

t

HXCH

t

CLHX

t

SHSL

t

SHQZ

t

QVCL

t

CLQX

t

QLQH

t

QHQL

t

HHQX

t

HLQZ

(1)

t

W

Note:

1. Not enough characterisation data were availa ble on this parameter at the time of issue this Data Sheet. The typical value is well
below 5ms, the maximum value will be reviewed and lowered when sufficient data is available.

t

t
t
t

t

t

t

DSU

t

t

t

HSU

t

t

t

t
t

t

t

t

f

SU

SH

WH

WL

RC

FC

DH

t

HH

CS

DIS

t

HO

RO

FO

HZ

t

C

Clock Frequency D.C. 2 MHz
S Setup Time 50 ns
S Hold Time 50 ns
Clock High Time 200 ns
Clock Low Time 300 ns
Clock Rise Time 1 µs
Clock Fall Time 1 µs
Data In Setup Time 50 ns
Data In Hold Time 50 ns

RI

FI

Data In Rise Time 1 µs
Data In Fall Time 1 µs
HOLD Setup Time 50 ns
HOLD Hold Time 50 ns

S Deselect Time

4.5V < V
3V < V

< 5.5V 200 ns

CC

< 4.5V 250 ns

CC

Output Disable Time 150 ns

V

Clock Low to Output Valid 300 ns
Output Hold Time 0 ns
Output Rise Time 100 ns
Output Fall Time 100 ns

LZ

HOLD High to Output Low-Z 150 ns
HOLD Low to Output High-Z 150 ns

W

Write Cycle Time 10 ms

5/16

ST95P08

Figure 5. Output Timing

S

C

tCLQX

tQVCL

tCH

tCL

tSHQZ

Q

D

ADDR.LSB IN

MSB OUT MSB-1 OUT LSB OUT

Figure 6. Serial Input Timing

S

C

tDVCH

tSLCH

tCHDX

tQLQH
tQHQL

AI01070B

tSHSL

tCLSH

tCHCL

tCLCH

6/16

D

Q

MSB IN

HIGH IMPEDANCE

tDLDH
tDHDL

LSB IN

AI01071

Figure 7. Hold Timing

S

C

Q

D

HOLD

tCLHX

ST95P08

tHXCH

tHXCH

tCLHX

tHHQXtHLQZ

AI01072B

Write Protect (

protect. When

W).

This pin is for hardware write

W is low, non-volatile writes to the
ST95P08 are disabled but any other operation
stays enabled. When
including non-volatile writes are available.

W is high, all operations

W going
low at any time before the last bit D0 of the data
stream will reset the write enable latch and prevent
programming. No action on

W or on the write
enable latch can interrupt a write cycle which has
commenced.

HOLD ).

Hold (

HOLD pin is used to pause

The
serial communications with a ST95P08 without
resetting the serial sequence. To take the Hold
condition into account, the product must be se­lected (
a high to low transition on
resume the communications,

S = 0). Then the Hold state is validated by

HOLD when C is low. To

HOLD is brought high
when C is low. During Hold condition D, Q, and C
are at a high impedance state.

When the ST95P08 is under Hold condition, it is
possible to deselect it. However, the serial commu­nications will remain paused after a reselect, and
the chip will be reset.

OPERATIONS

All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after

the chip select (

S) goes low. Prior to any operation,
a one-byte instruction code must be entered in the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C). To enter an instruction code, the product must
have been previously selected (

S = low). Table 7
shows the instruction set and format for device
operation. When an invalid instruction is sent (one
not contained in Table 7), the chip is automatically
deselected. For operations that read or write data
in the memory array, bit 3 of the instruction is the
MSB of the address, otherwise, it is a don’t care.

Write Enable (WREN) and Wri te Disable (WRDI)

The ST95P08 contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation. The WREN instruction will set the latch
and the WRDI instruction will reset the latch. The
latch is reset under all the following conditions:

W pin is low

–
– Power on
– WRDI instruction executed
– WRSR instruction executed
– WRITE instruction executed
As soon as the WREN or WRDI instruction is

received by the ST95P08, the circuit executes the
instruction and enters a wait mode until it is dese­lected.

7/16

ST95P08

Read Status Register (RDSR)

The RDSR instruction provides access to the status
register. The status register may be read at any
time, even during a non-volatile write. As soon as
the 8th bit of the status register is read out, the
ST95P08 enters a wait mode (data on D are not
decoded, Q is in Hi-Z) until it is deselected.

The status register format is as follows:

b7 b0

1 1 1 1 BP1 BP0 WEL WIP

BP1, BP0: Read and write bits
WEL, WIP: Read only bits.

During a non-volatile write to the memory array, all
bits BP1, BP0, WEL, WIP are valid and can be read.
During a non volatile write t o the status register , the
only bits WEL and WIP are valid and can be read.
The values of BP1 and BP0 read at that time
correspond to the previous contents of the status
register.

The Write-In-Process (WIP) read only bit indic ates
whether the ST95P08 is busy with a write opera­tion. When set to a ’1’ a write is in progress, when
set to a ’0’ no write is in progress.

The Write Enable Latch (WEL) read only bit indi­cates the status of the write enable latch. When set
to a ’1’ the latch is s et, when set to a ’0’ t he latch is
reset.

The Block Protect (BP0 and BP1) bits indicate the
extent of the protection employed. These bits are
set by the user issuing the WRSR instruction.
These bits are non-volatile.

Write Status Register (WRSR)

The WRSR instruction allows the user to select the
size of protected memory . The ST95P08 is div ided
into four 2048 bit blo cks. The user may read the

blocks but will be unable to write within the selected
blocks.

The blocks and respective WRSR control bit s are
shown in Table 6.

When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of
rising edge of

S must appear after the 8th bit of the

S. This

Status Register content (it must not appear a 17th
clock pulse before the rising edge of

S), otherwise

the internal write sequence is not performed.

Read Operation

The chip is first selected by putting

S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 and 4 of the
read instruction contain address bits A9 and A8
(most significant address bits). These bits ar e used
to select the first or second page of the device.
Then, the data stored in the m emory at the selected
address is shifted out on the Q output pin; each bit
being shifted out during the falling edge of the clock
(C). The data stored in the memory at the next
address can be read in s equence by continuing to
provide clock pulses. The byte address is automat-

T ab le 7. Array Addresses P rotect

Status Register Bits

BP1 BP0

0 0 none
0 1 300h - 3FFh
1 0 200h - 3FFh
1 1 000h - 3FFh

Array Addresses

Protected

T ab le 8. Instruction Set

Instruction Description Instruction Format

WREN Set Write Enable Latch 000X X110

WRDI Reset Write Enable Latch 000X X100
RDSR Read Status Register 000X X101
WRSR Write Status Register 000X X001

READ Read Data from Memory Array 000A A011

WRITE Write Data to Memory Array 000A A 010

Notes:

A = 1, Upper page selected
A = 0, Lower page selected
X = Don’t care

8/16

ST95P08

ically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached (1FFh), the address counter
rolls over to 0h allowing the read cycle to be con­tinued indefinitely. The read operation is terminated
by deselecting the chip. The chip can be deselected
at any time during data output. Any read attempt
during a non-volatile write cycle will be rejected and
will deselect the chip.

Byte Write Operation

Prior to any write attempt, the write enable lat ch
must have been set by issuing the WREN instruc­tion. First, the device is selected (

S = low) and a
serial WREN instruction byte is issued. Then, the
product is deselected by taking

S high. After the
WREN instruction byte is sent, the ST95P08 will
set the write enable latch and then remain in
standby until it is deselected. Then, the write state
is entered by selecting the chip, issuing a one byte
address (A7-A0), and one byte of data. Bits 3 and
4 of the write instruction contain address bits A9
and A8 (most significant address bits).

S must
remain low for the entire duration of the operation.
The product must be deselected just after the eigth

bit of data has been latched in. If not, the write
process is cancelled. As soon as the product is
deselected, the self-timed write cycle is initiated.
While the write is in pr ogress, the status register
may be read to check BP1, BP0, WEL and WIP.
WIP is high during the s elf-timed write cycle. When
the cycle is close to completion, the write enable
latch is reset.

Page Write Operation

A maximum of 16 bytes of data may be written
during one non-volatile write cycle. All 16 bytes
must reside on the same page. The page write
mode is the same as the byte write mode except
that instead of deselecting after the first byte of
data, up to 15 additional bytes can be shifted in
prior to deselecting the chip. A page address begins
with address xxxx 0000 and ends with xxxx 1111.
If the address counter reaches xxxx 1111 and the
clock continues, the counter will roll over to the first
address of the page (xxxx 0000) and overwrite any
previous written data. The progr amming cycle will
only start if the

S transition does occur at the clock
low pulse just after the eigth bit of data of a word is
received.

Figure 8. Read Operation Sequence

S

21 345678910111213141516171819

0

C

INSTRUCTION BYTE ADDRESS

D

HIGH IMPEDANCE

Q

A7

20 21 22 23

A6 A5 A4 A3 A2 A1 A0A9 A8

DATA OUT

7 65432 0

1

AI01318

9/16

ST95P08

Figure 9. Write Enable Latch Sequence

S

C

D

Q

21 34567

0

HIGH IMPEDANCE

AI01430

Figure 10. Write Operation Sequence

S

21 345678910111213141516171819

0

C

INSTRUCTION BYTE ADDRESS

D

HIGH IMPEDANCE

Q

A7

20 21 22 23

DATA BYTE

A6 A5 A4 A3 A2 A1 A0A9 A8

7 65432 0

1

AI01319

10/16

Figure 11. Page Write Operation Sequence

S

21 345678910111213141516171819

0

C

ST95P08

20 21 22 23

INSTRUCTION BYTE ADDRESS

A7

D

S

2625 27 28 29 30 31

C

DATA BYTE 2

D

7 6 321054

A6 A5 A4 A3 A2 A1 A0A9 A8

8+8N

9+8N

DATA BYTE N

7

6 3210247 65432

5 4

Figure 12. RDSR: Read Status Register Sequence

10+8N

11+8N

12+8N

13+8N

DATA BYTE 1

7 65432 0

14+8N

15+8N

136

137

138

139

DATA BYTE 16

140

141

1

1

142

7

143

0

AI01320

S

21 3456789101112131415

0

C

INSTRUCTION

D

Q

HIGH IMPEDANCE

STATUS REG. OUT

7 6543210

MSB

AI01431

11/16

ST95P08

Figure 13. WRSR: Write Status Register Sequence

S

21 3456789101112131415

0

C

INSTRUCTION STATUS REG.

D

HIGH IMPEDANCE

Q

AI01432

POWER ON STATE

After a Power up the ST95P08 is in the following
state:

– The device is in the low power standby state.
– The chip is deselected.
– The chip is not in hold condition.
– The write enable latch is reset.
– BP1 and BP0 are unc hanged (non-volatile bits).

DATA PROTECTION AND PROTOCOL SAFETY

– All inputs are protected against noise, see T able

3.

– Non valid

S and HOLD transitions are not taken

into account.
S must come high at the proper clock count in

–

order to start a non-volatile write cycle (in the
memory array or in the c ycle status register). The
Chip Select

S must rise during the clock pulse

following the introduction of a multiple of 8 bits.

– Access to the memory array during non-volatile

programming cycle is cancelled and the chip is
automatically deselected; however, the pro­gramming cycle continues.

– After either of the following operations (WREN,

WRDI, RDSR) is completed, the chip enters a

wait state and waits for a deselect.
– The write enable latch is reset upon power-up.
– The write enable latch is reset when

W is brought

low.

INITIAL DELIVERY STATE

The device is delivered with the memory array in a
fully erased state (all data set at all "1’s" or FFh).
The block protect bits are initialized to 00.

12/16

ORDERING INFORMATION SCHEME

Example: ST95P08 M 6 TR

ST95P08

Data Strobe

(1)

P

D Q

Notes:

1. Data In strobed on rising edge of the clock (C) and Data Out synchronized from the falling edge of the clock.

2. Temperature range on request only, 5V ± 10% only.

Package

B PSDIP8

0.25 mm Frame

M SO8

150mil Width

Temperature Range

1 0 to 70 °C
6 –40 to 85 °C

(2)

3

–40 to 125 °C

Option

TR Tape & Reel

Packing

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Package, etc...) or for further information on any aspect of this device, please
contact the STMicroelectronics Sales Office nearest to you.

13/16

ST95P08

PSDIP8 - 8 pin Plastic S k i nny DIP, 0.25mm lead f r ame

Symb

Typ Min Max Typ Min Max

A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014

D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.150

N8 8

CP 0.10 0.004

PSDIP8

mm inches

Drawing is not to scale.

14/16

A2

A1AL

B

e1

B1

D

N

C

eA
eB

E1 E

1

PSDIP-a

SO8 - 8 lead Plastic Small Outline, 150 mils body width

ST95P08

Symb

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°

N8 8

CP 0.10 0.004

mm inches

Drawing is not to scale.

B

SO-a

h x 45˚

A

C

e

CP

D

N

E

H

1

LA1 α

15/16

ST95P08

Information furnished is believ ed to be accurate and reliable. How ever, STMicroelectronic s assumes no responsi bility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and repl aces all information previous ly supplied. STMicroelect ronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

© 1999 STMicroelectronics - All Rights Reserved

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16/16