- FLAT FREQUENCY RESPONSE DOWN TO
10Hz FOR 56Kps MODEM
.
INTERFACE WITH CAPACITIVE ISOLATION
BARRIER
.
CALLER ID INTERFA CE
.
DIGITAL PHONE LINE OR OVER LOOP
CURRENT LIMIT DETECT
.
PHONE LINE IN USE CHECK
APPLICA TIONS
.
MODEMS UP TO V.34, 33.6KBPS A ND 56K bps
.
PCMCIA CARDS
.
FAX MA CHINES
.
PERSONAL DIGITAL ASSISTANTS
.
ANSWERING MACHINES
.
HIGH FEATURE PHONES
.
WEBPHONES AND SET TOP BOXES
DESCRIPTION
ST952 is a line interface designed to implement
Modem application up to 56Kbps and Voice applications.
ST952 interfaces between telephone line and capacitive isolation barrier.
A complete D. A.A. is made with ST75951 which
interfaces between capacitive isolation barrier and
the DSP or HSP signals.
Tip
Digital
ST75951ST952
Signals
It incorporates Krypton Isolation Inc. patented silicon DAA technology.
The ring burst signal is detected by ST952 and is sent
to ST75951 through the capacitive isolation barrier.
Using t he control signals given by ST7 5951, through
the cap ac itiv e isolation barrier, ST952 ac ti va tes t he
off-hook or the CLID external transistor sw it c h.
Ring
ST952
D.A.A. LINE INTERFACE
PRELIMINARY DATA
TQFP32
(Thin Plastic Quad Flat Pack)
ORDER CODE :
If CLID external transistor switch is enabled, a
limited amount of current, less than 1mA, is drawn
from the line.
In off-hook state, ST952 DC voltage, 4V at a 20mA
line current, allows to interface with most of public
networks in the world.
The return loss is externally adjustable t o real or
complex impedance.
In case of a wrong connection in a digital phone
line, ST952 detects the over current value and
sends to ST75951 an alert signal through the ca pacitive isolation barrier.
Before starting a line connection, ST952 is abled
to check if the line is used by an other terminal
connected on the same telephone line.
PIN CONNECTIONS
16
17TER1
SET
VDR
LINE
IDG
952-02.EPS
IDI
LINI
GAIN
18
19
20
21
22
23
24
25 26 27 28 29
(7 x 7 x 1.4mm)
TER2
VDREF
IREF
AIN
AOUT
LCOM
ST952TQF7
OHC
NC
NCNC
30 31 32
D1
NC
101112131415
COM
D2
IDC
9
8
7
6
5
4
3
2
1
LCOM
LIM1
LIM2
TOFF
D6
D5
RIN
D4
D3
952-01.EPS
December 1998
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/12
Page 2
ST952
PIN LIST
Pin NumberNameTypeDescription
1D3OutputIsolation Signal Output
2D4OutputIsolation Signal Output
3RINInputRing Signal Input
4D5InputIsolation Control Signal Input
5D6InputIsolation Control Signal Input
6TOFFSupplyInternal Reference Supply
7LIM2InputLoop Current Limiter Control
8LIM1OutputLoop Current Limiter Control
9IDCOutputCaller ID Control Output
10COMOutputOff-hook & ID Commun Output
11OHCOutputOff-hook Control Output
12N.C.-Not Connected
13N.C.-Not Connected
14IREFInputCurrent Reference Setting
15VDREFSupplyInternal Reference Pin
16TER2OutputCurrent Regulator Control Feedback
17TER1OutputCurrent Regulator Control Output
18SETInputCurrent Regulator Filter
19VDRSupplyLine DC Voltage Regulator
20LINEOutputLine AC Signal Output
21IDGInputCaller ID Voltage Reference Input
22IDIInputCaller ID Signal Input
23LINIInputLine AC Signal Input
24GAINInputTransmit Gain / Trans-Hybrid Loss Set
25LCOMGroundLine Side Common Ground
26AINInputAnalog Transmit Signal Input
27AOUTOutputAnalog Transmit Signal Output
28N.C.-Not Connected
29N.C.-Not Connected
30D1InputIsolation Signal Input
31D2InputIsolation Signal Input
32LCOMGroundLine Side Common Ground
Note :
Pins 12, 13, 28 and 29 must be left opened.
952-01.TBL
2/12
Page 3
PIN DESCRIPTION
D1 - D2
These pins input the A C signal modulated at Fmod
coming from ST75951 through the capacitive isolation barrier.
ST952
RIN
During the ring burst, a 1MHz oscillator is pow ered
on this pin and a 6V
and D4 to indicate the ring presence.
/1MHz signal is sent on D3
PP
D3 - D4
These pins output the AC signal modulated at Fmod
in off-hook mode and at Fmod /2 in CLID mode to
ST7 59 51 through t he capacitiv e isolatio n barrier .
In ring mode, these pins out put the ring information,
a differential 6V
/1MHz signal.
PP
D5 - D6
These control pins input a 5V
/Fmod signal com-
PP
ing from ST75951 through the capacitive isolation
barrier.
These signals control the off-hook and CLID external transistor switches and are sent to the internal
transmit demodulator and receive modulator.
Off-hook mode is enabled with a 5V
/Fmod signal
PP
sent on D5 and D6 inputs with an opposite phase
(see Figure 1). With a dedicated application it is
possible to reduce the input level to 3V
CLID mode is enabled with a 5V
.
PP
/Fmod signal
PP
sent on D5 input only ( s ee Figure 2). With a dedicated application it is possible to reduce the input
level to 3V
PP
.
Figure 1
D5
D6
5V
Fmod
5V
Fmod
LINE
DC positive line connection and line AC signal output.
LCOM
Negative line connection.
LINI
Line AC signal input in off-hook mode.
AIN - AOUT
The transmit signal coming from AIN pin is injected
in AOUT pin to the 2W/4W internal converter stage.
The line echo is minimized if R3, connected between LINE and VDR pins is equal to 620Ω.
IREF
Internal reference current source setting, R4 must
be equal to 82kΩ.
VDR
Power supply for the transmit and receive paths in
Off-Hook mode.
VDREF
Internal resistor reference.
SET
Line gyrator AC/DC filter.
OHC
When D5 and D6 inputs a 5V
/Fmod signal in
PP
opposite phase, this pin puts ON the hook swit ch
external Q1/Q2 transistor stage.
IDC
When D5 input a 5V
/Fmod sign al, this pin puts
PP
ON the CLID external Q3/Q4 transistor stage.
R2 limits t he line current in CL ID mode at 1mA
max.
COM
Commun output for off-hook and CLID external
transistor stages
TER1 - TER2
These pins control the external Q5 transistor, in
which the main part of the line current goes
through to meet the line DC, V = f(I
952-03.EPS
), termination
L
requirements.
IDI
Line AC signal input in CLID mode.
IDG
Power supply for the r ec eive path in CLID mode.
LIM1 - LIM2
200mA over current detection for device protection.
TOFF
Internal Reference Supply.
Figure 2
GAIN
R1 connected on this pin fi xes the transm it gain.
The R1 recommanded value, on a 600Ω AC line
termination, is 82Ω.
D5
D6
5V
Fmod
3/12
952-04.EPS
Page 4
ST952
BLOCK DIAGRAM
C8
Tip
2627
R8
Ring
C6
R7
R6
R2
IDG
21
CLID
Q4Q5
Q2
R3
C3
VDR
191415
VOLTAGE
REFERENCE
C4
R4
DREF
REF
V
I
VOLTAGE
OFF-HOOK
REFERENCE
C5
TER1
TER2
R5
Q3
Q1
C1
R1
LINE
GAIN
20
24
Output
Amplifier
23
C2
LINI
IDI
22
C7
SET
R9
1617 18
4/12
AOUTAIN
ST952
FILTER
LOW PASS
FILTER
HIGH PASS
30
31
D1
D2
Fmod
2W/4W
& HYBRID
CONVERTER
1
2
D3
D4
ST75951
RING
DETECT
3
RIN
Fmod
LIMITER
CURRENT
CLID & OFF-HOOK
SWITCH CONTROL
4
5
D5
D6
8
LIM1
7
LIM2
IDC
9
OHC
11
COM
10
TOFF
6
LCOM
25
LCOM
32
C9
952-05.EPS
Page 5
ST952
ABSOL UT E MAXIMUM RATING
(AGND = DGND = 0V , all voltages with respect to 0V)
Symbol ParameterValueUnit
V
T
MLINE
oper
Positive Line Voltage Continuous14V
Operating Temperature0, +70°C
TstgStorage Temperature-55, +150°C
THERMAL DATA
SymbolParameterValueUnit
R
th (j-a)
ELECTRICAL CHARACTERI STICS
Junction-ambient Thermal ResistanceMax.80
= 25oC, unless otherwise specified)
(T
amb
SymbolParameterTest ConditionsMin. Typ. Max. Unit
DC AND AC TERMINATION (see Figure 3)
V
LINE
ZLOSSReturn LossI
RECEIVE PATH (I
GrxReceive GainV
GrfReceive Frequency ResponseV
RxhdReceive 2nd/3th/4th Harmonic DistortionV
ThlTrans-Hybrid LossV
RnReceive Noise FloorV
TRANSMIT PATH (IL = 20mA, f = 1kHz, V
GtxTransmit GainV
GtfTransmit Frequency ResponseV
TxhdTransmit 2nd/3th/4th Harmonic Disto rtion V
Line VoltageIL = 20mA
IL = 120mA
= 20mA, V
L
f = 200 to 4000Hz24
= 20mA, f = 1kHz, see Figure 4)
L
= 0dBV, V
LAC
= 0dBV, V
LAC
f = 200 to 3400Hz
f = 50 to 200Hz
= 0dBV, V
LAC
f = 150Hz
f = 1000Hz
= 0, V
LAC
Fmod = 1.5MHz
= V
LAC
f = 200-3400Hz, 100Hz BW
= 0, see Figure 4)
LAC
= -6dBV-0.500.5dB
TAC
= -6dBV, f = 200 to 4000Hz-0.2+0.2dB
TAC
= -6dBV, Fmod = 1.5MHz-82dBV
TAC
TAC
10.5
= -6dBV
LAC
= 0-0.500.5dB
TAC
= 0
TAC
-0.1
-0.5
= 0
TAC
= -6dBV,
TAC
3035dB
= 0,
4.1
-79
-82
-93dBV
TxmaxMax Line Drive Voltage3V
TnTransmit Noise FloorV
= 0,
TAC
f = 200-3400Hz, 100Hz BW
-93dBv
POWER AND DC LOGIC INPUT (see Figure 5)
V
I
LINE
OFH
Line CurrentST952 Line Pin + Ic(Q5)10120mA
Hook Switch InputD5 and D6 Input
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No licence is granted by implicat ion or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or sys te ms
without express written approv al of STMi cr oelec troni cs.
Purchase of I
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