Datasheet ST52E420, ST52T420, ST52T410 Datasheet (SGS Thomson Microelectronics)

®

E420

8-BIT INTELLIGENT CONTROLLER UNIT (ICU)

Memories



Upto4KbytesOTP



128 bytes of RAM



Readout Protection

Core



Register File Based Architecture



55 instructions



Hardware multiplication and division



Decision Processor for the implement ation of
Fuzzy Logic algorithms

Clock and Power Supply



Up to 20 M H z clock frequency.



Power Saving features

ST52T410/T420/

ST52T410/T420/E420

Three Timer/PWMs, ADC, WDG

PRELIMINARY DATASHEET

Interrupts



Up to 5 interrupt vec tors



Top Level External Interrupt (INT)

I/O Ports



19 I/O PINs configurable in Input and Output
mode



High current sink/source in all pins.

Peripherals



3Programmable 8-bit Tim er/PWM s withinternal
16-bit Prescaler featuring:

– PWM output
– Input capture
– Output compare
– Pulse generator mode



On-chip 8-bit Sam ple and Hold A/D C onv erter
with 8-channel analog multiplexer (ST52T420/
E420 only)



Watchdog timer

Development tools



High level Software tools



Emulator



Low cost Programmer



Gang Programme r

Rev. 1.6 - November 2002 1/84

ST52T410/T420/E420

ST52T410/ST52x420 Device Summ ary

Device NVM RAM

ST52T420G0py 1K OTP 128 3x8-bit 8-Ch - Yes 3.0-5.5 V 19 Dip/So 28

ST52T420G1py 2K OTP 128 3x8-bit 8-Ch - Y es 3.0-5.5 V 19 Dip/So 28

ST52T420G2py 4K OTP 128 3x8-bit 8-Ch - Y es 3.0-5.5 V 19 Dip/So 28

ST52E420G2D6 4K EPROM 128 3x8-bit 8-Ch - Yes 3.0-5.5 V 19 Cdip 28

ST52T410G0py 1K OTP 128 3x8-bit - Yes 2.7-5.5 V 19 Dip/So 28

ST52T410G1py 2K OTP 128 3x8-bit - Yes 2.7-5.5 V 19 Dip/So 28

ST52T410G2py 4K OTP 128 3x8-bit - Yes 2.7-5.5 V 19 Dip/So 28

Timers

PWM

ADC SCI Watchdog

Operating

Supply

I/O Package

2/84

ST52T410/T420/E420

TABLE OF CON­TENTS

TABLE OF CONTENTS

1GENERALDESCRIPTION......................................... 7

1.1Introduction...................................................................7

1.2 Functional Desc ript ion . .........................................................7

1.2.1MemoryProgrammingMode................................................ 7

1.2.2Workingmode............................................................ 8

1.3PinDescription...............................................................12

2INTERNALARCHITECTURE...................................... 15

2.1 ST52T410/ST5 2x420 Operating M odes . ...........................................15

2.2ControlUnitandDataProcessingUnit.............................................15

2.2.1ProgramCounter ........................................................ 15

2.2.2Flags.................................................................. 15

2.3AddressSpaces..............................................................17

2.3.1RAMandSTACK........................................................ 17

2.3.2 Input Registers Bench . . . ................................................. 18

2.3.3ConfigurationRegisters ................................................... 19

2.3.4OutputRegisters......................................................... 20

2.4 Arithmetic Logic Unit. . . ........................................................21

3EPROM....................................................... 24

3.1EPROMProgrammingPhaseProcedure...........................................25

3.1.1EPROMOperation....................................................... 26

3.1.2EPROMLocking......................................................... 26

3.1.3EPROMWriting ......................................................... 26

3.1.4EPROMRead/VerifyMarginMode........................................... 27

3.1.5StandbyMode.......................................................... 27

3.1.6IDcode................................................................ 27

3.2EpromErasure...............................................................27

4INTERRUPTS.................................................. 28

4.1InterruptOperation............................................................28

4.2 Global Interrupt Request Enabling ................................................28

4.3InterruptSources.............................................................29

4.4 Interrupt Maskability . . . ........................................................29

4.5InterruptPriority..............................................................31

4.6InterruptsandLowpowermode..................................................33

4.7InterruptRESET..............................................................33

5CLOCK,RESET&POWERSAVINGMODE.......................... 34

5.1SystemClock................................................................34

5.2 RESET .....................................................................34

5.3PowerSavingMode...........................................................34

5.3.1WaitMode.............................................................. 34

5.3.2HaltMode.............................................................. 35

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ST52T410/T420/E420

6FUZZYCOMPUTATION(DP)...................................... 37

6.1FuzzyInference ..............................................................37

6.2FuzzyficationPhase...........................................................37

6.3InferencePhase..............................................................37

6.4 Defuzzyfication . ..............................................................38

6.5 Input Members hip Function . . . ..................................................38

6.6OutputSingleton..............................................................39

6.7FuzzyRules .................................................................39

7I/OPORTS.................................................... 41

7.1Introduction..................................................................41

7.2 Input Mode ..................................................................41

7.3OutputMode.................................................................42

7.4AlternateFunctions............................................................42

7.5I/OPortConfigurationRegisters..................................................43

8A/DCONVERTER(ST52X420ONLY)............................... 47

8.1Introduction..................................................................47

8.2 Operational Description ........................................................47

8.2.1OperatingModes........................................................ 48

8.2.2PowerDownMode....................................................... 49

8.3A/DRegistersDescription.......................................................49

9WATCHDOGTIMER............................................. 50

9.1 Operational Description ........................................................50

9.2RegisterDescription...........................................................51

10PWM/TIMER.................................................. 52

10.1TimerMode.................................................................52

10.2PWMMode.................................................................54

10.3TimerInterrupt ..............................................................55

11ELECTRICALCHARACTERISTICS ............................... 66

11.1ParameterConditions.........................................................66

11.1.1MinimumandMaximumvalues............................................ 66

11.1.2Typicalvalues.......................................................... 66

11.1.3Typicalcurves.......................................................... 66

11.1.4 Loading c apac it or ....................................................... 66

11.1.5Pininputvoltage........................................................ 66

11.2AbsoluteMaximumRatings ....................................................66

11.3 Recommended Operating Condition. . . ...........................................68

11.4SupplyCurrentCharacteristics..................................................69

11.5ClockandTimingCharacteristics................................................71

11.6MemoryCharacteristics .......................................................72

11.7ESDPinProtectionStrategy....................................................73

11.7.1 Standard Pi n Protection . ................................................. 73

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ST52T410/T420/E420

11.7.2 Multi-supply C onfiguration ................................................ 74

11.8PortPinCharacteristics .......................................................75

11.8.1 General Charact eristics . ................................................. 75

11.9ControlPinCharacteristics.....................................................78

11.9.1 RESET pin ............................................................ 78

11.9.2VPPpin............................................................... 78

11.108-bitA/DCharacteristics......................................................79

ORDERINGINFORMATION........................................ 83

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ST52T410/T420/E420

6/84

ST52T410/T420/E420

1 GENERAL DESCRIPTION

1.1 Introduction

ST52T4 10/ST52x420 are 8- bit Intelligent Control
Units (ICU) of t he ST Five Family, which can
perform both boolean and fuzzy algorithms i n an
efficient manner, in order to reach the best
performances that the t wo methodologies allow.

ST52T410/ ST52x420 are produced b y
STMicroelectronics using the reliable high
performance CMOS process, including integrated­on-chip peripherals that allow maximization of
system reliability , decreasin g system costs and
minimizing the nu mber of external components.

The fle xible I/O c onfigu ration of ST 52x4 00/440
allows for an interface with a wide range of external
devices, like D/A converters or power control
devices.

ST52T410/ST52x420 pins are configurable,
allowing the user to set the input or output signals
on each single pin.

A hardware multiplier (8 b it by 8 bit with 16 bi t
result) and a divide r (16 bit over 8 bit with 8 bit
result and 8 bit remainder) are available to
implement complex fu nctions by usi ng a single
instruction. The program memory utilization and
computational speed is optimized.

Fuzzy Logic dedicated structures in ST52T410/
ST52x420 ICU’s can be exploited to model
complex systems with high accuracy in a useful
and easy way.

Fuzzy Expert Systems for overall system
management and fuzzy Real time Controls can be
designed to increase performa nces at highly
competitive costs.

The linguistic approach characterizing Fuzzy Logic
is based on a set of IF-THEN rules, which describe
the control behavior, as well as on Membership
Functions, w hich are associated to input and
output variables.

Up to 334 Member ship Functions, with triangular
and trapezoidal shapes, or singleton values are
available to describe fuzzy variables.

The Timer/PW M peripheral allows the
management of power devices and timing signals,
implementing different operating modes and high
frequency PWM (Pulse With Modulation) controls.
Input Capture an d Output Compare f unc tions are
available on the TIMER.

The programmable Timer has a 16 bit Internal
Prescaler and an 8 bit Counter. It can use internal
or external Start/Stop signals and clock.

An internal prog rammable Watchdog is ava il able
to avoid loop errors and to reset the ICU.

ST52x420 includes an 8-bit Analog to Digital
Converter with an 8-analog channel Multiplexer.
Single/Multiple channels and Single/Sequence
conversion modes are supported.

In order to optimize energy consumption, two
different power saving modes are availabl e: Wait
mode and Halt mode.

Program Memory (EPROM/O TP) addressing
capability addresses up to 8 K bytes of memory
locations to store both program instructions and
permanent data.

EPROM can be locked by the user to prevent
external undesired operations.

Operations may be performed on data stored in
RAM, allowing the direct combination of new input
and feedback data. All bytes of RAM are used like
Register File.

OTP (One Time Programmable) v ersion devices
are fully compatible with t he EPROM windowed
version, which m ay be used for prototyping and
pre-production phases of development.

A powerful d ev elopment env ironment c ons isting of
a board a nd software too ls allows an easy
configuration and us e of ST52T410/ST52x420.

TM

TheVISUALFIVE

software tool al lows
development of projects through a user-friendly
graphical interface and optimization of generated
code.

1.2 Functional Description

ST52T410/ST52x420 ICUs can work in two
modes:

■ Memory Programming Mode

■ Working Mode

according to RESET and Vpp signals levels (see
pins description).

Note: When RESET=0 it is advisable n o t to use
the sequence “101010“ to port P A (7 : 2).

1.2.1 Memory Programming Mode.

The ST52T410/ST52x420 memory is loaded in the
Memory Programming Phas e. All fuzzy and
standard instructions are written inside the
memory.

This phase starts by setting the control signals as
illustrated below:

RESET

V

ss

TEST V

V

ss

12V/V

PP

DD

7/84

ST52T410/T420/E420

When this phase starts, the ST52T410/ST52x420
core are set to RESET status; then 12V are applied
to the Vpp pin in order t o start EPRO M
programming. A signal app lied to PB1 is used to
increment the m emory address; the da ta is
supplied to PORT A (see EPROM programming for
further details).

1.2.2 Working mode.

Below are the cont ro l signals of this mode:

RESET TEST V

V

DD

V

SS

PP

V

SS

The processor sta rts the working phase following
the instructions, whic h have been previousl y
loaded in the memory.

ST52T410/ST52x 420’s internal struct ure includes
a computational block, CO NTROL UNIT (CU) /
DATA PROCESSIN G UNIT (DPU), which allows

Figure 1.1 ST52x420 SO28 Pin Configuration

proces sing of boolean f unctions and fuz zy
algorithms.

The CU/DPU can m anage up to 334 different
Membership Functions for the f uzzy rules
antecedent part. The rule consequents are “crisp”
values (real numbers). The maxim um number of
rules that can be defined is limited by the
dimens ions of the i mplemented stan dard
algorithm.

EPROM is then sh ared betw een fuzzy and
standard algorithms. The Membership Function
data is stored inside the first 1024 mem ory
locations. The Fuzzy rules are parts of the program
instructions.

The Control Unit (CU) reads the information and
the status deriving from the peripherals.

Arithmetic calculus can be performed on these
values by using the internal CU and the 128 bytes
of RAM, which supports all computations. The
peripheral input c an be fuz zy and/or arithmetic
output, or the values contained in Data RAM and
EPROM locations.

RESET

OSCOUT

OSCIN

TEST

INT/PC0
T0OUT/PC1
T1OUT/PC2
T2OUT/PC3

Ain0/PB0
Ain1/PB1
Ain2/PB2
Ain3/PB3

V

DDA

GNDA

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SO28

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V

VSS
VPP

PA0/T0RES

PA1/T0OUT
PA2/T1OUT
PA3/T2OUT
PA4/T0STRT
PA5/T0CLK
PA6
PA7/PB7/Ain7
PB6/Ain6
PB5/Ain5
PB4/Ain4

8/84

Figure 1.2 ST52x420 PDIP28 Pin Configuration

ST52T410/T420/E420

RESET

OSCOUT

OSCIN

TEST

INT/PC0
T0OUT/PC1
T1OUT/PC2
T2OUT/PC3

Ain0/PB0
Ain1/PB1
Ain2/PB2
Ain3/PB3

DDA

V

GNDA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Figure 1.3 ST52T410 SO28 Pin Configuration

PDIP28

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VDD

VSS

VPP

PA0/T0RES

PA1/T0OUT
PA2/T1OUT
PA3/T2OUT
PA4/T0STRT
PA5/T0CLK
PA6
PA7/PB7/Ain7
PB6/Ain6

PB5/Ain5

PB4/Ain4

RESET

OSCOUT

OSCIN

TEST

INT/PC0
T0OUT/PC1
T1OUT/PC2
T2OUT/PC3

PB0
PB1
PB2
PB3

V

DDA

GNDA

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SO28

V

28

27

VSS

26

VPP

25

PA0/T0RES

24

PA1/T0OUT

23

PA2/T1OUT

22

PA3/T2OUT

21

PA4/T0STRT

20

PA5/T0CLK

19

PA6

18

PA7/PB7

17

PB6

16

15

PB5

PB4

9/84

ST52T410/T420/E420

Figure 1.4 ST52410 PDIP28 Pin Configuration

RESET

OSCOUT

OSCIN

TEST

INT/PC0
T0OUT/PC1
T1OUT/PC2
T2OUT/PC3

PB0
PB1
PB2
PB3

V

DDA

GNDA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

PDIP28

VDD

28

27

VSS

26

VPP

25

24

23

22

21

20

19

18

17

16

15

PA0/T0RES

PA1/T0OUT
PA2/T1OUT
PA3/T2OUT
PA4/T0STRT
PA5/T0CLK
PA6
PA7/PB7
PB6

PB5

PB4

10/84

Table 1.1 ST52T410/ST52x420 SO28 & PDIP28 Pin list

ST52T410/T420/E420

SO28

Pins

1 RESET

NAME Programming Phase Working Phase

General Reset General Reset
2 OSCOUT Oscillator Output
3 OSCIN Oscillator Input
4 TEST Must be tied to V

ss Must be tied to Vss

5 INT/PC0 PHASE signal (PHASE) External interrupt, Digital I/O
6 T0OUT/PC1 Timer/PWM 0 output, Digital I/O
7 T1OUT/PC2 Timer/PWM 1 output, Digital I/O
8 T2OUT/PC3 Timer/PWM 2 output, Digital I/O
9 Ain0/PB0 Address Reset (RST_ADD) Analog Input (*), Digital I/O

10 Ain1/PB1 Address Increment (INC_ADD) Analog Input (*), Digital I/O
11 Ain2/PB2 Configuration Reset (RST_CONF) Analog Input (*), Digital I/O
12 Ain3/PB3 Configuration Increment Analog Input (*), Digital I/O
13 V

DDA Analog Power Supply Analog Power Supply (*)

14 GNDA Analog Ground Analog Ground (*)
15 Ain4/PB4 Analog Input (*), Digital I/O
16 Ain5/PB5 Analog Input (*), Digital I/O
17 Ain6/PB6 Analog Input (*), Digital I/O
18 Ain7/PB7/PA7 I/O EPROM Data Analog Input (*), Digital I/O
19 PA6 I/O EPROM Data Digital I/O
20 T0CLK/PA5 I/O EPROM Data Timer/PWM 0 clock, Digital I/O
21 T0STRT/PA4 I/O EPROM Data Timer/PWM 0 start/stop, Digital I/O
22 T2OUT

/PA3 I/O EPROM Data
23 T1OUT/PA2 I/OEPROM Data
24 T0OUT/PA1 I/OEPROM Data

Timer/PWM 2 compl. output, Digital I/O
Timer/PWM 1 compl. output, Digital I/O
Timer/PWM 0 compl. output, Digital I/O

25 T0RES/PA0 I/O EPROM Data Timer/PWM 0 Reset, Digital I/O
26 V

PP

EPROM Programming Power

supply (12V ± 5%)

EPROM VDD or Vss

27 V
28 V

(*) ST52x420 only

ss Digital Ground Digital Ground

DD Digital Power Supply Digital Power Supply

11/84

ST52T410/T420/E420

1.3 Pin Description
V

DD

, VSS, V

, GNDA, VPP. In order to avoid

DDA

noise disturbances, t he power supply of the digital
part is kept separate from t he power s upply of the
analog part.

Main Power Supply Voltage (5V± 10%).

V

DD.

In t he ST52x410 version the two VDDpins must be
connected togheter.

VSS. Digital circuit ground.

In the ST52x410 version the two VSSpins must be
connected togheter.

V

.AnalogVDDoftheAnalogtoDigital

DDA

Converter.
GNDA. Analog V

Converter. Must be tied to V

of the Analog to Digital

SS

SS

.

VPP. Ma in Power Supply for internal EPRO M

(12.5V±5%, in programming phase) and Operating
MODE selector. During the Programming phase
(programming), V
Working phase V

must be set at 12V. In the

PP

must be equal to VSS.

PP

OSCin and OSCout. Th ese pins are i nte rnally
connect ed with the on-chip osci llato r circuit . A
quartz crystal or a ceram ic resonator can be
connected between these two pins in order to allow
the correct operations of ST52T410/ST52x420
with various s tability/cost t rade-off. An external
clock signal can be applied to OSC in, in this case
OSCout must be floating.

RESET. This signal is used to restart ST52T410/
ST52x420 at the begi nning of its program and to
select the program mode for EPROM.

Ain0-Ain7. Thes e 8 lines are connec ted to the
input of the analog multiplex er. They allow the
acquisition of 8 analog input (ST52x420 only).
During th e Programming phase, Ain0, Ain1, Ain2
and Ain3 are used to manage EPROM operation.

PA0-PA7, PB0-PB7, PC0-PC3. These lines are
organized as I/O port. Each pin can be co nfi gured
as input or output. PA7/P B7 are tied to the same
output. During Programming phas e PA port is used
for EPROM read/write data.

T0RES, T0CLK, T0STRT. These pins are related
with the internal Programmable Timer/PWM 0.
This Timer can be reset externally by using
T0RES. In Working Mode, T0RES resets the
address counter of the Timer. T0RES is active at
low level.

TheTimer0Clockcanbetheinternalclockorcan
be supplied externally by using pin T0CLK.

An external Start/Stop signal can be used to
control the Timer t hrough T0STRT pin .

T0OUT, T1OUT, T2OUT. The TIMER/PWM

outputs are availa ble on these pin s.

T0OUT

, T1OUT, T2OUT.TheTIMER/PWM
complementary outputs are available on these
pins.

TEST. During the Programming and Working
phase it must be set to Vss.

INT. This pin is used to start t he External Interrupt
routine.

12/84

Figure 1.5 ST52X420 Block Diagram

ST52T410/T420/E420

PROGRAM

MEMORY

EPROM

CORE

INTERRUPTS

CONTROLLER

ALU &

DPU

DECISION

PROCESSOR

CONTROL

UNIT

RegisterFile

128 bytes

Input

registers

TIMER/PWM 0

TIMER/PWM 1

TIMER/PWM 2

PORT A

PORT C

PORT B

ADC

PA7:0

PC3:0

PB7:0

VDDA
GNDA

PC FLAGS

POWER SUPPLY OSCILLATOR

VDD VPP VSS OSCIN OSCOUT RESET

WATCHDOG

RESET CIRCUIT

13/84

ST52T410/T420/E420

Figure 1.6 ST52X410 Block Diagram

PROGR AM

MEMORY

EPROM

CORE

INTERRUPTS

CONTROLL ER

ALU &

DPU

TIMER/PWM 0

TIMER/PWM 1

TIMER/PWM 2

PORT A

PA7:0

DECISION

PROCESSOR

CONTROL

UNIT

Regist erFile

128 bytes

Input

registers

PORT C

PORT B

WATCHDOG

PC FLAGS

POWER SUPPLY OSCILLATOR

VDD VPP VSS OSCIN OSCOUT RESET

RESET CIRCUIT

PC3:0

PB7:0

14/84

ST52T410/ST52T420/E420

2 INTERNAL ARCHITECTURE

ST52T410/ST52x420 are made up of the f ollowing
blocks and peripherals:

■ Control Unit (CU) and Data Processing Unit

(DPU)

■ ALU / Fuzzy Co re

■ EPROM

■ 128 Byte RAM

■ Clock Oscillator

■ Analog Multiplexer and A/D Converter

(ST52x420 only)

■ 3PWM/Timers

■ Digital I/O port

2.1 ST52T410/ST52x420 O perating Modes

ST52T410/ST52x420 works in two modes ,
Programming and Working Modes, depending on
the control signals level RESET, TEST and V

PP

The Operating modes are selec ted by setting the
control signal level as specified in the Control
Signals Setting table.

Table 2.1 Control Signals Setting

Control

Signal

RESET V

TEST VSS

VPP 12 V

Pro-

gramming

SS VSS VDD

Reset Working

VSS VSS

SS VSS

V

2.2 Con trol Unit and Data P rocessing Unit

The Control Unit (CU) formally includes five main
blocks. Each blo ck decodes a set of instructions,
generating the appropriate control signals. The
main parts of the CU are illustrated in Figure 2.1.

The five different parts of the CU manage Loading,
Logic/Arithmetic, Jump, Control and the Fuzzy
instruction set.

The block called “Collector” manages the signals
deriving from the different parts of t he CU, defining
the signals for the Data P roc essi ng Unit (DPU) and
the different peripherals of the microcontroller.
The block called “Arbiter” manages the different-

parts of the CU so that only one part of the system
is activated during working mode.

The CU structure is ve ry flexible. It was designed
with the purpose of e asily adapting the c ore of the
microcontroller to market needs. New instruction
sets or new peripherals can be easily included
without changing the structure of the
microcontroller, maintaining c ode compatibility.

The CU reads the instructions stored on EPR OM
(Fetch) and decodes them. According to the
instruction types, the arbiter activates one of the
main blocks of the CU. A fterwards, all the cont rol
signals for the DPU are ge nerated.

A set of 46 different arithmetic, fuzzy and logic
instructions is available. Each instruction r equires
6(fuzzyinstructions)to26(DIVISION)clock
pulses to be performed.

The DPU receives, stores and s ends instructions
deriving from EPROM, RA M or peri pherals in order
to execute t hem.

2.2.1 Program Counter.

The Program Counter (PC) is a 12-bit register that
contains the address of the next memory location
to be proc es s ed by the core. This memory location
may be a n opcode, operand, or an address of an

operand.
The 12-bit length allows direct addressing of a

maximum of 4,096 bytes in t he program spac e.
After having read the c urrent instruction a ddres s,

the PC value is incremented. The result of this
operation is shifted back into the PC.

The PC can be changed in the following ways:

■ JP (Jump)PC = Jump Address

■ InterruptPC = Interrupt Vector

■ RETIPC = Pop (stack)

■ RETPC = Pop (stack)

■ CALLPC = Subroutines address

■ ResetPC = Reset Vector

■ Normal InstructionPC = PC + 1

2.2.2 Fla gs.

The ST52T 410/ ST 52x 420 core i nc ludes a differ­ent set of flags that correspond to 2 different
modes: normal mode and interrupt mode. Each
set of flags consists o f a CARRY flag (C), ZE RO
flag (Z) and SIGN flag (S).

One set (CN, ZN, SN) is used during norm al
operation and one is used during interrupt mode
(CI, ZI, SI). Formally, the user has to manage
only one set of flags: C, Z and S.

15/84

ST52T410/ST52T420/E420

Figure 2.1 Data Processing Unit (DPU)

Figure 2 .2 CU/DP U Block Diagram

16/84

ST52T410/ST52T420/E420

The ST5 2T410/ST52x420 core uses flags that
correspond to the actual mode. As soon as an
interrupt is generated t he ST52T410/ST52x420
core uses the interrupt flags instead of the normal
flags.

Each interrupt lev el has its own set of flags, which
is saved in the STACK together with the Program
Counter. These flags are restored from the STACK
automatically when a RE TI ins truct ion is executed.

Ifthe MCU was in norma l mode before aninterrupt,
the normal flags are restored when the RETI
instruction is executed.

Note:

A CALL subroutine is a normal mode
execution. For this reason, a RET instruction,
consequent to a CALL instruction does not affect
the normal m ode set of flags.

Flags are not cleared during context switching and
remain in the state they were at the end of the last
interrupt routine switching.

The Carry flag is set when an overflow occurs
during arithmetic operations, otherwise it is
cleared.

The Sign flag is set when an underflow occurs
during arithmetic operations, otherwise it is
cleared.

2.3 Address Spaces

ST52T410/ST52x420 has four separat e address
spaces:

Figure 2.3 Address Spaces Description

■ RAM: 128 Bytes

■ Input Registers: 18 8-bit registers

■ Output Registers 9 8-bit registers

■ Configuration Registers: 17 8-bit registers

■ Programmemory up to 4K Bytes

Program memory will be described in further
details in the M EMORY section

2.3.1 RAM and STACK.

RAM memory consists of 128 general purpose 8­bit RAM registers.

All the registers in RAM can be specified by using
a decimal address. For example, 0 identifies the
first register of RAM.

To read or write RAM registers LOAD instructions
must be used. See Table 2.5

Each interrupt level has its own set of flags, which
is saved in the STACK together with the Program
Counter. These flags are restored from th e STACK
automatically when a RETI instruction is executed.

When the instructions like Interrupt request or
CALL are executed, a STACK level is used to push
the PC.

The STACK is located in RAM. For each level of
stack, 2 bytes of RAM are use d. The v alues of this
stack are stored from the last RAM register
(address 127). The maximum level of stack
must be less than 128.

17/84

ST52T410/ST52T420/E420

The STACK POINTER indicates the first level
available to store data. When a subroutine c all o r
interrupt request occurs, the content of the PC and
the current s et of flags are stored into the level
locatedby the STACK POINTER.

When a interrupt return occ urs (RETI instruction),
the data stored in the highest stack level is
restored back into the PC and current flags.

Instead, when a subrout ine return occurs (RET
instruction) the data stored in the highest st ac k
level are restored in the PC not affecting the flags.

These operating modes are illustrated in Figure

2.4.

The user must pay clos e attention to avoid

Note:

overwritingRAM locations where the STACK could
be stored

.

2.3.2 Input Registers Bench.

The Input Registers (IR) bench consists of 18 8-bit
registers containing data or the status of the
peripherals.

Figure 2.4 S tack Operation

All t he registers can be specified by using a
decimal address (for example, 0 identifies the first
register of the IR).

The assembler instruction:

LDRI RAM_Reg. IR_i

loads the value of the i-th I R in the RAM location
identified by the RAM_Reg address.

The first inpu t register is dedicated to s tore the
value of th e stack pointer. The next 8 reg isters
(ADC_OUT_0:7) of the IR are dedicated to the 8
converted values d eriving f rom the ADC
(ST52x420 only). The last 9 Input Registers
contain data from the I/O ports and PWM/Timers.
The following table summarizes t he IR address
and the relative peripherals. In order to simplify the
concept, a mnemonic name is assigned to the
registers. The same name is used in
VISUALSTUDIO

®

development tools

18/84

ST52T410/ST52T420/E420

Table 2.2 Input Registers

IR MNEMONIC NAME PERIPHERAL REGISTER ADDRESS

STACK_POINTER STACK POINTER 0

CHAN 0 (*) A/D CHANNEL 0 (*) 1
CHAN 1 (*) A/D CHANNEL 1 (*) 2
CHAN 2 (*) A/D CHANNEL 2 (*) 3
CHAN 3 (*) A/D CHANNEL 3 (*) 4
CHAN 4 (*) A/D CHANNEL 4 (*) 5
CHAN 5 (*) A/D CHANNEL 5 (*) 6
CHAN 6 (*) A/D CHANNEL 6 (*) 7
CHAN 7 (*) A/D CHANNEL 7 (*) 8

PORT_A PORT A INPUT REGISTER 9
PORT_B PORT B INPUT REGISTER 10
PORT_C PORT C INPUT REGISTER 11

PWM_ 0_COUNT PWM/TIMER 0 COUNTER 12

PWM_ 0_ STATUS PWM/TIMER 0 STATUS REGISTER 13

PWM_ 1_ COUNT PWM/TIMER 1 COUNTER 14

PWM_ 1_ STATUS PWM/TIMER 1 STATUS REGISTER 15

PWM_ 2_ COUNT PWM/TIMER 2 COUNTER 16

PWM_ 2_ STATUS PWM/TIMER 2 STATUS REGISTER 17

2.3.3 Configuration Registers.

The ST52T410/ST52x420 con figurati on R egisters
allow the configuration of all the blocks of the fuzzy
microcontroller. Table 2.3 describes the functions
and the related peripherals of each of the

instructions, the Configuration Registers can be
set by using values stored in the Program Memory
(EPROM) or in RAM.

Use and meaning of eac h register will be described
in further details in the corresponding sec tion.

Configuration Registers. By using the load

Table 2.3 Configuration Registers

CONFIGURATION REGISTER PERIPHERAL DESCRIPTION

REG_CONF 0 INTERRUPT MASK Interrupts mask setting
REG_CONF 1 INTERRUPT PRIORITY INTERRUPT PRIORITY
REG_CONF 2 WATCHDOG TIMER Watchdog Timer Configuration

REG_CONF 3 (*) A/D CONVERTER A/D configuration

REG_CONF 4 PORT A

Set the relative bit like digital input

or digital output

19/84

ST52T410/ST52T420/E420

Table 2.3 Configuration Registers (continued)

CONFIGURATION REGISTER PERIPHERAL DESCRIPTION

REG_CONF 5 PWM/TIMER 0

REG_CONF 6 PWM/TIMER 0

REG_CONF 7 PWM/TIMER 0

REG_CONF 8 PWM/TIMER 1

REG_CONF 9 PWM/TIMER 1

REG_CONF 10 PWM/TIMER 2

REG_CONF 11 PWM/TIMER 2

REG_CONF 12 PORT A

REG_CONF 13 PORT B

REG_CONF 14 PORT B

PWM/Timer 0 Working mode

Configuration

PWM/TIMER 0 Prescaler

configuration and output waveform

selection.

PWM/TIMER 0 Working Mode

Configuration

PWM/TIMER 1 Working Mode

Configuration

PWM/TIMER 1 Prescaler

configuration and output waveform

selection.

PWM/TIMER 2 Working Mode

Configuration

PWM/Timer 2 Prescaler

configuration and output waveform

selection.

Set the bit 0,1 and 2 like Digital I/O

or complementary Timers Output.

Set the relative bit like digital input

or digital output.

Set the relative I/O like Digital or

Analog (*).

REG_CONF 15 PORT C

REG_CONF 16 PORT C

(*) ST52x420 only

2.3.4 Output Registers.

The Out put Registers (OR) c ons ist of 9 registers
containing data f or the microcontroller peripherals
including the I/O Port s.

All registers can be specified by using a decimal
address (for example, 1 identifies the second OR).

By using LOAD instructions the Output Regist ers
(OR) may be set by using values stored in the
Program Memory (LDPE) or in RAM (LDP R)

The assembler instruction:

LDPR OR_i RAM_Reg.

Set the relative I/O like digital input

Set the relative I/O like Digital I/O

or digital output

or Timers Output

loads the value of the RAM location identified by
theaddressRAM_RegintheORi-thTable2.4
describes OR.

In order to simplify the concep t, a mnemonic name
is assigned to OR. The same names are us ed in
VISUALFIVE

TM

5.0 development tools.

Use and meaning of eac h register will be described
in further details in the corresponding sec tion.

20/84

ST52T410/ST52T420/E420

Table 2.4 Output Registers

OR MNEMONIC NAME PERIPHERAL REGISTER ADDRESS

PORT_ A PORT A OR 0
PORT_ B PORT B OR 1

PORT_C PORT C OR 2

PWM_0_COUNT TIMER/PWM 0 COUNTER 3

PWM_0_RELOAD TIMER/PWM 0 RELOAD REGISTER 4

PWM_1_COUNT TIMER/PWM 1 COUNTER 5

PWM_1_RELOAD TIMER/PWM 1 RELOAD REGISTER 6
PWM_ 2_ COUNT TIMER/PWM 2 COUNTER 7

PWM_2_RELOAD TIMER/PWM 2 RELOAD REGISTER 8

2.4 Ari thmetic Logic Unit

The 8-bit Arithmetic Logic Unit (ALU) allows the
performance of arithmetic c alculations and logic
instructions, which can be divided into 5 groups:
Load, Arithmetic, Jump, Interrupts and Program
Control instructions (ref er to the ST52T4 10/
ST52x420 Assembler S et for further details).

The ALU of the ST52T410/ST52x420 can perform
multiplication (MULT) and division (DI V).
Multiplication is performed by using 8 bit operands
storing the resu lt in 2 registers (16 bit values), see
Figure 2.5 and Figure 2.6.

WARNING 1: The current page register value
set with the PGSET instruction is lost after a
jump, call, or an interrupt jump.

The computational time required for each
instruction consists of one clock pulse for each
Cycle plus 3 clock pulses for the decoding phase.

WARNING 2: If the LSB of the multiplication
result is 0, the Zero flag is set alth ough the
result is not 0.

Table 2.5 Load instructions

Load Instructions

Mnemonic Instruction Bytes Cycles Z S C

LDCE LDCE conf, EPROM 3 17 - - -

LDCR LDCR conf, RAM 3 14 - - -

LDFR LDFR FUZZY_i_RAM RAM 3 14 - - -

LDPE LDPE per, EPROM 3 17 - - -

LDPE LDPE per, (RAM) 3 17 - - -

LDPR LDPR reg, RAM 3 14 - - -

LDRC LDRC RAM, const 3 14 - - -

LDRE LDRE RAMi, EPROMi 3 16 - - -

LDRE LDRE (RAMi), (RAMj) 3 18 - - -

21/84

ST52T410/ST52T420/E420

Table 2.5 Load instructions

LDRI LDRI RAM, inp_reg 3 15 - - -

LDRR LDRR RAMi, RAMj 3 16 - - -

PGSET PGSET const 2 9 - - -

Table 2.6 Arithmetic & Logic instructions set

Arithmetic Instructions

Mnemonic Instruction Bytes Cycles Z S C

ADD ADD regi, regj 3 17 I - I

ADDO ADDO regi, regj 3 20 I I I

AND AND regi, regj 3 17 I - -

ASL ASL regi 2 15 I - I
ASR ASR regi 2 15 I I ­DEC DEC regi 2 15 I I -

DIV DIV regi, regj 3 26 I I I
INC INC regi 2 15 I - I

MULT MULT regi, regj 3 19 I - -

NOT NOT regi 2 15 I - -

OR OR regi, regj 3 17 I - -

SUB SUB regi, regj 3 17 I I -

SUBO SUBO regi, regj 3 20 I I I

MIRROR MIRROR regi 2 15 I - -

Table 2.7 Jump I nstruction Set

Jump instructions

mnemonic instruction bytes cycles z s c

CALL CALL addr 3 18 - - -

JP JP addr 3 12 - - -

JPC JPC addr 3 10/12 - - -

JPNC JPNC addr 3 10/12 - - ­JPNS JPNS addr 3 10/12 - - -

JPNZ JPNZ addr 3 10/12 - - -

JPS JPS addr 3 10/12 - - -

JPZ JPZ addr 3 10/12 - - ­RET RET 1 13 - - -

22/84

ST52T410/ST52T420/E420

Table 2.8 Interrupt Instructions Set

Interrupt Instructions

Mnemonic Instruction Bytes Cycles Z S C

HALT HALT 1 7/15 - - ­MEGI MEGI 1 7/15 - - -

MDGI MDGI 1 6 - - -

RETI RETI 1 12 - - -

RINT RINT INT 2 8 - - -

UDGI UDGI 1 6 - - -

UEGI UEGI 1 7/15 - - -

WAITI WAITI 1 7/14 - - -

Table 2.9 Control Instructions Set

Control Instructions

Mnemonic Instruction Bytes Cycles Z S C

FUZZY FUZZY 1 5 - - -

NOP NOP 1 6 ---

WDTRFR WDTRFR 1 7 - - -

WDTSLP WDTSLP 1 6 - - -

Notes:
I affected

- not affected

Figure 2.5 Multiplication Figure 2.6 Division

23/84

ST52T410/ST52T420/E430

3 EPROM

EPROM memory provides an on-chip user­programmable non-volatile m emory, which allows
fast and reliable storage of user data.

EPROM memory c an be locked by the user. In
fact, a memo ry location called Lock Cell i s devoted
to lock EPROM and avoid external operations. A
software identification code, called ID CODE,
distinguishes which software version is stored i n
the memory.

32 kbits of memory s pac e with an 8-bit internal
parallelism (up to 4 kbytes) addressed by a 12-bit
bus are available. The data bus is 8 bits.

Memory has a double supply: V
12V±5% in Programming Phase or to V
Working Phase. V

is equal to 5V± 10% .

DD

is equal to

PP

SS

during

ST52T410/ST52x42 0 EPROM memory is divided
into three main blocks (see Figure ):

■

Interrupt Vectors memory block

(3 through 17)
contains the addresses for the interrupt routines.
Each address is composed of three bytes.

Figure 3.1 Program Memory Organization

■

Mbfs Setting memory block
MemAdd

) contains the coordinates of t he

(18 through

vertexes of every Mbf defined in the program.

■ The maximum value of MemAdd is 1023. This

area is dynamica lly assigned according to the
size of the fuzzy routines. The unused memory
area, if any, is assigned to the Program
Instruction Set memory block.

■ The Program Instructions Set memory block

(MemAdd through 4095) c onta ins theinstruction
set of the us er program.

Locations 0, 1 and 2 contain the address of the first
microcode instruction.The operations that can be
performed o n EPROM during the Program ming
Phase are: Stand By, Memory Writing, Reading
and Verify/Margin Mode, Memory Lock, IDCode
Writing and Verify.

24/84

Table 3.1 EPROM Control Register

VER

GINMODE

D

A

V

ALIDDATAVA

LIDDAT

A

T

A

OUT

OPERATION REGISTER VALUE

Stand By 0

Memory Reading/Verify 1

ST52T410/ST52T420/E430

The operations above are managed by using the
internal 4-bit EPROM Control Register. The
reading phase isexecuted withV
the verify/Margin Mode phase needs V
12V±5%. The Blank Check mus t be a r eading
operation with V

=5V±5%.

PP

Table 3.1 illustrates EPROM Control Register
codes used to identify the operation running.

=5V±5%, while

PP

PP

=

Memory Unlock and

Lock Status Reading

2

Memory Writing 3

Memory Lock 4

ID CODE Writing 5

Memory Lock Status

Reading/Verify

ID CODE Reading/

Verify

9

10

Figure 3.2 Eprom Programming Timing

PA(0:7)

OUT

RST_ADD

3.1 EPROM Pr ogramming Phase Procedure

The Programming mod e is selected by applying
12V±5% voltage or 5V±5% voltage to t he V

PP

pin

and setting the control signal as following:
RESET =Vss
TEST =Vss
If the V

performed.

voltage is 5V ± 5% only readi ng may be

PP

RST_ADD, INC_ADD, RST_CONF, INC_CONF
and PHA S E are the control s ignals used during the
Programming Mode.

PHASE, RST_CONF and RST_ADD signals are
active on level, the others are active on rising
edge.

VALID
DATA

TA

DATA

IN

DA

DATA

OUT

RST_CONF

INC_ADD

INC_CONF

PHASE

MEMORY UNLOCK

100nS

MEMORY WRITING

LOCATION ADDRESS =1

10

S

µ

MEMORY

MAR

IFY

25/84

ST52T410/ST52T420/E430

PHASE and RST_ADD signals are active low,
RST_CONF signal is ac tive high.

Port A is us ed for the memory data I/O.

(See Tab le

3.1 for pin reference onthe different packages)

Memory may be locked by means of the M emory
Lock Status, which is a flag used to enable
EPROM operations.

If Memory Lock Status is 1 all EPROM operation s
are enabled, otherwise the user may only read
(and verify) the OTP code and the Memory Lock
Status.

Only if E PROM is not locked by means of Lock Cell
(see EPROM Locking may EPROM operations be
enabled by changing the Memory Lock Status from
0to1.

RST_ADD signal resets t he memory address
register and the Memory Lock Status. W hen the
RST_ADD becomes high, the memory must be
unlocked in order to read or write.

INC_ADD signal increments the memory address.
RST_CONF signal resets the EPROM Control

Register. When RST_CONF is high, the DATA I/

O Port A is in outpu t, otherwise it is always i n
input.

INC_CONF signa l increments the EPROM Control
Register value.

PHASE signal validates the operation selected by
means of the EPROM Control R egister value.

3.1.1 EP ROM Operati on.

In order to execute an EPROM operation (See
Table 3.1), the corresponding identification value
must be loaded in the EPROM Control Register.
The s ignal timing is the following: RST_ADD= high
and PHASE= high, RST_CONF changes from low
to high lev el, to reset the EPRO M Control Register,
and INC_CONF signal g enerates a number of
positive pulses equal to the value to be loaded.
After this sequence, a negative pulse of the
PHASE signal will validate the operat ion selected.
The minimum PHASE s ignal pulse wi dth must be
10 µs for EPROM Writing Operation and 100 ns for
the others.

When RST_CONF is high, DATA I/O P ort A is
enabled in output and the reading/verifying
operation results are available.

Aftera writing operat ion, when RST_CONF is high,
Port A is in output without valid data.

3.1.2 EPROM Locking.

The Memory Lock operation, which is ident if ied
with the num ber 4 in the EPROM Control Register,

.

writes “0" in the Memory Lock Cell.
At the beginning of an E xternal Operat ion, when

the R ST_ADD signal changes from low level to
high level, the Memory Lock Stat us is “0", therefore
it must be unlocked before proceeding.

In order to unlock the M emory Lock Status the
operation, which is identified by the number 2 in
the EPROM Control Register must be executed
(see Figure 3.2).

Memory Lock Status can be changed only if
Memory Lock Cel l is “1". After a Memory Lock
operation external operations cannot be ex ec uted
except to read (or verify) the OTP Code and t he
Memory Lock Status.

3.1.3 EPROM Writing.

When the memory is blank, all bits are at logic level
“1". Data is introduced by programming only the
zeros in the desired memory location. However, all
input data mu st contain both ”1" and “0".

The only w ay to c hange “0" into ”1" is t o erase the
entire memory (by exposure to Ultra Violet light)
and reprogram it.

The memo ry is in Writing m ode when the EPROM
Control Register value is 3.

TheV

voltage must be 12V±5%, with stable data

PP

on the dat a bus PA(0:7).
The timing signals are the following (see Figure ):

1) RST_ADD and RST_CONF change from low to
high level,

2) two pulses on INC_CONF signal load the
Memory Unlock operation code,

3) a negative pulse (100 ns ) on the PHASE signal
validates the Memory Unlock o peration,

4) a negative pulse on RST_CONF signal resets
the EPROM Control Register,

5) three positive pulses on INC_CONF load the
Memory Writing operation code,

6) a train of positive pulses on INC_ADD signal
increments the memory location addres s up to the
requested value (generally this is a sequential
operation and only one pulse is used),

7) a negative pulse (10 µ s ) on the PHASE signal
validates the Memory Writing operation.

26/84

ST52T410/ST52T420/E430

3.1.4 EPROM Read/Verify Margin Mode.

The read phase is executed with V
instead of the verify phase that needs V

=5V±5%,

PP

PP

12V±5%.
The Memory Verify operation is available in order

to verify the accuracy of th e data written. A
Memory Verify Margin Mode operation can be
executed im mediately after writing each byte, in
this case (see Figure 3.2):

1) a positive pulse on RST_CONF signal resets the
EPROM Control Register, if i t wasn’t already res et;

2) one positive pulse on INC_CONF loads the
Memory Read/Verify operat ion code;

3) a negative pulse (100 ns) on the PHASE signal
validates the Memory Reading / Verify operation;

4) a negative pulse on RST_CONF signal puts in
the PA(0:7) port the value stored in the actual
memory address and resets the EPROM Control
Register;

If an error occurred writing, the user h as to repeat
EPROM writing.

3.1.5 Stand by Mode.

EPROM has a standby mode, which reduces the
active current from 10mA (Programm ing mode) to
less than 100 µ A . Memory is placed in standby
mode by setting the PHASE s ignal at a high level
or when the EPROM Control Regist er value is 0
and the PHASE s ignal is low.

3.1.6 ID code.

A software identification code, called ID code may

=

be written in order to distinguish which software
versionisstoredinthememory.

64 Bytes are dedicated to store this code by using
the address values from 0 t o 63.

The ID Code may be read or verified even if the
Memory Lock Status is “0".

The timing signals are the same as that of a normal
operation.

3.2 Eprom Erasure

The transparent window available in the
CSDIP32W package, allows the memory conte nts
to be erase d by exposure to UV light.

Erasure begins whe n the device is exposed to light
with a wavelength shorter than 4000Å. Sunlight, as
well as some types of artificial light, includes
wavelengths in the 3000-4000Å range which, on
prolonged exposure can cause erasure of me mory
contents. Therefore, it is rec ommended that
EPROM devices be fitted with a n opaque label
over the window area in ord er to prevent
unintentional erasure.

The erasure procedure reco mm ended for EPROM
devices consists of exposure to short wave UV
light having a wavelength of 2537Å. The minimum
integrated dose re co mmended (intensity x ex po­sure time) for complete erasure is 15Wsec/cm 2.

This is equivalent to an erasure time of 15-20
minutes using a UV source having an intensity of
12mW/cm 2 at a distance of 25mm (1 inch) from
the device w indow.

27/84

ST52T410/ST52T420/E420

Global Interrupt

4 INTERRUPTS

The Control Unit (CU) responds to peripheral
events and external events via its interrupt
channels.

When such an events occur, if the related interrupt
is not masked and according t o a priority order, the
current program execution can be suspended to
allow the CU to execute a spec ific response
routine.

Each interrupt is associated with an interrupt
vector that contains the memory address of the
related interrupt serv ice routine. Each vector is
located in the Program Space (EPROM Memory)
at a fixed address (see Interrupt Vec tors Table

4.2).

4.1 Int errupt Operation

If there are pending interrupts at the end of an
arithmetic or logic instr uc tion, the one with the
highest pri ority is passed. Passing an interrupt
means storing the arithmetic flags and the c urrent
PC in the stack and executing the associated
Interrupt routine, whose address i s located in three
bytes of the EPROM memory location between
address 2 and 17.

The Interrupt routine is performed as a normal
code, checking if a higher priority interrupt has to
be passed at the end of each instruction. An
Interrupt request with the higher priority stops the
lower priority Interrupt . The Prog ra m Counter and
the arithmetic flags are stored in the stac k.

With the RETI (Return from Interrupt) instruction
the arithmetic flags and Program Counter (PC) are
restored from the top of the stack. This stack was
already described in section RAM and STACK.

An Interrupt request c annot stop processing of the
fuzzy rule, but this is passed only after the end of a
fuzzy rule or at the end of a logic, or arithmetic
instruction.

NOTE: A fuzzy routine can only be interrupted
in the Main program. An interrupt request
cannot stop a Fuzzy function that is r un ning
inside another interrupt routine. In order to use
a Fuzzy function inside an interrupt routine, the
user MUST include the Fuzzy function between
an UDGI (M DGI) instruction and an UEGI
(MEGI) instruction (see the following
paragraphs), so that the interrupt request may
be disabled during the execution of the f uzzy
function.

Figure 4.1 Interrupt Flow

NORM AL

PROG RAM

FLOW

INTERRUPT

SERVICE
ROUTINE

INTERRUPT

RETI

INSTRUCTION

Figure 4.2 Interrupt Vectors mapping

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

INT_ADC

INT_PWM/ 0TIMER

_PWM/ 1TIMER

INT

INT_PWM/ 2TIMER

INT_EXT

INTERRUPT

VECTORS

Figure 4.3 Global Interrupt Request generation

Global Interrupt
Pending

Request

User Global
Interrupt Mask

4.2 Gl obal Interrupt Request Enabling

When an Interrupt occurs, it generates a Gl obal
Interrupt Pending (GIP), that can be masked by
software. After a GIP a Global Interrupt Request
(GIR) will be generate d and Interrupt service

28/84

Macro Global

Routine associated to the interrupt w ith higher
priority will start.

In order to avoid possible conflicts between
interrupt masking set in the main program, or
inside high level language compiler macros, the
GIP is h ung up through t he User Global Interrupt
Mask or the Macro Global Interrupt Mask (see
Figure 4.2).

UEGI/UDGI instruction switches on/off the User
Global Interrupt Mask, enabling/disabling the GIR
for the main program.

MEGI/MDGI instructions switch the Macro Global
Interrupt Mas k on/off, in order to e ns ure that the
macro will not be broken.

4.3 Int errupt Sources

ST52T410/ST52x420 manages interrupt signals
generated by the internal peripherals (PWM/
Timers and Analog to Digital Con ve rter) or coming
from the INT/PC0 pin. The External Interrupt is
active on the rising of INT/PC0 signal.

Each peripheral ca n be programmed in order to
generate the associated interrupt; further details
are described in the related chapter.

4.4 Int errupt Maskability

The inte rrupts can be masked by configuring the
REG_CONF 0 by means of LDCR, or LDCE,
instruction. The interrupt is enabled when the bit
associated to the mask interrupt is “1". Viceversa,
when the bit is ”0", the interrupt is ma sked and is
kept pendent.

For example:

LDRC 10,6 //load the constant 6 in the
RAM Register 10

LDCR 0, 10 // set the CONF_REG 0 with
the value stored in the RAM Register
10

ST52T410/ST52T420/E420

Table 4.1 Configuration Register 0

Description

Bit Name Value Description

0

0MSKE

1

0

1 MSKAD

1

0

2 MSKTM0

1

0

3 MSKTM1

1

0

4 MSKTM2

1

5 Not used -

External Interrupt

Masked

External Interrupt

Not Masked

A/D Converter (*)

Interrupt

Masked

A/D Converter (*)

Interrupt

Not Masked

PWM/TIMER 0

Interrupt

Masked

PWM/TIMER 0

Interrupt

Not Masked

PWM/TIMER 1

Interrupt

Masked

PWM/TIMER 1

Interrupt

Not Masked

PWM/TIMER 2

Interrupt

Masked

PWM/TIMER 2

Interrupt

Not Masked

theresult is CONF_REG0 =00000110 enabling the
interrupts deriving from the ADC (INT_ADC)
(ST52x420 only) and f rom the PWM/TIMER 0
(INT_PWM/TIMER0).

6 Not used

4 Not used -

(*) ST52x420 only
Reset Configuration ‘000000’

29/84

ST52T410/ST52T420/E420

Table 4.2 Interrupts Description

Name Description Priority

INT_ADC (*) ADC Int Programmable 00 yes 3-5

INT_PWM/

TIMER0

INT_PWM/

TIMER1

INT_PWM/

TIMER2

INT_EXT

(*) ST52x420 only

Figure 4.4 Interrupt Configuration Register 0

PWM/TIMER 0 Int Programmable 01 yes 6-8

PWM/TIMER 1 Int Programmable 10 yes 9-11

PWM/TIMER 2 Int Programmable 11 yes 12-14

External

Interrupt (INT)

Ext Highest - yes 15-17

Peripheral

Code

Maskable

REG_CONF 0

EPROM

Locations

70

MSKTM0 MSKAD MSKE

MSKTM1MSKTM2not used not usednot used

EXTERNAL INT.
A/D CONV. INT.
PWM/TIMER 0 INT.
PWM/TIMER 1 INT.
PWM/TIMER 2 INT.
NOT USED

30/84

Figure 4.5 Interrupt Configuration Register 1

REG_CONF 1

70

LOW LOW M EDLMEDL MEDH HIGHHIGHMEDH

ST52T410/ST52T420/E420

PRIORITY HIGH
PRIORITY MED. HIGH
PRIORITY MED. LOW
PRIORITY LOW

4.5 Int errupt Priority

Six priority levels are available: level 5 has the
lowest priority, level 0 ha s the highest priority.

Level 5 is associated to the Main P r ogram, leve ls 4
to 1 are programmable by means o f the priority
registers called R EG_CONF1 (see Figure 4.5 and
Table 4.3); whereas the higher level is related to
the external interrupt (INT_EXT).

PWM/Timers and ADC are identified by a two -bit
Peripheral Codes (see Table 4.2); in order to set

i

-th priority level the user must write the

the

i

peripheral label
i.e.

LDRC 10, 201 //(load the value
201=’11001001’ in the RAM Register 10)

LDCR 1, 10 // set the REG_CONF1=
‘11001001’

The following priority levels are defined:

■ Lev el 1: INT_PWM/TIMER0 (PWM/TIMER 0

Code: 01)

■ Lev el 2: INT_PWM/TIMER0 (PWM/TIMER 1

Code: 10)

in the related I N Tipriority level.

Table 4.3 Conf. Register 1

Bit Name Value Level

0, 1 INT1

2,3 INT2

4,5 INT3

■ Level 3: INT_ADC (ADC Code: 00) (ST52x420

only)

■ Level 4: INT_PWM/ TIMER0 (PWM/TIMER 2

Code: 11)

Peripheral

Code

Peripheral

Code

Peripheral

Code

High

Medium-High

Medium-Low

31/84

ST52T410/ST52T420/E420

Figure 4.6 E xample of a sequence of Interrupt requests

PRI2
PRIORITY
LEVEL

PRI0

PRI4

PRI1 PRI3

0

1

2

3

4

5

MAIN PROGRAM

PRI2

PRI0

Note: The Interrupt priority must b e fixed at the
beginning of the main program because at the
RESET REG_CONF1=’00000000’ it could
generate erroneous operations. During
program execution the interrupt priority can
only be modified with the following procedure:

PRI1

PRI2

PRI2

PRI3

PRI4

MAIN PROGRAM

When an interrupt occurs the CU executes a JUMP
instruction to the address loaded in the related
location of the InterruptVector.

When the execution returns to the ori ginal program
it imm ediately begins following the instruction that
was interrupted.

STEP 1:
MasktheinterruptsbymeansofaUDGI(or

MDGI) instruction
STEP 2:
Change the REG_CONF 1 values to modify the

interrupt priority
STEP 3:
Reset all the pending interrupt instructions by

means of RIN T instructions.
STEP 4:
UnmasktheinterruptsbymeansofaUEGI(or

MEGI) instruction

When a source provides an Interrupt request and
the reques t processing is also enabled, the CU
changes the n ormal sequential flow of a program
by transferring program control to a selected
service routine.

32/84

Table 4.4 RINT Instruction code

Peripheral Name Value

INT_ADC (*) 0

PWM/TIMER 0 1

PWM/TIMER 1 2

PWM/TIMER 2 3

INT_EXT 4

(*) ST52x420 only

4.6 Interrupts and Low power mode

All interrupts allow the processor toleave the WAIT
low power mode. Only the exte rnal Interrupt allows
the processor to leave the HALT low power mode.

ST52T410/ST52T420/E420

Note: The R INT command must be preceded
from a UDGI (or MDGI) command and followed
by a UEGI (or MEGI) command.

4.7 In terrupt RESET

An eventually pending interrupt can be reset with
the instruction RINT j, which resets the interrupt

j

-th wherejidentifies the peripherals as described

inthefollowingtable(seeTable4.4).
The assembler instruction:

RINT 2

Resets the PWM/Timer 1 interrupt.

WARNING: If an i nterrupt is reset, with the RINT
instruction within its own interrupt routine, the
priority level of the interrupt becomes the
lowest and the routine can be im mediately
interrupted by a lower priority interrupt
request.

33/84

ST52T410/ST52T420/E420

5 CLOCK, RESET & POWER SAVING MODE

5.1 System Clock

The ST52T410/ST52x420 Clock Gen erator
module generates the internal clock for the internal
Control Unit, ALU and on-chip peripherals and it is
designed to require a minimum number of external
components.

The ST52T410/ST52x420 oscillator circuit
generates an internal clock signal with the same
period and phase as that of the OSCin input pin.
The maximum frequency allowed is 20 Mhz.

The system clock may be ge nerated by using
either a quartz crystal, ceramic resonator or an
external clock.

The dif ferent methods of the clock generator are
illustrated in Figure 5.1.

When an external clock is used, it must be
connected on the OSCin pin, while OSCout can be
floating.

The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially

), oscillator load capacitance (CL), IC

R

s

parameters, env ironment temperature, suppl y
voltage.

Note: The crystal or ceramic leads and circuit
connections must be as s hort as possible. Typ ical
values for CL1, CL2 are 10pF for a 20 MHz crystal.

5.2 RESET

There are two Reset sources:

- RESET pi n (ex ternal source.)

- WATCHDOG (internal source)
When a Reset event happens, the user program

restarts from the beginning.
The Re set pin i s an input. An internal reset does

not affect this pin.
A Reset signal originated by external sources is

recognized instantaneously. The RESET pin may
be used to ensure V
the MCU can operate co rrectly before the user
program runs. In w ork ing mode Reset m us t be set
to ‘1’ (see Table 2.1).

5.3 P ower Saving Mode

There are two Power Saving modes: WAIT and
HALT mode. These conditions may be entered
using the WAI T or HALT instructions.

has risen to a point where

DD

Figure 5.1 Oscillator Connections

CRYSTAL CLOCK EXTERNAL CLOCK

ST52X420

OSCin OSCout

Cl1

10pF

Cl2

10pF

5.3.1 Wait Mode

Wait mode places the MCU in low power
consumption by stopping the CPU. All peripherals

ST52X420

OSCin

CLOCK

INPUT

OSCout

FLOATING

34/84

ST52T410/ST52T420/E420

and the watchdog remain active. During WAIT
mode, Interrupts are enabled. The MCU will
remain in Wait mode until an Interrupt or a RESET
occurs, whereupon the Program Counter jumps to
theinterruptserviceroutineor,ifaRESEToccurs,
at the beginning of the user program.

REMARK: In Wait mode the CPU clock does not
stop.

5.3.2 Halt Mode

Halt mode is MCU’s lowest power cons umption
mode, which is entered by execut ing the HALT
instruction. The internal oscillator is turned off,
causing all internal processing to stop, including
the operations of the on-chip peripherals.

Figure 5.2 Reset Block Diagra m

RESET INTERNAL

RESET

Halt mode cannot be used wh en the watchdog
is enabled.

If the HALT instruction is executed while the
watchdog system is enabl ed, it will be skipped
without modifying the normal CPU o perations .
TheICUcanexitHaltmodeafteranexternalinter-

rupt or reset. The oscillator is then t urned on and
stabilization time is provided before restarting
CPU operations. Stabilization time is 4096 CPU
clock cycles after t he interrupt and 1.000.000 after
the Reset.
After the start up delay, the CPU restarts opera­tions by serving th e external interrupt routine.
Reset makes the ICU exit from HALT mode and
restart, after the delay, from the beginning of t he
user program after the delay.

Warning: if the External Interrupt is disabled, t he
ICU exits from the Halt m ode and jumps to the

lower priority interrupt routine.

Figure 5.4 WAIT Flow Chart

WATCHDOG RESET

Figure 5.3 S imple Reset Ci rcuit

Vcc

100 F 10k

2.2k 2.2k 1 F

RESET

35/84

ST52T410/ST52T420/E420

Figure 5.5 HALT Flow Chart

HALT INSTRUCTION

YES

HALT INSTRUCTION

SKIPPED

OSCILLATOR OFF
PERIPHERALS CLOCK OFF
CPU CLOCK OFF

NO

RESET

YES

OSCILLATOR ON
PERIPHERALS CLOCK ON
CPU CLOCK ON

1000000 CPU CLOCK

CYCLES DELAY

NO

WATCHDOG

ENABLED

NO

EXTERNAL

INTERRUPT

YES

OSCILLATOR ON
PERIPHERALS CLOCK ON
CPU CLOCK ON

4096 CPU CLOCK

CYCLES DELAY

36/84

RESET CPU

AND RESTART

USERPROGRAM

NO

RESTART PROGRAM

SERVICINGTHE

LOWER PRIORITY

INTERRUPT ROUTINE

EXTERNAL

INTERRUPT

ENABLED

YES

RESTART PROGRAM

SERVICINGTHE

EXTERNAL

INTERRUPT ROUTINE

ST52T410/T420/E420

6 FUZZY COMPUTATION (DP)

The ST52T410/ST52x420 Decision Proc es sor
(DP) main features are:

■ Up to 8 Inputs with 8-bit resolution;

■ 1 Kbyte of Program/Data Memory available to

store more than 300 to Membership Functions
(Mbfs) for each Input;

■ Up to 128 Ou tpu ts with 8-bit resolution;

■ Possibility of processing fuzzy rules w ith an

UNLIMITED number of antecedents;

■ UNLIMITED number of Rules and Fuzzy Blocks.

The limits on the num ber of Fuzzy Rules and
Fuzzy program blocks are only related to the
Progra m/Data Memory size.

6.1 Fuzzy Inference

The block diagram shown in Figure 6.1 describes
the different steps performed during a Fuzzy
algorithm. The ST52T410/ST52x420 Core allows
for the implement ation of a Mamdani type fuzzy
inference with crisp cons equents. Inputs for fuzzy
inference are stored in 8 dedicated Fuzzy input
registers. The LDFR instruction is used to set the
Input Fuzzy registers with values stored in the
Register File. The resu lt of a Fuzzy inference is
stored directly in a location of the Register File.

6.2 Fuzzyficati on Phase

In this phase the intersection (alpha weight)
between the input values and the related Mbfs
(Figure 6.2) is performed.

Eight Fuzzy Input registers are available for Fuzzy
inferences.

Figure 6.2 Alpha WeightCalcula tion

j-th Mbf

i-th INPUTVARIABLE

α

1

ij

After loading the input values by using the LDFR
assembler instruction, the user can start the fuzzy
inference by using the FUZZY assembler
instruction. During fuzzyfication: input data is
transformed in the activation level (alpha weight) of
the Mbf’s.

6.3 I nference Phase

The Inference Phase manages the alpha weights
obtained during the fuzzyfication phase to com pute
the truth value (ω) for each rule.

This is a calculation of the maximum (for the OR
operator) and/or minimum (for the AND operator)
performed on alpha values according to the logical
connectives of Fuzzy Rules.

Several conditions may be linked t ogether by
linguistic connectives AND/OR, NOT operators
and brackets.

The truth value ω and the related output singleton
are used by the Defuzzyfication phase, in order
to complete t he inference calculation.

Figure 6.1 Fuzzy Inference

FUZZYFICATION

Input Values

11

1m

INFERENCE

n1

nm

PHASE

1

2

DEFUZZYFICATION

Nrules-1

Nrules

OutputValues

37/84

ST52T410/T420/E420

.

Figure 6.3 Fuzzyfication

IF

INPUT 1

1

α

IF

INPUT 1

1

α

IS X1 OR

X1

IS X1 AND

X1

Input 1

Input 1

INPUT 2

α2

OR = Max

INPUT 2

α2

IS X2 THEN .......

X2

Input 2

IS X2 THEN ......

X2

Input 2

6.4 Defuzzyfication

In this phase the output crisp va lues are
determined by implementing the consequent part
of the rules.

Each consequent Si nglet on X
weight values ω

, calculated by the Decision

i

is multiplied by its

i

processor, in order to compute the upper part of
the Defuzzyfication formula.

Each output value is obtained from the consequent
crisp values (X

) by carrying out the following

i

Defuzzyfication formula:

6.5 I nput Membershi p Function

The Decision Processor allows th e management of
triangular Mbfs. In order to define an Mbf, three
different parameters must be stored on the
Program/Data Memory (see Figure 6.4):

■ the vertex of the Mbf: V;

■ the length of the left semi-base: LVD;

■ the length of the right s emi-base: RVD;

In order to reduce the size of the memory area and
the computational effort the vertical range of the
vertex is fixed b etwe en 0 and 15 (4 bits)

By using the previous memorization method
different kinds of triangular Membership Functions
maybestored.Figure6.5showssomeexamples
of val id Mbfs that can be defi ned in ST52T410/
ST52x420.

Each Mbf is t hen def ined st oring 3 bytes in the first
Kbyte of the Program/Data M emory.

The Mbf is stored by using the following instruction:

n_mbf lvd v rvd

MBF

where:

n_mbf
lvd,v

is a tag number that identifies the Mbf

,and

rvd

aretheparametersthatdescribethe

Mbf’s shape as described above.

Figure 6.4 Mbfs Parameters

15

Input Mbf

N

Xijω

Y

=

i

∑

---------------------

j

∑

ij

N

ω

ij

j

where:
i = identifies the current output variable
N = number of the acti v e rules on the current

output

= weight of the j-th singleton

ω

ij

= abscissa of the j-th singleton

X

ij

The Decision Processor outputs are stored in the
RAM location i-th specified in the assem bler
instruction OUT i.

38/84

15

0

w

0

V

LVD RVD

Output Singleton

X

Input Variable

Output Variable

ST52T410/T420/E420

X

Figure 6.5 Example of val id Mbfs

6.6 Output Singleton

The Decision Processor uses a particular kind of
membership function called Singl eton for its output
variables. A Singleton doesn’t have a shape, like a
traditional Mbf, and is characterized by a single
point identified by the couple (X, w), where w is
calculated by the Inference Unit as des c r ibed
earlier. Often, a Singleton is s im ply identified wi th
its Crisp Value X.

Figure 6.6 Output Membership Functions

1

ω

ij

ω

i0

ω

in

0

X

j-th Singleton

i0

ij

X

i-th OUTPUT

in

6.7 Fuzzy Rules

Rules can have the following structures:

if A op B op C...........then Z

if (A op B) op (C op D op E...) ...........then Z

op

where

is one of the possible linguistic operators

(AND/OR)
In the first case the rule operators are managed

sequentially; in the second one, the priority of the
operator is fixed by the brackets .

Each rule iscodified by using an instruction set , the
inference t im e for a rule with 4 ant ec edents and 1
consequent is about 3 microseconds at 20 MHz.

The Ass embler Instructio n Set us ed to manage the
Fuzzy operations is reported in the table below.

Table 6.1 Fuzzy Instructions Set

Instruction Description

MBF

n_mbf Ivd v rvd

LDP

nm

nm

LDN

FZAND Implements the Fuzzy operation AND between the last two values stored in internal registers
FZOR Implements the Fuzzy operation OR between the last two values stored in internal registers

LDK Stores the result of the last Fuzzy operation executed in internal registers

SKM

LDM Copies the value of register M in the data stack

crisp

CON

OUT

n_out

FUZZY Starts the Fuzzy algorithm

Stores the Mbf

n_mbf

with the shape identified by the parameters

Ivd,v

and

rvd

Fixes the alpha value of the inputnwith the Mbfmand stores it in internal registers
Calculates the complementary alpha value of the inputnwith the Mbfm. and stores the result

in internal registers

Loads the result of the last performed Fuzzy operation (stored in the temporary register K) in
the temporary buffer M.

Multiplies the

Performs Defuzzyfication and stores the currently Fuzzy output in the RAM

crisp

value with the last ω weight

n_out

location

39/84

ST52T410/T420/E420

Example 1:

IF Input1IS NOT Mbf1AND Input4is Mbf12OR Input3IS Mbf8THEN Crisp

1

is codified by the foll owing instructions:

LDN 1 1

LDP 4 12

calculates the NOT α v alue of Input

fixes the α value of Input

with Mbf12and stores the result in internal registers

4

with Mbf1and stores the result in internal registers

1

FZAND implements the operation AND between the results obtained with the previous instructions
LDK stores the result of the previous operation in internal DPU registers

LDP 3 8

fixes the α value of Input

with Mbf8and stores the res ult in internal regist ers

3

FZOR i mplements the operation OR between the results obtained with t he previous instructions
CON

crisp

multiplies the result of the last Ω operation with the crisp value

1

crisp

1

Example 2, the priority of the operator is fixed b y the brackets:

IF (Input3IS Mbf1AND Input4IS NOT Mbf15)OR(Input1IS Mbf6OR Input6IS NOT Mbf14)THENCrisp

2

LDP 3 1

LDN 4 15

fixes the α value of Input
calculates the NOT α value of Input

with Mbf1and stores the result in internal registers

3

with Mbf15and stores the result in internal registers

4

FZAND implements the operation AND between the results obtained with the previous instructions
SKM stores the result of the previous ope ra tion in register M

LDP 1 6

LDN 2 14

fixes the α value of Input

calculates the NOT α value of Input

with Mbf6and stores the result in internal registers

1

with Mbf14and stores the result in internal registers

6

FZOR i mplements the operation OR between the results obtained with t he previous instructions
LDK stores the result of the previous operation in internal DPU registers
LDM copies the value of the register M in internal DPU registers
FZOR im plements the operation OR between the last two values stored in DPU registers

crisp

CON

At the end of the fuzzy rule, by using the instruct ion OUT

multiplies the result of the last Ω operation with the crisp value

2

RAM_reg

, a byte is written. Afterwards, the

crisp

2

control of the algorithm returns to the CU.

40/84

ST52T410/ST52T420/E420

7 I/O PORTS

7.1 Introduction

ST52T410/ST52x 420 devices feature flexible
individually programmable multi-functional input/
output lines. Refer to the following figure for
specific pin allocations.

19 I/O li nes , grouped in 3 different ports are
available on t he ST52T410/ST52x420:

PORT A = 7 or 8-bit ports (PA0 - PA7 pins)
PORT B = 7 or 8-bi t ports (PB0 - PB7 pins)
PORT C = 4-bit port (PC0 - PC3 pins)

PIN 18 can be configured to belong to port A or to
port B.

These I/O lines can be programmed to provide
digital input/output and analog input, or to c onnect
input/output signals to the on-chip peripherals as
alternate pin func tio ns .

Input buffers are TTL compatible with Schmitt
trigger in port A and C while port B is CMOS
compatible without Schmitt trigger.

The output buf fer can supply up to 8 mA.
The port cannot be config ured to be used

contemporaneously as input and output.

Figure 7.1 Ports A & C Functional Blocks

Each port is configured by using two configuration
registers. The first is used to determine if a pin is
an input or output, while the second defines the
Alternate functions.

7.2 Input Mode

The input configuration is selected by setting the
corresponding configuration register bit to “1”
(REG_CONF 4, 13 and 15) (see paragraph I/O
Port Configuration Registers). The ports are
configured by using the configuration r egisters
illustrated in the following table.

.

Table 7.1 I/O Port Configuration Registers.

PORT A PORT B PORT C

Reg_Conf 4 Reg_Conf 13 Reg_Conf 15

Digital input data is automatically stored in the
Input Registers, but it cannot be read directly. In
order to read a single bit of the IR its value must be
copied i n a RAM location. Digital data is stored in a
RAM location by using the assembler instruction:

LDRI RAM_Reg Input_i

TO INPUT REGISTER
and PERIPHERALS

FROM PERIPHERAL

FROMOUTPUTREGISTER

FROMCONFIGURATIONREGISTER

FROMCONFIGURATIONREGISTER

TTL

PORT A PIN
or PORT C PIN

41/84

ST52T410/ST52T420/E420

Figure 7.2 Port B Functional Blocks

FROM CONFIGURATION REGISTER

CMOS

TO INPUT REGISTER

TO A/D CONVERTER

FROM OUTPUT REGISTERS

FROM CONFIGURATION REGISTER

Table 7.2 Input Register and I/O Ports

PORT A PORT B PORT C

IR 9 IR 10 IR 11

7.3 Output Mode

The output configuration is selected by set ting the
corresponding configuration register bit to “0”
(REG_CONF 4, 13 and 15) (see paragraph I/O
Port Configuration Registers).

Digital data is transferred to the related I/O Port by
means of the Output register via the assemble r
instructions LDPE or LDPR.

Table 7.3 Output Register and I/O Ports

PORT A PORT B PORT C

OR 0 OR 1 OR 2

PORT B PIN

7.4 Alternate Functions

Several ST52T410/ST52x420 p ins are
configurable to be used with different functions
(see Table 1.1).

When an on-chip peripheral is configured to use a
pin, the correct I/O mode of the related pin must be
selected.

For example: if pin 20 (PA5/T0CLK) has to be used
as an external PWM/Timer0 c lock, the Reg_Conf
4(5) bit must be set to ‘1’.

When the signal is an on-chip peripheral input the
related I/O pin has to be configured in Inpu t Mode.

When a pin is used as an A/D Converter input the
related I/O pin is au tomat ically set in tristate. The
analog multiplexer (controlled by the A/D
configuration Register) switches the analog
voltage present on the s elected pi n to the common
analog rail, which is connected to the ADC input
(ST52x420 only).

It is recommended that the voltage leve l not be
changed or t hat any port pins not be loaded while
conversion is running. Furthermore, it is
recommended that clocking pins not be located
close to a selected analog pin (ST52x420 only).

42/84

7.5 I/O Port Configuration R egisters

The I/O mode for each bi t of the three ports is
selected by using the Configuration Registers 4,

13 and 15 (See Table 7.1) The structure of these
registers is illustrated in the following tables.

Each bit of the c onfiguration registers d etermines
the I/O mode of the related port pin.

Table 7.4 Ports A REG_CONF 4

ST52T410/ST52T420/E420

Table 7.5 Ports B REG_CONF 13

Bit Name Value Description

0

0D0

1

Set the pin PB0/Ain0

in Output Mode

Set the pin PB0/Ain0

in Input Mode

Bit Name Value Description

0

0D0

1

0

1D1

1

0

2D2

1

0

3D3

1

0

4D4

1

0

5D5

1

0

6D6

1

Set the pin PA0/T0RES

in Output Mode

Set the pin PA0/T0RES

in Input Mode

Set the pin PA1/T0OUT

in Output Mode

Set the pin PA1/T0OUT

in Input Mode

Set the pin PA2/T1OUT

in Output Mode

Set the pin PA2/T1OUT

in Input Mode

Set the pin PA3/T2OUT

in Output Mode

Set the pin PA3/T2OUT

in Input Mode

Set the pinPA4/T0STRT

in Output Mode

Set the pinPA4/T0STRT

in Input Mode

Set the pin PA5/T0CLK

in Output Mode

Set the pin PA5/T0CLK

in Input Mode

Set the pin PA6 in

Output Mode

Set the pin PA6 in Input

Mode

0

1D1

1

0

2D2

1

0

3D3

1

0

4D4

1

0

5D5

1

0

6D6

1

0

7D7

1

Reset Configuration ‘11111111’

Set the pin PB1/Ain1

in Output Mode

Set the pin PB1/Ain1

in Input Mode

Set the pin PB2/Ain2

in Output Mode

Set the pin PB2/Ain2

in Input Mode

Set the pin PB3/Ain3

in Output Mode

Set the pin PB3/Ain3

in Input Mode

Set the pin PB4/Ain4

in Output Mode

Set the pin PB4/Ain4

in Input Mode

Set the pin PB5/Ain5

in Output Mode

Set the pin PB5/Ain5

in Input Mode

Set the pin PB6/Ain6

in Output Mode

Set the pin PB6/Ain6

in Input Mode

Set the pin PB7/PA7/
Ain7 in Output Mode

Set the pin PB7/PA7/

Ain7 in Input Mode

0

7D7

1

Reset Configuration ‘11111111’

Set the pin PB7/PA7/

Ain7 in Output Mode

Set the pin PB7/PA7/

Ain7 in Input Mode

43/84

ST52T410/ST52T420/E420

Table 7.6 Port C REG_CONF 15

Bit Name Value Description

0

0D0

1

Set the pin INT/PC0 in

Output Mode

Set the pin INT/PC0 in

Input Mode

Analog Input Option. The PB0-PB7 pins can be
configured to be analog inputs according to the
codes programm ed in the configuration register
REG_CONF 14 (See Table 7.7) (ST52x420 only).
These analog input s are connected to th e on-chip
8-bit Analog to Digital Converter.

Table 7.7 Analog Inputs (REG_CONF 14)

Bit Name Value Description

1D1

2D2

3D3

4D4

5D5

0

1

0

1

0

1

Set the pin T0OUT/

PC1 in Output Mode

Set the pin T0OUT/
PC1 in Input Mode

Set the pin T1OUT/

PC2 in Output Mode

Set the pin T1OUT/

PC2 in Input Mode

Set the pin T2OUT/

PC3 in Output Mode

Set the pin T2OUT/

PC3 in Input Mode

Not used

Not used

0 pin PB0/Ain0 Digital I/O

0D0

1 pin PB0/Ain0 Analog
0 pin PB1/Ain1 Digital I/O

1D1

1 pin PB1/Ain1 Analog
0 pin PB2/Ain2 Digital I/O

2D2

1 pin PB2/Ain2 Analog

0 pin PB3/Ain3 Digital I/O

3D3

1 pin PB3/Ain3 Analog

0 pin PB4/Ain4 Digital I/O

4D4

1 pin PB4/Ain4 Analog

0 pin PB5/Ain5 Digital I/O

5D5

1 pin PB5/Ain5 Analog

0 pin PB6/Ain6 Digital I/O

6D6

1 pin PB6/Ain6 Analog

0 pin PB7/Ain7 Digital I/O

7D7

1 pin PB7/Ain7 Analog

6D6

7D7

Reset Configuration

44/84

‘11111111’

Not used

Not used

Reset Configuration ‘11111111’

PWM/Timers Alternate Functions

The pins of Port A and C can be configured to be I/
O of the three PWM/Timers available on the
ST52T410/ST52x420. The configuration of these
pins is performed by using the Conf igurat ion
Registers REG_CONF 12 and REG_CONF 16 if
the related pin has to be output. When the related
pin has to be used as an input peripheral the
configuration is performed by the relative
peripheral configuration registers (See PWM/
Timer Session).

Warning:

in order to use PC1, PC2 and PC3
pins as standard I/O pins, the PWM/Timers
must be configured in Timer mode

ST52T410/ST52T420/E420

Table 7.9 PWM/Timers REG_CONF 12

Bit Name Value Description

Pin PA1/T0OUT is

1

0PA1

0

configured as

PWM/Timer 0

complementary output

Pin PA1/T0OUT is

configured as

Port A Digital I/O

Table 7.8 PWM/Timers REG_CONF 16

Bit Name Value Description

1

0 PC1

0

1

1 PC2

0

1

2 PC3

0

Pin T0OUT/PC1 is

configured as Port C

Digital I/O

Pin T0OUT/PC1 is

configured as PWM/

Timer 0 output T0OUT

PinT1OUT/PC2 is

configured as Port C

Digital I/O

Pin T1OUT/PC2 is

configured as PWM/

Timer 1 output T1OUT

Pin T2OUT/PC3 is

configured as Port C

Digital I/O

Pin T2OUT/PC3 is

configured as PWM/

Timer 2 output T2OUT

1PA2

2PA3

3PASZ

Pin PA2/T1OUT is

1

0

1

0

1 PORT A bits = 8

0 PORT A bits = 7

configured as

PWM/Timer 1

complementary output

Pin PA2/T1OUT is

configured as

Port A Digital I/O

Pin PA3/T2OUT is

configured as

PWM/Timer 2

complementary output

Pin PA3/T2OUT is

configured as

Port A Digital I/O

3-7 NC X Not Used

Reset Configuration ‘00000000

4-7 NC x Not Used

Reset Configuration ‘0000’

45/84

ST52T410/ST52T420/E420

Figure 7.3 Configuration Register 12

REG_CONF 12

DIGITAL PORT

D7 D6 D5 D4 D3 D2 D1 D0

PA1T: Pin PA1/T0OUT setting

PA2T: Pin PA2/T1OUT setting
PA3T:Pin PA3/T2OUT setting
PA78: PORT A size

not used

Figure 7.4 Configuration Register 16

46/84

ST52T410/ST52T420/E420

8 A/D CONVERTER (ST52X420 ONLY)

8.1 Introduction

The A/D Converter of ST52x420 is an 8-bit analog
to digital converter with up to 8 analog inputs
offering 8 bit resolution with a total accuracy of 1
LSB and a typical conve rsi on time of 8.2 µswitha
20 MHz clock. This pe riod also includes the 5.1 µs
of the integral Sample and Hold circuitry, which
minimizes the need for external components and
allows quick sampling of the signal for a minimum
warping effect and Integral conversion error.

Conversion is p erformed in 82 A/D clock
pulses.

The A/D clock is derived from the clock master.
The maximum A/D clock frequ enc y has to be 10
MHz. When the master clock is higher than 10
MHz it has to be divided by 2 using the SCK bit of
the A/D configuration register REG_CONF 3 (See
Table 8.1).

The A/D peripheral converts the in put voltage with
a process of successive approximations using a
fixed clock frequency derived from the os cillator.

The conversion range is between the analog

and VDDreferences.

V

SS

The converter uses a fully differential analog input
configuration for the best noise immunity and

Figure 8.1 A/D Converter Structure

precision performance, along with one separate
supply (V

), allowing the best supply noise

DDA

rejection.
Up to 8 multiplexed Analog I nput s are available. A

group of signals can be converted sequentially by
simply programming the starting address of the
last analog channel to be c onv erted.

Single or continuous conversion mode are
available.

The result of the conversion is stored in an 8-bit
Input Register (from IR 1 to IR 8).

The A/D conv erter is controlled via the
Configuration Register RE G_CONF 3.

A Power-Down programmable bit allows the A/D
converter to be set to a minimum consumption idle
status.

The ST52x4 20 Interrupt Unit provides one
maskable channel for the End of Conversion
(EOC).

8.2 Operational Description

The conversion is monotonic, meaning that the
result never decreases if the analog input doesn’t
and never increas es if the analog input doesn’t.

If inpu t voltage is greater than or equal to V

dda

(Voltage Ref erenc e high) then the result is equal to
FFh (full scale) without an overflow indicat ion.

INPUT REGISTER

1 ÷ 8

A/D CHANNEL 0
A/D CHANNEL 1
A/D CHANNEL 2
A/D CHANNEL 3
A/D CHANNEL 4
A/D CHANNEL 5
A/D CHANNEL 6
A/D CHANNEL 7

CONFIGURATION REGISTER 3

CONTROL

LOGIC

SAMPLE

&

HOLD

SUCCESSIVE APPROXMATION

A/D CONVERTER

CH2CH1CH0SCKSEQPOWLPSTR

ANALOG

MUX

PB0/AIN0
PB1/AIN1
PB2/AIN2
PB3/AIN3
PB4/AIN4
PB5/AIN5
PB6/AIN6
PB7/PA7/AIN7

47/84

ST52T410/ST52T420/E420

If input voltage i s less than VSS(voltage reference
low) then the result is equal to 00h.

The A/D converter is linear and the digital result of
the conversion is provided by the following
formula:

255inputVoltage

Digitalresult

Where Reference Vol tag e is V
The accuracy of the conversion is described in the

Electrical Characteristics Section.
The A/D converter is not affected by the WAIT

mode.
When the MCU enters HA LT mode with A/D

converter enabled, the converter is disabled until
HALT mode is terminated and the start-up delay
has elapsed. A stabilization period is also required
before accurate conversions c an be performed.

Figure 8.2 Conf. Register (REG_CONF 3)

----------------------------------------------- -

=

referenceVoltage

dda-Vss

.

8.2.1 Operating M odes.

Four main operating modes can be selecte d by
setting the values of the LP and SEQ bit in the A/D
configuration Register.

One Channel Single Mode

Inthismode (SEQ = ‘0’’, LP = ‘0’) the A/D provides
an EOC signal after the end of channel i-th
conversion; then the A/D waits for a new start
event. Channel i-th is identified by the bit CH0,
CH1, CH2.

i.e CH(2:0) = ‘011’ means conversion of channel 3
then stop.

Multiple Channels Single Mode

In this m ode (SEQ = ‘1’, LP = ‘0’) the A/D provides
an EOC s ignal after the end of the channels
sequence conv ers ion identified by the bit CH0,
CH1, CH2; then the A/D waits fora new startevent.
i.e. CH(2:0) = ‘011’ means conversion of channels

0,1,2 and 3 then stop.

REG_CONF 3

D7 D0

CH2 CH1 CH0 SCK SEQPOW LP STR

START/STOP
CONVERSION MODE SEL.
ON/OFF A/D
CONVERSION MODE SEL.
CLOCK SELECTOR
CHANNELS SEL.

48/84

ST52T410/ST52T420/E420

One Channel Continuous Mode

In this mode (SEQ = ‘0’’, LP = ‘1’) a continuous
conversion flow is entered by a starting event on
the channel selected by the CH0, CH1, CH2 bits

For example: CH(2:0) = ‘011’ m eans continuous
conversion of channel 3. At the end of each
conversion the relative I R is updated with t he last
conversion result, while the former val ue is lost.

To stop the conversion STR has to b e set to ‘0’.

Multiple Channels Continuous Mode

In this mode (SEQ = ‘1’’, LP = ‘1’) a continuous
conversion flow is entered by a starting event on
the channels selected by t he CH0, CH1, CH2 bits.

i.e CH(2:0) = ‘011’ means continuous conversion
of channel 0,1,2 and 3.

At the end of each conversion the relative IRs are
updated with the last conversion results, while the
former values are lo st.

To stop the conversion STR has to b e set to ‘0’.

8.2.2 Power Down Mode.

Before enabling any A/D operation mo de, set the
POW bit of the A/D configuration register to ‘1’ at
least 60 µs before the first conversion starts to
enable the biasing circuit inside the analog section
of t he converter. Clearing the P OW bit (POW = ‘0’)
is useful when the A/D is not used, reducing the
total chip power consumption.This state is also the
reset configuration and it is forced by hardware
whenthecoreisinHALTstate(afteraHALT
instruction execution).

8.3 A/D Registers Description

The result of the conversions of the 8 available
channels are loaded in the 8 Input Register from
decimal address 1 to decimal address 8. (IR (1:8)
see T able 2.2)). Every IR(1:8) is reloaded with a
new value at the end of the conversion of the
correspondent analog input.

By using the assembler instruction:
LDRI RAM_Reg. IR_i
the value stored in the i-th IR is transferred on the

RAM location RAM_Reg.
The A/D configuration regist er is the R EG_CONF

3. Figure 7.2 illustrates the structure of this
register, whi ch manages the A/D logic operation.
The A/D c onfiguration register (REG_CONF 3) is
programmable as following:

b7-b5 = CH2, CH1, CH0: Last Conversion
Address. These 3 bits define the last analog input.
The first analog input is converted, then the
address is incremented for the succe ssive
conversion until the channel identified by CH0­CH2 is converted. The (CH2, CH1, CH0) bits
define the group of channels to be scanned. When

setting CH2=0 CH1=0 CH0=0 only channel 0 is
converted.

b4 = SCK: Master clock divider. ST52x420 can
work with a clock frequency up to 20 MHz. The
SCK must be set to ‘1’ when t he ST52 x4 20 clock is
higher then 10 MHz. It is useful to set SCK = ‘1’
even when the clock master i s lower than 10 MHz
and a high accuracy is requ ired.

b3 = SEQ: Multiple/Single channel. When SEQ is
set to ‘0’ the channel identified by CH(2:0) is
converted. If SEQ is set to ‘1’ the group of channels
identified by CH(2:0) are converted.

b2= POW: Power Up/ Power Down. A logical ‘1’
enables the A /D logic and analog circuitry.

Logical level ‘0’ disables all power consuming
logic, allowing a low power idle status.

b1 = LP: Continuous/Single. When this bit is set to
‘1’ (continuous mode), the first conversion
sequences are started by the STR bit then a
continuous conversion flow is processed.

When LP=’0’ (single mode) only one sequenc e of
conversions is started when STR is s et.

b0 = STR: Start/Stop. A logical level ‘1’ enables
starting a conversion sequence; a logical l ev el ‘0’
stops the conve rsio n. When the A/D is run ning in
the Single Modes (LP=’0’), this bit is hardware
reset at the end of a convers ion sequence.

Table 8.1 A/D Conf. Register (Reg_Conf 3)

Bit Name Value Description

0 STR

1LP

2POW

3 SEQ

4 SCK

5

6

CH(2:0)

7

0 Stop Conversion
1 Start Conversion
0 Single Conversion
1 Continuous
0 A/D OFF
1 A/D ON
0 Single Channel Conv.
1 Multiple Channels Conv
0 Clock not Divided

1 Clock Divided
000 Channel 0
001 Channel 1
010 Channel 2

011 Channel 3
100 Channel 4
101 Channel 5

110 Channel 6

111 Channel 7

49/84

ST52T410/ST52T420/E420

9 WATCHDOG T IMER

9.1 Operational Descriptio n

The Watchdog Timer (WDT) is used to detect the
occurrence of a sof tware fault, usually generated
by external interference or by unforeseen logical
conditions, which cause the application program to
abandon its normal sequence. The WDT circuit
generates an MCU reset on expiry of a
programmed time period, unless the program
refreshes the WDT before the end of t he
programmed time delay.

16 different delays can be selected by using the
WDT configurat ion register.

After the end of the delay programmed by the
configuration register if the WDT is activated (by
using the assembler instruction WDTSFR), it starts
a reset cycle pulling the reset pin low.

Once the WDT has been activated the application
program has to refresh this peripheral (by the
WDTSFR instruction) at regular intervals during
normal operation in order topreventan MCU reset.

In order to stop the WDT during user program
executiontheinstruction WDTSLP has to be used.

Figure 9.1 Watchdog Block Diagram

The working fr equency of the WDT (PRE S CLK in
the Figure 9.1) is equal to the clock master. The
clock master is divided by 500, obtaining the WDT
CLK signal, which is used to fix the timeout of t he
WDT.

Table 9.1 Watchdog Timing range (CLK=5

MHz)

WDT timeout period (ms)

min 0.1

max 937.5

According to the WDT configuration register
values, a WDT delay may be defined b etween 0.1
ms and 937.5 mS whe n the clock master is 5 MHz.
By changing the clock master frequen cy the
timeout delay can be calculated according t o the
configuration register values REG_CO NF 2, as
described in the following section.

Warning: chan ging the REG_CONF 2 value when
the WDT is a ctive, a W D T reset is generated and
the CPU is restarted. To avoid this side effect, use
the

WDTSLP

instruction before changing the

REG_CONF2.

WDTR FR

RESET

PRES CLK = CLK MASTER

50/84

WDTSLP

REG_CONF 2

D2D3

PRESCALER

D0D1

WTD CLK

WDT

RESET

GENERATOR

RESET

ST52T410/ST52T420/E420

9.2 Register Description

The WDT t im eout is defined by setting the value of
the REG_CONF 2. The first 4 bits of this register
are used , obtaining 16 different delays as
illustrated in Table 9.2. In Table 9.2 timeout is
expressed by using the number of WDT CLK. The
WDT C LK is derived from the c lock ma ster by a
division factor of 500. Tim eout is obtained by
multiplying the WDT CLK pulse len gth for the
number of p ulses defined by the configuration
register RE G_CONF 2. Table 9.4 illustrates the
pulse lengths for ty pical values of the clock master.

Table 9.3 illustrates the timeout WDT values when
the Master Clock is 5 MHz.

Table9.2 WDTREG_CONF2

Bit Name Value Timeout Values (WDT)

0000 1

0

1

D(3:0)

2

3

4-7 NC

0001 625
0010 1250
0011 1875
0100 2500
0101 3125
0110 3750
0111 4375
1000 5000
1001 5625
1010 6250
1011 6875
1100 7500
1101 8125
1110 8750

1111 9375

x Not Used

Table 9.3 Timeout Values with CLK = 5 MHz

Bit Name Value Timeout Values (ms)

0000 0.1

0

1

D (3:0)

2

3

4-7 NC

Reset Configuration ‘0000’

0001 62.5
0010 125
0011 187.5
0100 250
0101 312.5
0110 375

0111 437.5
1000 500
1001 562.5
1010 625
1011 687.5
1100 750
1101 812.5

1110 875

1111 937.5

x Not Used

Table 9.4 Typical WDT CLK Pulse Length

MASTER CLK

(MHz)

4 8 0.125
5 10 0.1

8 16 0.0625
10 20 0.05
20 40 0.025

WDT CLK

(KHz)

WDT CLK

PULSE

LENGTH (ms)

Reset Configuration ‘0000’

51/84

ST52T410/ST52T420/E420

10 PWM/TIMER

ST52T410/ST52x420 offers three on-chip PWM/
Timer peripherals:TIMER0, TIMER1 and TIMER2.

The ST52T410/ST52x420 timers have the same
internal structure. The timer cons ists of an 8-bit
counter with a 16-bit programmable prescaler,
giving a maximum count of 2

24

(see Figure 10.1).

Figure 10.1 Timer Peripheral Block Diagram

16-BIT PRESCALER

CLKM

BIT 0 BIT 1 BIT 2 BIT3 BIT 4

17 - 1 MUL TIPLEXER

8-BIT COUNTER

Note: In order to use T0RST, T0STR, T0CLK
external signals the related pins must be
configured in Input Mode by setting
REG_CONF4 and REG_CONF7 registers (see
Table 7.4 and Table 10.3)

For each timer, the content of the 8-bit counter is
incremented on the Rising E dge of the 16-bit
prescaler outpu t (PRESCOUT) and it can be read
at any instant of the counting phase, saved in a
location of RAM memory. The PWM/Timer x
Counter v alue can be read from the Input Register

BIT5 BIT 14 BIT 15

PRESCx

TMRCLK

TxRE S

BIT 1 BIT 2 BIT 6BIT 4 BIT5 BIT 7

BIT3BIT 0

Next, the generic timer is called T imer x, where x
canbe0,1or2.

Each timer has two different working modes, which
can be selected by setting the correspondent
TxMODE bits of REG_CONF5, REG_CONF8 and
REG_CONF10 registers: T imer Mode and PWM
(Pulse Width Modulation) Mode.

All Timers have Autoreload Functions in PWM
Mode.

Each timer output is available, with its
complementary signal on ext ernal pins b y setting
PAx and PCx bits of REG_CONF12 and
REG_CONF16 (see Table 10.8 and Table 10.9).

Note: In order to enable timer output (TxOUT or
TxOUT

) the related pin must be configured in
Output Mode by setting REG_CONF4 and
REG_CONF15 registers (see Table 7.4 and
Table 7.6)

In particular, TIMER0 can also use ext ernal
START/STOP signals (Input capture and Output
compare), external RESET signal and external
CLOCK: PA4/T0STRT, PA0/T0RES and PA5/
T0CLK pins.

TxSTRT

PWM_x_COUNT (Input Registers 12, 14 or 16.
See Table 2.2).

The PWM/Timer x Status can be read from the
Input Register PWM_x_STATUS (Input Registers
13, 15 or 17. See Table 2.2 and Tabl e 10.10).

10.1 TimerMode

TimerModeisselectedbyfixingtheTxMODEbit
of REG_CONF5, RE G_CONF8 and
REG_CONF10 equal to 0 (see Table 10.1, Table

10.4 and Table 10.6).
Each TIMERx requires three signals: T im er Clock

(TMRCLKx), Timer Reset(TxRES) and Timer Start
(TxSTRT) (see Figure 10.1). E ac h of these signals
can be generated internally, or, only for Timer 0,
externally by s et ting T0RST, T0STR , T0CLK bits of
REG_CONF7 register.

TMRCLKx is the Presc aler x output, which
increments the Counter x value on the rising edge.
TMRCLKx is obtained f rom the internal clock
signal (CLKM) or, only for TIMER0, from the
external signal provided on the PA5/T0CLK pin.

52/84

Figure 10.2 Timer 0 External START/STOP Mode

ST52T410/ST52T420/E420

start

Level

start

Edge

Reset

Clock

Counted

01 10443

2

Value

NOTE:Theexternal clocksignalapplied on the
T0CLK pin m ust have a frequency at least two
times smaller than the internal master clock.

The prescaler output can be selected by setting the
PRESCx bit of REG_CONF6, R EG_CONF 9 and
REG_CONF11 registers (see Table 10.2, Table

10.5 and Table 10.7).

REMARK: The first period of the TxOUT signal
is one clock cycle shorter.

TxRES resets the content of the 8-bit cou nter x to
zero. It is generated by the TIRST x and TxMSK
bits of REG_CONF5, REG_CONF7, REG_CONF8
and REG_CONF10 registers (see Table 10.1,
Table 10.3, Table 10.4 and Ta ble 10.6).

TxSTRT signal starts/stops Timer x counting only
if the peripherals are configured in Timer mode.
This s ignal is forced by setting the correspond ent
TISTRx bit of REG_CONF5, REG_CON F8 and
REG_CONF10 registers (see Table 10.1, Table

10.4 and Table 10.6).
TxMSK bits mas k the reset of eac h timer and can

be utilized to synchronize a simultaneous start of
the time rs by means (for example), of the foll owing
procedure, which starts three t imers :

1) TIRST0 = TIRST1 = TIRST2 = 0,

2) TISTR0 = TISTR1 = TISTR2 = 0,

3) T0MSK = T1MSK = T2MSK = 1,

4) TIRST0 = TIRST1 = TIRST2 = 1,

5) TISTR0 = TISTR1 = TISTR2 = 1,

6) T0MSK = T1MSK = T2MSK = 0,

start

stop

stop

When TxM SK is 1 the TIMER x is reset.

REMARK: to use the simultaneus start, the
prescalers of the Ti m ers must have the same
value. Simultaneus start canno t be used in
Timer mode

Figure 10.3 TIMEROUT Signal Type

Prescout*C ou nter

start

Timer Output
Type 1

Type 2

TIMER0 START/STOP can be providedexternally
on the T0STRT pin. In this case, the T0STRT
signal allows the user to work in two different
modes by setting the TESTR configuration bit of
REG_CONF5 register (s ee Figure 10.2) (Input
capture):

53/84

ST52T410/ST52T420/E420

Figure 10.4 PWM Mode with Auto Reload

255

compare
value

reload
register

0

PWM

Output

t

Ton

T

LEVEL (Time Counter): I f the T0STRT signal is
high the Timer starts counting. When T0STRT is
low the counting ceases and the current value is
stored in the PWM_0_COUNT Input Register.

EDGE(Period Counter): After reset, on the first
T0STRT rising edge, TIMER 0 starts counting and
at the next rising edge it s tops. In this manner, the
period of an ext ernal signal may be measured.

Timer x out put signal, TIMERxOUT is a signal with
a frequenc y equ al to the 16 bit-Prescaler x out put
signal, TMRCLKx, divided by the Output R egister
PWM_x_COUNT value (8 bit) (Output Registers 3,
5 or 7. See Table 2.4), which is the value to count.

Therecan be two types of TIMERxOUT waveform:

type 1: TIMERxOUT waveform equal to a s quare
wave wi th a 50% duty-cycle.

type 2: TIMERxOUT waveform equal to a pulse
signal with the pulse duration equal to the
Prescaler x output signal.

For each Timer x, the TIMERxOUT waveform type
can be selected by setting the correspondent

t

TMRWx bit of REG_CONF6, REG_CONF9 and
REG_CONF11 registers (see Table 10.2, Table

10.5 and Table 10.7)

WARNING: in Timer M od e the
PWM_x_RELOAD output register (see below)
must be set to 0.

10.2 PWM Mode

For each timer, PWM workin g mode is obtained by
setting the correspondent TxMODE bits of
REG_CONF5, REG_CONF8 and REG_CONF10
registers to 1 (see Table 10.1, Table 10.4 and
Table 10.6).

REMARK: The first period of the TxOUT signal
is shorter than the other periods for a time
interval which is [0.5*TMRCLK-CLKM].

TIMERxOUT, in PWM Mode consists of a signal
with a f ixed period, whose duty cycle can be
modified by th e user.

The TIMERxOUT signal can be available on the
TxOUT pin and the TIME R xOUT inverted signal
canbeavailableontheTxOUT
PxSL bits of REG_CONF12 and REG _CONF 16
(see Table 10.8 and Table 10.9)

pin by setting the

54/84

ST52T410/ST52T420/E420

The PWM TIMERxOUT period can be determined
by setting the 16-bit prescaler x output and an
initial autoreload 8-bit counter value stored in the
Output Register PWM_x_RELOAD , as illustrated
in Figure 10.4.

NOTE: the Start/ Stop and Set/ R eset signals
should be moved together in PWM m ode. If the
Start/Stop bit is reset during the PW M mode
working, the TxOUT signal keeps its status
until the next start.

The Output Register P WM_x_RELOAD value is
automatically reloade d when Counter x restarts
counting.

The 16-bit Presc aler x divides the master clock,
CLKM, or, only for TIMER0, the external T0CLK
signal, by the 16-bit Prescaler x.

NOTE: The external clock signal, appl ied on
T0CLK pin m ust have a frequency at least two
times smaller than the internal master clock.

The Presc aler x output can be selected by setting
PRESCx bit of REG_CONF6, R EG_CONF 9 and
REG_CONF11 registers (see Table 10.2, Table

10.5 and Table 10.7).
When Coun ter x reach es the Peripheral Register

PWM_x_COUNT value (Com pare Value),
TIMERxOUT signal changes from high to low level,
up to the next counter start.

The period of the PWM signal is obtained by using
the following equation:

T = (255 - P WM _x_RELOAD)x TMR CLKx

where TMRCLKx is the output of the 16-bit
prescaler x.

The duty cycle of the PWM signal is controlled by
the Output Register PWM _x_COUNT:

Ton =(PWM_x_COUNT- PWM_x_RELOAD)*

TMRCLKx

If the Ou tput Register PWM_x_CO UNT value is
255 the TIMERxOUT signal is always at a high
level.

If the Output Register PWM_x_CO UNT is 0, or
less than the PWM_x_RELOAD value,
TIMERxOUT signal is always at a low level.

NOTE. If PWM_x_RELOAD value increases the
duty cycle resolution decre ases. PWM cannot
work w ith a PWM_x_RELOAD value equal to

255.

By us ing a 20 MHz clock master a PWM frequency
in the range 1.2 Hz to 78.43 Khz can be obtained.

WARNING: loading new values of the counter
or of the reload in the Output Registers, the
PWM/Timer registers are immediately set on­fly. This can cause some side effects during
the current co unting cycle. The next cycles
work normally. This occurs both in Timer and
in PWM mode.

When the Timers a re in Reset, or when the
device is reset, TxOut pins go in threestate. If
these outputs are used to drive external
devices it is recommended to put a pull-up or a
pull-down resistor.

10.3 Timer Interrupt

TIMERx can be programm ed to generat e an
Interrupt request at the end of the count or when
there is an ext ernal TSTART signal. The Timer can
generate programmable Interrupts into 4 different
modes:

Interrupt mode 1: Interrupt on counter Stop.
Interrupt mode 2: Interrupt on Rising Edge of

TIMEROUT.
Interrupt mode 3: Interrupt on Falling Edge of

TIMEROUT.
Interrupt mode 4: Interrupt on bot h edges of

TIMEROUT.
Interrupt mode can be selected by means of

INTSLx and INTEx bits of the REG_CONF5,
REG_CONF8 and REG_CONF10 registers (see
Table 10.1, Table 10.4 and Table 10.6).

NOTE: the interrupt on TIMEROUT rising edge
is also generated after the Start.

WARNING: the first interrupt after starting
PWM is not generated if the counter value is 0,
255, or lower than the reload value. If the PWM/
Timer is configured with the Interrupt on Stop
and the Start/Stop is configured as external, a
low signal in the STRT pin determines a PWM/
Timer interrupt even i f the peripheral is off. If
the interrupt is configured on falling edge, a
reset signal generates an interrupt request.

55/84

ST52T410/ST52T420/E420

Table 10.1 Configu rati on Register 5 Description

Bit Name Value Description

0

TIRST0

1 TERST

2 TISTR0

3 TESTR

4

INTE0

5

6 INTSL0

0 PWM/TIMER 0 Internal RESET
1 PWM/TIMER 0 Internal SET

0 External RESET on Level

1 External RESET on Edge
0 PWM/TIMER 0 Internal STOP

1 PWM/TIMER 0 Internal START
0 External START on Level

1 External START on Edge

00

01

10 TIMER0 Interrupt on Both Edges of TIMER0OUT

11 - not used

0

1

TIMER0 Interrupt on TIMER Interrupt on

TIMEROUT Falling Edge

TIMER0 Interrupt on

TIMER0OUT Rising Edge

TIMER0 Interrupt on

Counter Stop

TIMER0 Interrupt on

TIMER0OUT

0 TIMER MODE

7 T0MODE

1 PWM MODE

Figure 10.5 Configuration Register 5

REG_CONF 5

TIMER 0

D7 D6 D5 D4 D3 D2 D1 D0

56/84

TIRST0: Timer 0 Internal RESET
TERST: Timer 0 External RESET on Edge/Level
TISTR0: Timer 0 Internal START
TESTR: Timer 0 External START on Edge/Level

INTE0: Timer 0 Interrupt on TIMER0OUT Rising/Falling Edge
INTSL0: Timer 0 Interrupt Source selection

T0MODE: Timer 0 working mode

Table 10.2 Configu rati on Register 6 Description

Bit Name Value Description

00000 TIMER0 Clock = CLKM / 1

0

1

2

PRESC0

3

00001 TIMER0 Clock = CLKM / 2
00010 TIMER0 Clock = CLKM / 4

00011 TIMER0 Clock = CLKM / 8
00100 TIMER0 Clock = CLKM / 16
00101 TIMER0 Clock = CLKM / 32

00110 TIMER0 Clock = CLKM / 64

00111 TIMER0 Clock = CLKM / 128
01000 TIMER0 Clock = CLKM / 256
01001 TIMER0 Clock = CLKM / 512
01010 TIMER0 Clock = CLKM/1024

01011 TIMER0 Clock = CLKM/2048

01100 TIMER0 Clock = CLKM/4096

01101 TIMER0 Clock = CLKM/8192

ST52T410/ST52T420/E420

01110 TIMER0 Clock=CLKM/16384

4

01111 TIMER0 Clock=CLKM/32768
10000 TIMER0 Clock=CLKM /65536

0 TIMER0OUT Waveform equal to pulse wave

5 TMRW0

1 TIMER0OUT Waveform equal to square wave
6 - - - not used

7 - - - not used

Figure 10.6 Configuration Register 6

REG_CONF 6

TIME R 0

D7 D6 D5 D4 D3 D2 D1 D0

PRESC0: Timer 0 P re sc aler

TMRW 0: TIMER0O U T waveform

not used

57/84

ST52T410/ST52T420/E420

Table 10.3 Configu rati on Register 7 Description

Bit Name Value Description

0

T0RST

1

2

T0STR

3 10 TIMER0 START External or Internal

4 T0CLK

5 T0MSK

00 TIMER0 RESET
01 TIMER0 RESET External
10 TIMER0 RESET External or Internal

11 - not used
00 TIMER0 START Internal
01 TIMER0 START External

11 - not used

0 TIMER0 Clock Internal
1 TIMER0 Clock External

0

1

TIMER 0 reset synchronization mask.

TIMER 0 RESET enabled

TIMER0 reset synchronization mask.

TIMER0 RESET masked

6 T2MSK

7 T1MSK

Figure 10.7 Configuration Register 7

REG_CONF 7

TIMER 0, TIMER 1, TIMER2

D7 D6 D5 D 4 D3 D2 D1 D0

0

1

0

1

TIMER2 reset synchronization mask.

TIMER2 RESET enabled

TIMER2 reset synchronization mask.

TIMER2 RESET masked

TIMER1 reset synchronization mask.

TIMER1 RESET enabled

TIMER1 reset synchronization mask.

TIMER1 RESET masked

T0RST: Timer 0 R ESET Mode
T0STR: Timer 0 START Mode

T0CLK: Timer 0 Clock Source
T0MSK: Timer 0 RESE T Mask
T2MSK: Timer 2 RESE T Mask

T1MSK: Timer 1 RESE T Mask

58/84

ST52T410/ST52T420/E420

e

Table 10.4 Config. Register 8 D escription

Bit Name Value Description

0 TIRST1

1- - -notused

2 TISTR1

3- - -notused

4

INTE1

5 10 TIMER1 Interrupt on Both Edges of TIMER1OUT

6 INTSL1

0 PWM\TIMER 1 Internal RESET
1 PWM\TIMER 1 Internal SET

0 PWM/TIMER 1 Internal STOP
1 PWM/TIMER 1 Internal START

00 TIMER1 Interrupt on TIMER1OUT Falling Edge
01 TIMER1 Interrupt on TIMER1OUT Rising Edge

11 - not used

0 TIMER1 Interrupt on Counter Stop
1 TIMER1 Interrupt on TIMER1OUT

0 TIMER MODE

7 T1MODE

1 PWM MODE

Figure 10.8 Configuration Register 8

REG_CONF 8

TIMER 1

D7 D6 D5

D4

D3

D2 D1

D0

TIRST1: Timer 1 RESET

- not used
TISTR1: Timer 1 START

- not used
INTE1: Timer 1 Interrupt on TIMER1OUT Rising/Falling Edg
INTSL1: Timer 1 Interrupt Source selection

T1MODE: Timer 1 working mode

59/84

ST52T410/ST52T420/E420

Table 10.5 Config. Register 9 D escription

Bit Name Value Description

00000 TIMER1 Clock = CLKM / 1

0

1

2

3

4

5 TMRW1

6 - - - not used
7 - - - not used

PRESC1

00001 TIMER1 Clock = CLKM / 2
00010 TIMER1 Clock = CLKM / 4

00011 TIMER1 Clock = CLKM / 8
00100 TIMER1 Clock = CLKM / 16
00101 TIMER1 Clock = CLKM / 32

00110 TIMER1 Clock = CLKM / 64

00111 TIMER1 Clock = CLKM / 128
01000 TIMER1 Clock = CLKM / 256
01001 TIMER1 Clock = CLKM / 512
01010 TIMER1 Clock =CLKM / 1024

01011 TIMER1 Clock =CLKM / 2048

01100 TIMER1 Clock =CLKM / 4096

01101 TIMER1 Clock =CLKM / 8192

01110 TIMER1 Clock =CLKM/16384

01111 TIMER1 Clock=CLKM /32768
10000 TIMER1 Clock=CLKM /65536

0 TIMER1OUT Waveform equal to pulse wave
1 TIMER1OUT Waveform equal to square wave

Figure 10.9 Configuration Register 9

REG_CONF 9

TIMER 1

D7 D6 D5 D4 D3 D2 D1 D0

60/84

PRESC1: Timer 1 Prescaler

TMRW1: TIMER1OUT waveform
not used

Table 10.6 Config. Register 10 Description

Bit Name Value Description

ST52T410/ST52T420/E420

0 TIRST2

1 - - - not used

2 TISTR2

3 - - - not used

4

INTE2

5

6 INTSL2

7 T2MODE

0 PWM/TIMER 2 Internal RESET
1 PWM/TIMER 2 Internal SET

0 PWM/TIMER 2 Internal STOP
1 PWM/TIMER 2 Internal START

00 TIMER2 Interrupt on TIMER2OUT Falling Edge
01 TIMER2 Interrupt on TIMER2OUT Rising Edge

10 TIMER2 Interrupt on Both Edges of TIMER2OUT
11 - not used

0 TIMER2 Interrupt on Counter Stop
1 TIMER2 Interrupt on TIMER2OUT
0 TIMER MODE
1 PWM MODE

Figure 10.10 Configuration Register 10

REG_CONF 10

D7 D6 D5

TIMER 2

D3

D4

D2 D1

D0

TIRST2: Timer 2 RESET

- not used
TISTR2: Timer 2 START

- not used
INTE2: Timer 2 Interrupt on TIMER2OUT Rising/Falling Edge
INTSL2: Timer 2 Interrupt Source selection

T2MODE: Timer 2 working mode

61/84

ST52T410/ST52T420/E420

Table 10.7 Config. Register 11 Description

Bit Name Value Description

00000 TIMER2 Clock = CLKM / 1

0

1

2

3

4

5 TMRW2

6 - - - not used
7 - - - not used

PRESC2

00001 TIMER2 Clock = CLKM / 2
00010 TIMER2 Clock = CLKM / 4

00011 TIMER2 Clock = CLKM / 8
00100 TIMER2 Clock = CLKM / 16
00101 TIMER2 Clock = CLKM / 32

00110 TIMER2 Clock = CLKM / 64

00111 TIMER2 Clock = CLKM / 128
01000 TIMER2 Clock = CLKM / 256
01001 TIMER2 Clock = CLKM / 512
01010 TIMER2 Clock = CLKM /1024

01011 TIMER2 Clock = CLKM/ 2048

01100 TIMER2 Clock = CLKM/ 4096

01101 TIMER2 Clock = CLKM/ 8192

01110 TIMER2 Clock= CLKM/16384

01111 TIMER2 Clock =CLKM/32768
10000 TIMER2 Clock =CLKM/65536

0 TIMER2OUT Waveform equal to pulse wave
1 TIMER2OUT Waveform equal to square wave

Figure 10.11 Configuration register 11

REG_CONF 11

TIMER 2

D7 D6 D5 D4 D3 D2 D1 D0

62/84

PRESC2: Timer 2 Prescaler

TMRW2: TIMER2OUT waveform

not used

Table 10.8 Config. Register 12 Description

Bit Name Value Description

0PA1

1PA2

2PA3

3PASZ

4 - - - not used
5 - - - not used
6 - - - not used
7 - - - not used

0 Pin PA1/T0OUT
1 Pin PA1/ T0OUT
0 Pin PA2/ T1OUT
1 Pin PA2/ T1OUT
0 Pin PA3/ T2OUT
1 Pin PA3/ T2OUT
0 PORT A bits = 7
1 PORT A bits = 8

equal to PORT A Digital I/O

equal to PORT A Digital I/O

equal to PORT A Digital I/O

ST52T410/ST52T420/E420

equal to T0OUT

equal to T1OUT

equal to T2OUT

Figure 10.12 Configuration Register 12

REG_CONF 12

DIGITAL PORT

D7 D6

D5

D4 D3 D2 D1 D0

PA1: Pin PA1/T0OUT setting

PA2: Pin PA2/T1OUT setting

PA3: Pin PA3/T2OUT setting

PASZ: PORT A size

not used

63/84

ST52T410/ST52T420/E420

Table 10.9 Config. Register 16 Description

Bit Name Value Description

0 PC1

1 PC2

2 PC3

3-7 - - - not used

Figure 10.13 Configuration Register 16

1 Pin T0OUT/PC1 equal to PORT C Digital I/O
0 Pin T0OUT/PC1 equal to T0OUT
1 Pin T1OUT/PC2 equal to PORT C Digital I/O
0 Pin T1OUT/PC2 equal to T1OUT
1 Pin T2OUT/PC3 equal to PORT C Digital I/O
0 Pin T2OUT/PC3 equal to T2OUT

64/84

ST52T410/ST52T420/E420

Table 10.10 Input Registers 13.

PWM_0_STATUS

Bit Name Value Description

0 STR0 0 TIMER 0 is STOP

1 TIMER 0 START

1 RST0 0 TIMER 0 is RESET

1

2 - - - not used
3 - - - not used
4 - - - not used
5 - - - not used
6 - - - not used
7 - - - not used

TIMER 0 is NOT

RESET

Table 10.11 Input Registers 15.

PWM_1_STATUS

Table 10.12 I nput Registers 17.

PWM_2_STATUS

Bit Name Value Description

0 STR2 0 TIMER 2 is STOP

1 TIMER 2 is START

1 RST2 0 TIMER 2 is RESET

1

2 - - - not used
3 - - - not used
4 - - - not used
5 - - - not used
6 - - - not used
7 - - - not used

TIMER 2 is NOT

RESET

Bit Name Value Description

0 STR1S 0 TIMER 1 is STOP

1 TIMER 1 is START

1 RST1S 0 TIMER 1 is RESET

1 TIMER 1 is NOT
2 - - - not used
3 - - - not used
4 - - - not used
5 - - - not used
6 - - - not used
7 - - - not used

65/84

ST52T410/ST52T420/E420

11 ELECTRICAL CH ARACTERISTICS

11.1 Parameter Conditions

Unless otherwise specified, all v oltages are
referred to V

ss.

11.1.1 Minimum and Maximum values.

Unless otherwise specified, the minimum and
maximum values are guaranteed in the w ors t
conditions of environment temperature, supply
voltage and frequencies production testing on
100% of the devices with an environmental
temperature at T

=25°C and TA=TAmax (given by

A

the selected temperature range).
Data is based on characterization results, design

simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. The minim um and maximum values
are based on characterization and refer to sample
tests, representing th e mean value plus or minu s
three times the standard deviation (mean ±3Σ).

11.1.2 Typical values.

Unless otherwise spec ified, typical data is based

=25°C, VDD=5V (for the 4.5≤VDD≤5.5V

on T

A

voltage range). They are provided only as design
guidelines and are not tested.

11.1.4 Loading capacitor. T he loading condition
used for pin parameter measurement is illustrated
in Figure 11.1.

11.1.5 Pin input voltage.

Input voltage m easurement on a pin of the device
is described in Figure 11.2

Figure 11.2 Pin input Voltage

ST52 PIN

V

IN

11.1.3 Typical curves.

Unless otherwise spec ified, all typical curves are
provided only as design guidelines and are not
tested.

Figure 11.1 Pin loading conditions

ST52 PIN

C

L

11.2 Absolute Maxim um Ratings

Stresses above those listed as “absolute maximum
ratings” may cause permanent damage to the
device. This is a stress rating only.

Functional operation of the dev ice under these
conditions is not implied. Exposure t o maximum
rating conditions for extended periods may affect
device reliability.

66/84

Table 11.1 Voltage Characteristics

Symbol Ratings Maximum Value Unit

ST52T410/ST52T420/E420

V

DD-VSS

Analog reference voltage(VDD≥V

Variation betwee n different digital power pins 50

Variation betwe en digital and analog ground pins 50

|∆V

V

DDA-VSSA

|and |∆V

DDA

|V

SSA-VSSX

V

|

SSA

|

IN

Input voltage on any other pin

V

DESD

Electro-static discharg e voltage 2000

Table 11.2 Cu rrent Characteristics

Symbol Ratings Maximum Value Unit

I

VDD

I

VSS

I

I

INJ(PIN)

ΣI

INJ(PIN)

IO

To tal current in VDDpower lines (source)

Total curren t in VSSground lines (sink)

Standard Outp ut Source Sink curren t ±16

Injected current on RESET pin ±5

Injected current on OSCin and OSCout pins ±5

Injected current on any other pin

To tal Injected curren t (sum of all I/O and control

Supply voltage 6.5

)6.5

DDA

Input voltage on V pp VSS-0.3 to 13

1) & 2)

3)

3)

VSS-0.3 to VDD+0.3

100
100

Injected current on VPPpin ±5

pins)

4)

4)

±5

±20

V

mV

V

mA

Table 11.3 T herm al Characteri stics

Symbol Ratings Maximum Value Unit

T

A

T

STG

T

J

Notes:

1. Connecting RESET and I/O P ins directly to V
or an unexpected change of I/O configuration occurs (for example, due to t he corrupted program counter). In order to guarantee
safe operation, this connection has to be pe rforme d via a pul l-up or pull -down res istor (typical: 4.7k
Unused I/O pins m ust be tied in t he same manner to VDD or VSS according to their reset configuration.

2. When the current limitatio n is not possible, the VIN absolute max imum ra ting m ust be respected, otherwise refer to I
specification. A positive injecti o n is ind uced by V IN >V DD while a negative injection is induced by VIN<VSSto I INJ(PIN) specification.
A positive injection is VIN>VDD while a negative injection is induced by V

3. All power (V

4. When several inputs are submitted to a current injection, the maximum ΣI
injected currents (instantaneousvalues).

DD) and ground (VSS) lines must always be c onnec ted t o t he external supply.

Operating temper ature -25 to +85 °C

Storage temp eratur e range -65 to +150 °C

Maximum junction temperat ure 150 °C

DD or VSS c ould damage the device if the unintentional internal reset is generated

Ω forRESET, 10K Ω for I/Os).

IN<VSS.

is the absolute sum of the positive and negative

INJ(PIN)

INJ(PIN)

67/84

ST52T410/ST52T420/E420

11.3 Recommended Operating Condition

Operating condition: V

Table 11.4 Recommended O perating Conditions

Symbol Parameter Test Condition Min. Typ. Max Unit

V

DD

V

PP

V

O

V

DDA,VSSA

DD=5V±10%; TA=-25/85°C (unless oth erwise specified).

Operating Supply

Programming Voltage 11.4 12 12.6

Output Voltage V

Analog Supply Voltage

1)2)

1)

Refer to Figure 11.3 4.75 5.0 5.25

SS

VSS≤V

SSA≤VDDA≤VDD

V

SS

V

DD

V

DD

V

f

OSC

1)2)

Oscillator Frequency 1 20 MHz

Notes:

1. The ma ximum difference between V
in module. The minimum value of V

2. V

3. The

depend on f

DD

f

OSC

4. Lower V

minallowedtousetheA/DConverteris2MHz

decreasing f

DD

seeFigure11.3

OSC ,

osc

(see Figure 11.3). Data illustrated in the figure are characterized but not test-

SS

DDA

and V

is 3 V.

and between VDDand V

SSA,

ed.

Figure 11.3 fosc Maximum Operating Frequency versus VDD supply

20
18
16
14
12

Functionality not guarateed in this area

must be less than 0.6 V

DDA,

68/84

max (MHz)
f

10

8

osc.

6

Functionality guarateed in this area

4
2

Functionality not guarateed in this area

0

0

0.5

1 1.5 2 2.5 3 3.5

4.5

4

5.5

5

Vdd (V)

ST52T410/ST52T420/E420

11.4 S upply Current Ch aracteristics

Supply c urrent is mainly a f unction of the operating
voltage and frequency. Other factors such as I/O
pin loading and switching r ate, oscillator type,
internal c ode execution pattern and t emperature,
also have an impact on the current consumption.

The test condition in RUN mode for all the IDD
measurements are:

OSCin = e xternal square wave, from rail to rail;
OSCout = floating;
All I/O pins tristated pulled to VDD

A=25°C

T

Table 11.5 Supply Current in RUN and WAIT Mode

Symbol Parameter Conditions Typ

f

=2 Mhz 4.34 4.34

osc

f

=4 Mhz 7.66 7.72

osc

f

=5 Mhz 8.75 8.81

Supply current in RUN mode

1)

VDD=5V±5%

I

DD

TA=25°C

Supply current in WAIT mode

2)

osc

f

=8 Mhz 12.67 12.89

osc

=10 15.04 15.13

f

osc

f

=20 27.3 27.48

osc

f

=2 MHz 1.14 1.16

osc

f

=4 MHz 3.38 3.39

osc

f

=5 MHz 3.63 3.71

osc

f

=8 Mhz 5.63 5.68

osc

f

=10 6.29 6.31

osc

f

=20 13.22 13.3

osc

Notes:

1. CPU running with memory access, all I/O pins in input mode with a s tatic value at V

all peripherals switched of f; clock input (OSCin driven by external square wave).

2. CPU in WAIT mode with all I/O pins in input mode with a static value at V

DD

peripherals switched off; clock input (OSCin driven by ex ternal square wave).

3. Data based on characterization res ults, tested in production at V

DDmax

and f

oscmax

3)

Max

Unit

mA

or VSS(no load),

DD

or VSS(no load), all

.

Figure 11.4 Typical IDD in RUN vs fosc

35
30
25
20
15

IDD[mA]

10

5
0

2 2.5 3 3 .5 4 4 .5 5 5.5 6

VDD[V]

2M Hz 4M Hz 5MH z 8MH z 10M Hz 20MHz

Figure 11.5 Typical ID D in WAIT vs fosc

14
12
10

8
6

IDD[mA]

4
2
0

22.533.544.555.56

VDD[V]

2M H z 4MH z 5MH z 8MH z 10M H z 20M Hz

69/84

ST52T410/ST52T420/E420

Table 11.6 Supply Current in HALT Mode

Symbol Parameter Conditions

I

DDA Supply current in HALT mode

2)

3.0 V≤ VDD ≤ 5.5 V 1 10 µA

Notes:

1. Typical data is based on TA = 25 °C

2. All I/O pins in input mode with a static value at V

DD or VSS (no load)

Table 11.7 On - Chi p Peripheral

Symbol Parameter Conditions

I

DDA

ADC Supply current when converting

fosc=20MHz, V

VssA = Vss

Notes:

V

SSA=VSS

= 5 ±5% V,

DDA

Typ

1)

Typ

Max Unit

3

12mA

Max

4

Unit

3. Typical data is based on T

=25°C, V

A

DDA

=5 V.

4. Data is bas ed on characterization results and isn’t tested in production.

70/84

ST52T410/ST52T420/E420

11.5 Clo ck and Timing Characteristics

Operating Conditions: V

Table 11.8 General Timing P arameters

Symbol Parameters Test Condition Min Typ. Max Unit

DD=5V ±5%, TA=-25/85°C, unless otherwise specified

f

osc

t

CLH

t

CLL

t

SET

t

HLD

t

WRESET

t

WINT

t

IR

t

IF

t

OR

t

OF

Oscillator Frequency 1 20 MH

Clock High 25 500

Clock Low 25 500

Setup See Figure 11.6 5

Hold See Figure 11.6 5

Minimum Reset Pulse Width f

Minimum External Interrupt

Pulse Width

Input Rise Time See Figure 11.7 15

Input Fall Time See Figure 11.7 15

Output Rise Time C

Output Fall C

=20MHz 100

osc

=20MHz

f

osc

=10pF 10

LOAD

=10pF 10

LOAD

100

nS

Figure 11.6 Data Input Timing

t

CLL

t

CLH

50%

t

CP

Data

Clock

50%

t

SETtHLD

50%

Figure 11.7 I/O Rise and Fall Timing

71/84

ST52T410/ST52T420/E420

11.6 Memory Characteristi cs

Subject to general operating conditions f or V

Table 11.9 RAM and Registers

Symbol Parameter Conditions Min. Typ. Max Unit

DD,fosc and T A , unless otherwise specified.

RM

V

Data retention

1)

mode

HALT mode (or

RESET)

1.6 V

Table 11.10 E PRO M Program Memory

Symbol Parameter Conditions Min. Typ. Max Unit

ERASE UV lamp

W

Lamp

wavelength

2537 A

15

Watt,

sec/cm

UV lamp is

placed 1 inch

tERASE

Erase time

2)

from the device
window without

7 15 min.

any interposed

filters

RET Data Retention

t

A =+55°C

T

20 years

Notes:

1. Minimum V

DD supply voltage without losing data stored into RAM (in HALT mode or under R ESE T) or

into hardware registers (only in HALT mod e). Guaranteed by construction, not tested in produc tion.

2. Data is provid ed only as a guideline.

2)

72/84

ST52T410/ST52T420/E420

11.7 E SD Pin Protection Strategy

In order to protect an integrated circuit against
Electro-Static Discharge the stress must be
controlled to prevent degradation or des truction of
the circuit elements. Stress generally affects the
circuit elements, which are connected to the pads
but can also affect the internal devices when the
supply pads receive the stress. The elements that
are to be protected must not receive excessive
current, voltage, or heating within the ir structure.

An E S D network combin es the different input and
output protections. This network works by allowing
safe discha rg e paths for the pins subject to ESD
stress. Two critical ESD stress cases are

presented in Figure 11.8 and Figure 11.9 for
standard pins.

11.7.1 Standard Pin Protection

In order to protect the output structure the following
elements are added:

-AdiodetoV

- A protection device between V
In order protect the input structure the follow ing

elements are added:

- A resistor in series with pad (1)

-AdiodetoV

- A protection device between V

Figure 11.8 Safe discharge pa th subjected to ESD stress

VDD

(3a)

OUT (4) IN

Main path
Path to avoid

(3b)

(3a) and a diode from VSS(3b)

DD

and VSS(4)

DD

(2a) and a diode from VSS(2b)

DD

and VSS(4)

DD

VDD

(2a)

(1)

(2b)

VSS

Figure 11.9 Neg ativ e Stress on a Standard Pad vs. VDD

VDD

(3a)

(4) IN

OUT

Main path

(3b)

VSS

VSS

VDD

(2a)

(1)

(2b)

VSS

73/84

ST52T410/ST52T420/E420

11.7.2 Multi-supply Configuration.

When several types of ground (V
power supply (V

DD,VDDA

,...) are available for any

SS,VSSA

,...) and

illustrated in F igure 11.10 is implemented in order
to protect the device against ESD .

reason (better noise immunity...), the structure

Figure 11.10 ESD Protection for Multisupply Configuration

VDD

(4)

VSS

BACKTO BACKDIODE
BETWEEN GROUNDS

VDDA

(4)

VDDA

VSSA

74/84

11.8 P ort Pin Characteristics

11.8.1 General Characteristics.

Subject to general operating condition for V

DD,fosc,

ST52T410/ST52T420/E420

and TA,unless otherwise specified.

Symbol Parameter Condition Min

CMOS type low level input voltage.

Port B pins. (See Figure 11.13)

V

IL

V

IH

V

hys

I

L

I

S

TTL type Schmitt trigger low level

input voltage. Port A and Port C

pins. (See Figure 11.12)

CMOS type high level input voltage.

Port B pins. (See Fig 11.13)

TTL type Schmitt trigger high level

input voltage. Port A and Port C

pins. (See Fig. 11.12)

Schmitt trigger voltage hysteresis

Input leakage current

Static current consumption

3)

3.3

2.2

2)

V

SS≤VIN≤VDD

Floating input mode 200

-1 4

Typ

1.4

1)

Max Unit

2

0.8

V

µA

Notes:

1. Unless otherwise specified, typical data is bas ed on T

=25 °C and VDD=5 V

A

2. Hysteresis voltage between Schmitt trigger switching level. Based on characterization results, not

tested in production.

3. Configuration is not recommended, all unused pins must be kept at a fixed voltage : using the output

mode of the I/O for exam ple or an external pull-up o r pull-down resistor (see Figure 11.11). Data based
on design simulat ion and/or technology c haracteristics is not tested in productio n.

Figure 11.11 Recommended configuration for unused pins

VDD

ST52

10k

UNUSEDI/O PORT

UNUSEDI/O PORT

10k

ST52

75/84

ST52T410/ST52T420/E420

Subject to general operating conditions for VDD,fosc,andTA, unless otherwise specified.

Table 11.11 Output Voltage Levels

Symbol Parameter Conditions Min Typ Max Unit

+

Output low level voltage for standard I/O

1)

V

OL

V

OH

pin when 8 pins are sunk at same time.

Output high level voltage for standard I/

2)

O pin when 8 pins are sourced at same

time.

V

=5V, IIO=+8mA

DD

=5V, IIO=- 8mA

V

DD

V

DD

0.5

-

Notes:

1. The I
(I/O ports and control pins) must not exceed I

current sunk must always respects the absolute maximum rating specified in Section 11.2 and the sum of I

IO

VSS

2. The IIOsourced current must always respect the absolute maximum rating specified in Section 11.2and the sum of I
(I/O ports and control pins) must not exceed I

VDD.

V

SS

0.4
V

IO

IO

Figure 11.12 TTL-Level input Schmitt Trigger

5

V(V)

o

4

3

2

1

0.5 0.8 1.0 1.5 2.0 2.5

0

V(V)

i

V=5V

DD

T = 25°C

A

(TYPICAL)

Figure 11.13 Port B pins CMOS-level input

5

V(V)

o

4

3

2

1

0

2.0 3.3 5.0
V(V)

i

V=5V

DD

T = 25°C

A

(TYPICA L )

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ST52T410/ST52T420/E420

R

V

I

N

Subject to general operating condition for VDD,fosc, and TA, unless otherwise specified.

Table 11.12 Output Driving Current

Symbol Parameter Test Conditions Min Typ Max Unit

S Input protection resistor All input Pins 1

R

CS Pin Capacitance All input Pins 5 pF

Figure 11.14 Port A and Port C pin Equivalent Circuit

V

DD

Device
Input/Output

S

Ω

k

S

C

SS

V

V

Figure 11.15 Port B Pin Equivalent Circuit

V

Device
Input/Output

S

C

SS

DD

R

OUT

V

S

V

IN

OUT

V

V

SS

V

SS

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ST52T410/ST52T420/E420

11.9 Control Pin Cha racteristics

11.9.1 RESET pin.

Subject to general operating conditions f or V

Table 11.13 Reset pin

Symbol Parameter Conditions Min Typ Max Unit

DD,fosc, and TA, unless otherwise specified

V

IL

V

IH

V

hys

t

w(RSTL)out

t

h(RSTL)int

11.9.2 V

PP

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

General reset pulse duration 30

External reset pulse hold time 20

pin.

1)

1)

Subject to general operating conditions f or V

Table 11.14 V

PP

4)

pin

2)

DD,fosc

VDD=5V

VDD=5V

VDD=5V

2.2

1.4

, and TA,unless otherwise specified.

0.8

Symbol Parameter Conditions Min Typ Max Unit

V

IL

V

IH

Input low level voltage

Input high level voltage

3)

3)

V

SS

VDD-0.1

0.2

12.6

V

µS

V

Notes:

1. Data is based on characterization results, not tested in production.

2. Hysteresis voltage between Schm it t trigger switching level.
Based on characterization results not tested in production.

3. Data is based on design simulation and/or technology characteristics, not tested in production.

4. In work ing mode V

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must be tied to V

PP

SS

ST52T410/ST52T420/E420

11.10 8-bit A/D Characteri stic s

Subject to general operating conditions f or V

Symbol Parameter Conditions Min Typ Max Unit

Res Resolution 8 bit

DD,fosc, and TA, unless otherwise specified.

A

TOT Total Accuracy

V

V

V

AD

AC

f

ADC

t

C

AN

ZI

FS

I

IN

Conversion Time 82/f

Conversion Range V

Zero Scale Voltage

Full Scale Voltage

Analog Input Current

during Conversion

Analog Input Capacitance 25 pF

ADC Clock frequency f

Notes:

1. Noise on V

DDA,VSSA

<40mV

1)

1 MHz<f

< 20 MHz ±1 LSB

ADC

Conversion result =

00 Hex

Conversion result =

FF Hex

f

=20MHz

ADC

ADC

SSA

V

SSA

V

DDA

1 µA

/2 f

osc

160/f

V

ADC

DDA

osc

µS

V

V

V

MHz

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ST52T410/ST52T410/E420

Table 11.15 PS028 PACKAGE MECHANICAL DAT A

DIM

MIN TYP. MAX MIN TYP. MAX

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45°(typ.)

D 17.7 18.1 0.697 0.713

E 10 10.65 0.394 0.419
e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299
L 0.4 1.27 0.016 0.050
S 8°(max)

mm inch.

L

C

1

c

A

s

b

e3

D

28

1

e

15

F

14

a1

E

b1

80/84

ST52T410/ST52T420/E420

Table 11.16 Plastic DIP 28 PACKAGE MECHANICAL DATA

DIM

MIN TYP. MAX MIN TYP. MAX

A 5.08 0.200
A1 0.38 0.015
A2 3.56 4.06 0.140 0.160

B 0.38 0.51 0.015 0.020
B1 1.52 0.060

C 0.20 0.30 0.008 0.012

D 36.83 37.34 1.450 1.470
D2 33.02 1.300

E 15.24 0.600
E1 13.59 13.84 0.535 0.545

e1 2.54 0.100
eA 14.99 0.590
eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α 0° 10° 0° 10°
N28 28

mm inch

B1

S

N

1

B

D2

D

2
A

A

1
A

e1

1

E

E

eA

eB

C

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ST52T410/ST52T410/E420

Table 11.17 CERAMIC DIP28 WINDOWED PACKAGE MECHANICAL DAT A

DIM

MIN TYP. MAX MIN TYP. MAX

A 38.10 1.469
B 13.05 13.36 0.514 0.526
C 3.90 5.08 0.153 0.177
D 3.18 0.125
E 0.50 1.78 0.020 0.070

e3 33.02 1.300

F 2.29 2.79 0.90 0.110

G 0.40 0.55 0.18 0.22

I 1.17 1.42 0.48 0.58

L 0.22 0.31 0.010 0.012

M 1.52 2.49 0.060 0.098

N 16.17 18.32 0.637 0.721

N1 4d 15d

P 15.40 15.80 0.606 0.616

Q 5.71 0.225

Diam. 6.86 7.36 0.275 0.285

mm inch.

M

C

b

P

E

N1

L

I

G

F

D

N

e3

A

28

Diam.

B

1

82/84

ST52T410/ST52T420/E420

ORDERING INFORMATION

Each device is available for production in user programmable version (OTP) as well as in factory pro­grammed version (FASTROM). O TP devices are shipped to the cust omer with a default blank content
FFh, while FASTROM factory programmed parts contain the code sent by the customer. There is one
common EPROM version for debugging and prototyping, which features the maximum memory size and
peripherals of the fami ly. Care must be taken only to use resources available on the target device.

Figure 11.16 Device Types Selection Guide

ST52 t nnn c m p y

TEMPE RA TUR E RANGE :

6 =-40to85°C

PACKAGES:

B =PDIP
M=PSO
D= CDIP

MEMORY SIZE:

0 =1Kb
1=2Kb
2=4Kb

PIN COUNT:

G =28pin

SUBFAMILY:

410, 420

MEMORY TYPE:

T =OTP
E=EPROM

FAMILY

PART NUMBER TEMPERATURE RANGE PACKAGE

ST52T410G0B6 -40 to +85 °CPDIP

ST52T410G0M6 -40 to +85 °CPSO

ST52T410G1B6 -40 to +85 °CPDIP

ST52T410G1M6 -40 to +85 °CPSO

ST52T410G2B6 -40 to +85 °CPDIP

ST52T410G2M6 -40 to +85 °CPSO

ST52T420G0B6 -40 to +85 °CPDIP

ST52T420G0M6 -40 to +85 °CPSO

ST52T420G1B6 -40 to +85 °CPDIP

ST52T420G1M6 -40 to +85 °CPSO

ST52T420G2B6 -40 to +85 °CPDIP

ST52T420G2M6 -40 to +85 °CPSO

ST52T420G2D6 -40 to +85 °CCDIP

83/84

Full ProductInformation at http://www.st.com/five

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useofsuch information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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