Datasheet ST5092TQFP, ST5092AD Datasheet (SGS Thomson Microelectronics)

2.7V SUPPLY14-BIT LINEAR CODEC

WITH HIGH-PERFORMANCEAUDIO FRONT-END

FEATURES:
CompleteCODECandFILTERsystemincluding:

14 BIT LINEAR ANALOG TO DIGITAL AND
DIGITALTO ANALOG CONVERTERS.

8 BIT COMPANDED ANALOG TO DIGITAL
AND DIGITAL TO ANALOG CONVERTERS
A-LAW OR µ-LAW.

TRANSMIT ANDRECEIVE BAND-PASSFILTERS
ACTIVEANTIALIAS NOISE FILTER.

Phone Features:

THREE SWITCHABLE MICROPHONE AM­PLIFIER INPUTS. GAIN PROGRAMMABLE:
20 dB PREAMP. (+MUTE), 0 . . 22.5 dB AM­PLIFIER,1.5 dB STEPS.

EARPIECE AUDIO OUTPUT. ATTENUATION
PROGRAMMABLE:0 .. 30dB, 2 dB STEPS.

EXTERNAL AUDIO OUTPUT. ATTENUATION
PROGRAMMABLE:0 .. 30dB, 2 dB STEPS.

TRANSIENT SUPRESSION SIGNAL DURING
POWER ON AND DURING AMPLIFIER
SWITCHING.

INTERNAL PROGRAMMABLE SIDETONE
CIRCUIT. ATTENUATION PROGRAMMABLE:
16 dB RANGE, 1 dB STEP. ROUTING POSSI­BLE TOBOTH OUTPUTS.

INTERNALRING OR TONE GENERATORIN­CLUDING DTMF TONES, SINEWAVE OR
SQUAREWAVE WAVEFORMS. ATTENU­ATION PROGRAMMABLE: 27dB RANGE,
3dB STEP.THREE FREQUENCYRANGES:

a) 3.9Hz. . .. 996Hz, 3.9Hz STEP

b) 7.8Hz. . .. 1992Hz, 7.8Hz STEP

c) 15.6Hz .. .. 3984Hz,15.6Hz STEP

PROGRAMMABLE PULSE WIDTH MODU­LATED BUZZERDRIVEROUTPUT.

GeneralFeatures:

SINGLE2.7Vto 3.6VSUPPLY
EXTENDED TEMPERATURE RANGE OPERA -

TION(*)-40°Cto85°C.

1.5 µW STANDBY POWER (TYP. AT 3.0V).
15mW OPERATING POWER (TYP. AT 3.0V).
13mW OPERATING POWER (TYP. AT 2.7V).
CMOSCOMPATIBLE DIGITAL INTERFACES.
PROGRAMMABLE PCM AND CONTROL IN-

TERFACE MICROWIRECOMPATIBLE.

ST5092

PRELIMINARY DATA

TQFP44(10x10x1.4)

ORDERING NUMBERS:

Package Dim. Cond.

ST5092AD
ST5092ADTR
ST5092TQFP
ST5092TQFPTR

SO28
SO28
TQFP44
TQFP44

APPLICATIONS:

GSM DIGITAL CELLULAR TELEPHONES.
CT2 DIGITAL CORDLESSTELEPHONES.
DECTDIGITALCORDLESSTELEPHONES.
BATTERY OPERATED AUDIO FRONT-ENDS

FORDSPs.

(*) Functionality guaranteedin the range – 40°C to +85°C;

Timingand Electrical Specificationsare guaranteedin the range

–30°C to +85°C.

GENERALDESCRIPTION

ST5092isa high performancelowpowercombined
PCMCODEC/FILTERdevice tailored to implement
the audio front-end functions required by the next
generation low voltage/low power consumption
digitalterminals.
ST5092 offers a number of programmable func­tionsaccessed througha serialcontrolchannelthat
easilyinterfacesto anyclassical microcontroller.
ThePCM interfacesupportsbothnon-delayed(nor­mal and reverse) and delayed frame synchroniza­tionmodes.
ST5092 can be configuratedeither as a 14-bit lin­earorasan8-bitcompandedPCMcoder.
Additionally to the CODEC/FILTER function,
ST5092 includes a Tone/Ring/DTMF generator, a
sidetonegeneration,and a buzzerdriveroutput.
ST5092fulfillsandexceedsD3/D4 and CCITT rec­ommendations and ETSI requirements for digital
handsetterminals.
Main applicationsinclude digitalmobilephones,as
cellular and cordless phones,or any battery pow­ered equipmentthat requiresaudio codecsoperat­ingatlowsinglesupplyvoltages

SO28

10x10x1.4
10x10x1.4

Tube
Tape&Reel
Tray 8x20
Tape&Reel

June 1997

This is preliminaryinformation on anew productnow in developmentor undergoing evaluation. Details are subject tochange without notice.

1/29

ST5092

PIN CONNECTIONS (Topview)

N.C.

N.C.

VCCP

VCCA

44 43 42 41 3940 38 37 36 35 34

N.C.

N.C.

MIC3+

MIC3-

GNDA

N.C.

MIC1+

N.C.

V

CCA

V

CCP

N.C.

V

Fr-

V

Fr+

V

Lr-

V

Lr+

GNDP MCLK

D

2
3
4
5
6

SO28

7
8
9
10

R

CCLK

CS-

CI CO

12
13

28
27
26
25
24
23
22
21
20
19
18
17
16
1514BZ V

D94TL094

BLOCK DIAGRAM

MIC3+1
MIC3­GNDA
MIC1+
MIC1­MIC2+
MIC2­LO

FS
GND11
D

x

CC

N.C.

VFr-

VFr+

N.C.

VLr-

VLr+

N.C.

GNDP

N.C.

DR

N.C.

1

2

3

4

5

6

7

8

9

10

12 13 14 15 16

N.C.

N.C.

CCLK

TQFP44

171118 19 20 21 22

CI

CS-

BZ

VCC

CO

DX

GND

N.C.

33

32

31

30

29

28

27

26

25

24

23

MIC1-

N.C.

MIC2+

MIC2-

N.C.

N.C.

N.C.

LO

MCLK

FS

N.C.

D94TL095

2/29

MIC3-

MIC2-

MIC1-

MIC2+

MIC1+

MIC3+

VFr-

VFr+

VLr-

VLr+

EARA OUTPUT

-1

12dB

1

OE

-1

12dB

1

EXTA OUTPUT

MIC

PREAMP

20dB

+ MUTE

VS & TE

0 -> -30dB,

2dB STEP

RTE

SE

SI

D93 TL074

AMP

MIC

0 -> 22.5

1.5dB STEP

TONE

0 -> -27dB
3dB STEP

SIDETONE

-12.5 -> -27.5dB
1dB STEP

AMP

PREFILTER &

DE

(A)

(B)

AMP

BANDPASS

FILTER

BANDPASS

FILTER

TONE, RING

& DTMF
GENER.

& FILTER

GNDP GNDA GND VCCA VCC VCCP

PCM ADC

PCM DAC

BE

EN

TRANSMIT
REGISTER

RECEIVE

REGISTER

EN

CONTROL INTERFACE

µ-WIRE

CLOCK GENERATOR

& SYNCHRONIZER

INTERFACE LATCH

BUZZER

DRIVER

LEVEL

ADJUST

(PWM)

DX

DR

CO

CI

CS­CCLK
MCLK

FS

LO

BZ

PIN FUNCTIONS(SO28)

Pin Name Description

1 N.C. Not Connected.
2V

3V
4 N.C. Not Connected.

5,6 V

7,8 V

Fr+,VFr–

Lr+,VLr–

9 GNDP Power ground. V

10 D

11 CCLK Control Clock input: Thisclock shifts serial control information into CI and out from CO when the

12 CS- Chip Select input: Whenthis pin is low, controlinformation is written into and outfrom the ST5092

13 CI Control data Input: SerialControl information is shifted into theST5092 on this pin when CS- is low

14 BZ Pulse widthmodulated buzzer driver output.
15 V
16 CO Controldata Output: Serial control/statusinformation isshifted out from the ST5092 on this pin

17 D

18 GND Ground: All digital signalsare referenced to this pin.
19 FS Frame Sync input: This signal is a 8kHz clock whichdefines thestart of the transmit andreceive

20 MCLK MasterClockInput:Thissignal isusedby theswitchedcapacitorfiltersandthe encoder/decoder

21 LO A logic 1 written intoDO (CR1) appears at LO pin as a logic 0

22 MIC2- Secondnegativehigh impedanceinput to transmit pre-amplifier for microphoneconnection.
23 MIC2+ SecondPositivehigh impedance inputto transmitpre-amplifier for microphone connection.
24 MIC1- Negativehigh impedanceinputto transmitpre-amplifier for microphoneconnection.
25 MIC1+ Positivehighimpedance input to transmitpre-amplifier for microphone connection.
26 GNDA Analog Ground: All analogsignals arereferenced tothis pin.GND and GNDA must be connected

27 MIC3- Thirdnegativehigh impedance outputtotransmitpreamplifier formicrophone connection.
28 MIC3+ Thirdpositive high impedance outputto transmit preamplifier for microphone connection.

Positive power supplyinput for the analog section.

CCA

V

and V

CC

Positive power supplyinput for the power section.V

CCP

must be direc t ly conn ec ted toget her.

CCA

and VCCmust be connected together.

CCP

Receive analog earpiece amplifier complementary outputs.Theseoutputscan drive directly earpiece
transductor. Thesignalat this output canbe the sum of:

- Receive Speech signal from D

,

R

- Internal Tone Generator,

- Sidetone signal.
Receive analogextra amplifier complementary outputs. The signalat these outputs can be the

sum of:

- Receive Speech signal from DR,

- Internal Tone generator,

- Sidetone signal.
and VLrdriver are referencedto thispin. GNDP and GND must be connected

Fr

together close tothe device.
Receive datainput:Data is shiftedin during the assigned Received timeslots In delayed andnon-

R

delayed normalframesynchr.modes voicedata byteis shiftedin at the MCLKfrequency on the
fallingedges ofMCLK, whilein non-delayed reverseframe synchr.mode voice data byteis shiftedin
at theMCLKfrequency onthe risingedges of MCLK.

CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other
system clocks.

via CI andCO pins.

on the rising edgesof CCLK.

Positive power supplyinput for the digital section.

CC

when CS- islow on the falling edges of CCLK.
Transmit Data ouput:Data is shifted out onthis pin during the assigned transmittime slots.

X

Elsewhere D
synchr. modes, voicedata byte is shifted out from TRISTATE output D

output is in the high impedance state. In delayed andnon-delayed normal frame

X

at the MCLKon the rising

X

edge of MCLK,while in non-delayed reverse frame synchr mode voice databyte is shiftedout on
the falling edge of MCLK.

frames. Any ofthree formats may be used for this signal: non delayed normal mode, delayed
mode, and non delayed reverse mode.

sequencing logic.Values mustbe 512 kHz,1.536MHz,2.048MHz or2.56MHzselected bymeansof
ControlRegisterCRO. MCLKis usedalso toshift-inandout data.

A logic 0 written intoDO (CR1) appears at LO pin as a logic1.

together close tothe device.

ST5092

3/29

ST5092

PIN FUNCTIONS(TQFP44)

Pin Name Description

1 N.C. Not Connected.

2,3 V

Fr+,VFr–

4 N.C. Not Connected.

5,6 V

Lr+,VLr–

7 N.C. Not Connected.
8 GNDP Power ground. V

9 N.C. Not Connected.

10 D

11,12,13 N.C. Not Connected.

14 CCLK Control Clock input: Thisclock shifts serial control information into CI and out from CO when the

15 CS- Chip Select input: Whenthis pin is low, controlinformation is written into and outfrom the ST5092
16 CI Control data Input: SerialControl information is shifted into theST5092 on this pin when CS- is low
17 BZ Pulse widthmodulated buzzer driver output.

18 V
19 CO Controldata Output: Serial control/statusinformation isshifted out from the ST5092 on this pin

20 D

21 GND Ground: All digital signalsare referenced to this pin.

22,23 N.C. Not Connected.

24 FS Frame Sync input: This signal is a 8kHz clock whichdefines thestart of the transmit andreceive

25 MCLK MasterClockInput:Thissignal isusedby theswitchedcapacitorfiltersandthe encoder/decoder

26 LO A logic 1 written intoDO (CR1) appears at LO pin as a logic 0

27,28,29 N.C. Not Connected.

30 MIC2- Secondnegativehigh impedance input to transmit pre-amplifier for microphoneconnection.
31 MIC2+ SecondPositivehigh impedance inputto transmitpre-amplifier for microphone connection.
32 N.C. Not Connected.
33 MIC1- Negativehigh impedanceinputto transmitpre-amplifier formicrophone connection.
34 MIC1+ Positivehighimpedance input to transmitpre-amplifier formicrophone connection.
35 N.C. Not Connected.
36 GNDA Analog Ground: All analogsignals arereferenced tothis pin.GND and GNDA must be connected

37 MIC3- Thirdnegative high impedance outputto transmitpreamplifier formicrophone connection.
38 MIC3+ Thirdpositive high impedance outputto transmit preamplifier for microphone connection.

39,40 N.C. Not Connected.

41 V
42 V

43,44 N.C. Not Connected.

Receive analog earpiece amplifier complementary outputs.Theseoutputscan drive directly earpiece
transductor. Thesignalat this output canbe the summof:

- Receive Speech signal from D

,

R

- Internal Tone Generator,

- Sidetone signal.

Receive analog extraamplifiercomplementary outputs. Thesignalat these outputs can bethesumof:

- Receive Speech signal from DR,

- Internal Tone generator,

- Sidetone signal.
and VLrdriver are referencedto thispin. GNDP and GND must be connected

Fr

together close tothe device.
Receive datainput: Datais shifted in during the assignedReceived time slots In delayed and non-

R

delayed normal frame synchr. modes voice data byte is shiftedin at the MCLK frequency onthe
falling edges of MCLK, while in non-delayed reverse frame sinchr. mode voice data byte isshifted
in at the MCLK frequency on the risingedges of MCLK.

CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other
system clocks.

via CI andCO pins.
on the rising edgesof CCLK.
Positive power supplyinput for the digital section.

CC

when CS- islow on the falling edges of CCLK.
Transmit Dataouput:Data isshiftedouton this pinduring theassignedtransmittimeslots.Elsewhere

X

D

outputis inthe high impendance state.Indelayed andnon-delayednormalframesynchr.modes,

X

voicedata byte isshiftedoutfromTRISTATEoutput D

attheMCLK onthe risingedgeof MCLK,while

X

innon-delayed reverse framesynchrmode voice databyteisshiftedouton thefallingedge ofMCLK.

frames. Either of threeformats may be used for this signal: non delayed normalmode, delayed
mode, and non delayed reverse mode.

sequencing logic.Values mustbe 512 kHz,1.536MHz,2.048MHz or2.56MHzselected bymeansof
ControlRegisterCRO. MCLKis usedalso toshift-inandoutdata.

A logic 0 written intoDO (CR1) appears at LO pin as a logic1.

together close tothe device.

Positive power supplyinput for the analog section.

CCA

V

and V

CC

Positive power supplyinput for the power section.V

CCP

must be direc t ly conn ec ted toget her.

CCA

and VCCmust be connected together.

CCP

4/29

ST5092

FUNCTIONAL DESCRIPTION

I DEVICEOPERATION
I.1 Poweron initialization:

When power is first applied, power on reset cir­cuitry initializes ST5092 and puts it into the power
down state.Gain ControlRegistersforthe various
programmable gain amplifiers and programmable
switches are initialized as indicated in theControl
Register description section. All CODEC functions
are disabled.
The desired selection for all programmable func­tions may be intialized prior to a power up com­mand using the MICROWIRE control channel.

I.2 Powerup/down control:

Following power-on initialization, power up and
power down controlmay be accomplishedby writ­ing any of the control instructions listed in Table 1
into ST5092with ”P”bit set to 0 for power up or 1
for power down.
Normally, it is recommended that all programma­ble functions be initially programmed while the
device is powered down. Power state control can
then be included with the last programming in­struction or in a separatesingle byte instruction.
Any of the programmable registers may also be
modified whileST5092 is powered up ordown by
setting ”P” bit as indicated. When power up or
down control is entered as a single byte instruc­tion, bit 1 must be set to a 0.
When a power up command is given, all de-acti­vated circuits are activated, but output D

will re-

X

main in the highimpedance state until the second
Fs pulse after power up.

I.3 Powerdown state:

Following a period of activity, power down state
may be reentered by writing a power down in­struction.
Control Registers remain in their currentstate and
can be changed by MICROWIRE control inter­face.
In addition to the power down instruction, detec­tion of loss MCLK (no transition detected) auto­matically entersthe device in ”reset” power down
state withD

I

.4 Transmit section:
Transmit analog interface is designed in two
stages to enable gains up to 42.5 dB to be real­ized. Stage 1 is a low noise differential amplifier
providing 20 dB gain. A microphone may be ca­pacitevely connected to MIC1+, MIC1- inputs,
while the MIC2+ MIC2– and MIC3+ MIC3- inputs
may be usedto capacitivelyconnect a secondmi­crophone or a thirdmicrophone respectivelyor an
auxiliary audio circuit. MIC1 or MIC2 or MC3 or
transmit mute is selected with bits 6 and 7 of reg­ister CR4.

outputin the high impedancestate.

X

In the mute case, the analog transmit signal is
grounded and the sidetone path is also disabled.
Following the first stage is a programmable gain
amplifier which provides from 0 to 22.5 dB of ad­ditional gain in 1.5dBstep.The total transmit gain
should be adjusted so that, at reference point A,
see Block Diagram description, the internal 0
dBm0 voltage is 0.49 Vrms (overload level is 0.7
Vrms). Second stage amplifier gain can be pro­grammedwith bits 4 to 7 ofCR5.
An active RC prefilter then precedesthe8th order
band pass switched capacitor filter. A/D converter
can be either a 14-bitlinear(bit CM= 0 in register
CR0) or can have a compressing characteristics
(bit CM = 1 in registerCR0) according to CCITT A
or MU255 coding laws. A precision on chip volt­age referenceensuresaccurate and highlystable
transmission levels.
Any offset voltage arisingin the gain-setamplifier,
the filtersor the comparator is cancelled by an in­ternalautozerocircuit.
Each encode cycle begins immediatly at the be­ginning of the selected Transmit time slot. The to­tal signal delay referenced to the start of the time
slot is approximatively195 µs (due to the transmit
filter) plus 125 µs (due to encoding delay), which
totals 320µs. Voicedata is shifted out on D

X

dur­ing the selected time slot on the transmit rising
edges of MCLK in delayedor non-delayednormal
mode or on the falling edges of MCLK in non-de­layed reversemode.

I.5 Receive section:

Voice Data is shifted into the decoder’s Receive
voice data Register via the D
lected time slot on the falling edges of MCLK in
delayed or non-delayed normal mode or on the
rising edges of MCLK in non-delayed reverse
mode.
The decoder consists of either a 14-bit linear or
an expanding DAC with A or MU255 law decod­ing characteristic. Following the Decoder is a
3400 Hz 8th order band-pass switched capacitor
filter withintegral Sin X/X correction for the 8 kHz
sampleand hold.
0 dBmO voltage at this (B) reference point (see
Block Diagram description) is 0.49 Vrms. A tran­scient suppressing circuitry ensure interference
noise suppressionat power up.
The analog speech signal output can be routed
eitherto earpiece (V
tra analog output (V

FR+,VFR-

,V

Lr+

bits OE and SE(1 and 0 of CR4).
Total signal delay is approximatively 190µs (filter
plus decoding delay) plus 62.5 µs (1/2 frame)
whichgives approximatively252 µs.
Differential outputs V

FR+,VFR-

rectly drive an earpiece. Preceding the outputs is
a programmableattenuationamplifier, which must

pin during the se-

R

outputs)or to an ex-

outputs) by setting

Lr-

are intended to di-

5/29

ST5092

be set bywriting to bits 4 to 7 in register CR6. At­tenuationsin the range 0 to -30 dB relativeto the
maximum level in 2 dB step can be programmed.
The input of this programmable amplifier is the
sum of several signals which can be selected by
writing to registerCR4.:

- Receive speech signal which has been de­codedand filtered,

- Internally generated tone signal, (Tone ampli­tudeis programmedwith bits4 to7 of register
CR7),

- Sidetonesignal, the amplitude of which is pro­grammedwithbits 0 to 3 ofregisterCR5

V

FR+

andV

outputsarecapableofdriving output

FR-

power level up to 66mW into differentially con­nectedload impedance of 30 Ω. Piezoceramicre­ceivers up to50nF can also be driven.

Differential outputs V

Lr+,VLr-

are intended to di­rectly drive anextra output. Preceding the outputs
is a programmable attenuation amplifier, which
must be set by writing to bits 0 to 3 in register
CR6. Attenuationsin the range 0 to -30 dB rela­tive to the maximum level in 2.0 dB step can be
programmed. The input ofthis programmable am­plifier can be the sumof signalswhich canbe se­lected by writingto register CR4:

- Receive speech signal which has been de­codedand filtered,

- Internally generated tone signal, (Tone ampli­tudeis programmedwith bits4 to7 of register
CR7),

- Sidetonesignal, the amplitude of which is pro­grammedwithbits 0 to 3 ofregisterCR5.

and V

V

Lr+

outputsare capableof drivingoutput

Lr-

power level up to 66mW into differentially con­nected loadimpedanceof 30 Ω. Piezoceramicre­ceivers up to50nF can also be driven.

Non delayed data mode is similar to long frame
timing on ST5080A: first time slot begins nomi­nally coincident with the rising edge of F

. Alter-

S

native is to use delayeddata mode, which is simi­lar to short frame sync timing on ST5080A, in
which F

input must be high at least a half cycle

S

of MCLK earlier the frame beginning. In the case
of companded code only (bit CM = 1 in register
CRO) a time slot assignment circuit on chip may
be used with all timing modes, allowing connec­tion to one of thetwo B1 and B2voice data chan­nels.
Two data formats are available: in Format 1, time
slot B1 corresponds to the 8 MCLK cycles follow­ing immediately the rising edge of FS, while time
slot B2 corresponds to the 8 MCLK cycles follow­ing immediately time slot B1.
In Format 2, time slot B1 is identical to Format 1.
Time slot B2 appears two bit slots after time slot
B1. This two bits space is left available for inser­tion of the D channel data.
Data format is selected by bit FF (2) in register
CR0. Time slot B1 or B2 is selected by bit TS (1)
in Control Register CR1.
Bit EN (2) in control register CR1 enables or dis­ables the voice data transfer on D

and DRas

X

appropriate. During the assigned time slot, D
output shifts data out from the voice data register
on the rising edges of MCLK in the case of de­layed and non-delayed normal modes or on the
falling edges of MCLK in the case of non-delayed
reverse mode. Serial voice data is shifted into D
input during the same time slot on the falling
edges of MCLK in the case of delayed and non­delayed normal modes or on the rising edges of
MCLK in thecaseof non-delayedreversemode.
D

is in the high impedance Tristate condition

X

when in thenon selected time slots.

X

R

BUZZER OUTPUT:
Single ended output BZ is intended to drive a
buzzer, via an external BJT, with a squarewave
pulse width modulated (PWM) signal the fre­quency of whichis storedinto registerCR8.
For some applicationsit is also possible to ampli­tude modulate this PWM signal with a square­wave signal having a frequency stored in register
CR9.
Maximum load for BZis 5kΩand 50pF.

I.6 DigitalInterface (Fig.1)

F

FrameSync inputdetermines the beginningof

S

frame. It may have any durationfrom a singlecy­cle of MCLK to a squarewave.Three different re­lationships may be established between the
Frame Sync input and the first time slot of frame
by setting bits DM1 and DM0 in register CR1.

6/29

I.7 Control Interface:

Control information or data is written into or read­back from ST5092via the serial control port con­sisting of control clock CCLK, serial data input CI
and output CO, and Chip Select input, CS-. All
controlinstructions require 2 bytes as listedin Ta­ble 1, with the exception of a single byte power­up/down command.
To shift control data into ST5092, CCLK must be
pulsed high 8 times while CS- is low. Data on CI
input is shifted into the serial input register on the
rising edge of each CCLK pulse. After all data is
shifted in, the contentof the input shift register is
decoded, and may indicate that a 2nd byte of
control data will follow. This second byte may
either be defined by a second byte-wide CS­pulse or may follow the first contiguously, i.e. it is
not mandatory for CS- to return high in between
the first and second control bytes. At the end of
the 2nd control byte, data is loaded into the ap-

Figure 1: DigitalInterface Format (*)

FORMAT 1

(delayed timing)F5

ST5092

F6

MCLK

DR

DX

F9

MCLK

DR

DX

FORMAT 2

(non delayed timing)

XB2B1 XX

B2B1

(delayed timing)F8

(non delayed timing)

XB2B1 XX

B2B1

D93TL075

(*) Significant Only For CompandedCode.

propriate programmable register. CS- mustreturn
high atthe end of the 2nd byte.
To read-backstatus informationfrom ST5092,the
first byte of the appropriate instruction is strobed
in during the first CS- pulse, as defined in Table

1. CS- must be set low for a further 8 CCLK cy­cles, during which data is shifted out of the CO
pin onthe falling edges of CCLK.
When CS- is high, CO pin is in the high imped­ance Tri-state, enabling CO pins of several de­vices to be multiplexedtogether.
Thus, to summarise,2 byte READ and WRITEin­structions may use either two 8-bit wide CS­pulses or a single 16 bit wide CS- pulse.

I

.8 Control channel access to PCMinterface:

It is possible to access the B channel previously

selected in Register CR1 in the case of com­pandedcode only.
A byte written into Control Register CR3 will be
automatically transmitted from D

output in the

X

followingframein placeof the transmitPCM data.
A byte written into Control Register CR2 will be
automatically sent through the receive path to the
Receiveamplifiers.
In order to implement a continuousdata flow from
the Control MICROWIRE interface to a B chan­nel, it is necessary to send the control byte on
each PCM frame.
A current byte received on D

input can be read

R

in the register CR2. In order to implement a con­tinuous data flow from a B channel to MI­CROWIREinterface,it is necessary to read regis­ter CR2 at eachPCM frame.

7/29

ST5092

II

PROGRAMMABLE FUNCTIONS

For both formats of Digital Interface, programma­ble functions are configured by writing to a num­ber ofregistersusing a 2-byte write cycle.

verification. Byte one is always register address,
while byte two is Data.
Table 1 lists the register set and their respective
adresses.

Most of these registers can also be read-back for

Table 1: ProgrammableRegisterIntructions

Function Address byte

76543210
Single byte Power up/down P X X X X X 0 X none
Write CR0 P 0 00001XseeCR0TABLE 2
Read-back CR0 P 0 00011XseeCR0
Write CR1 P 0 00101XseeCR1TABLE 3
Read-back CR1 P 0 00111XseeCR1
Write Data toreceive path P 0 01001XseeCR2TABLE 4
Read datafromD
Write Data toD
Write CR4 P 0 10001XseeCR4TABLE 6
Read-back CR4 P 0 10011XseeCR4
Write CR5 P 0 10101XseeCR5TABLE 7
Read-back CR5 P 0 10111XseeCR5
Write CR6 P 0 11001XseeCR6TABLE 8
Read-back CR6 P 0 11011XseeCR6
Write CR7 P 0 11101XseeCR7TABLE 9
Read-back CR7 P 0 11111XseeCR7
Write CR8 P 1 00001XseeCR8TABLE 10
Read-back CR8 P 1 00011XseeCR8
Write CR9 P 1 00101XseeCR9TABLE 11
Read-back CR9 P 1 00111XseeCR9
Write CR10 P 1 01001XseeCR10 TABLE12
Read-back CR10 P 1 01011XseeCR10
Write CR11 P 1 01101XseeCR11 TABLE13
Read-back CR11 P 1 01111XseeCR11
Write Test RegisterCR14 P 1 11001Xreserved

R

X

P001011XseeCR2
P001101XseeCR3TABLE 5

Data byte

NOTE 1: bit 7 of the address byte and data byte is alwaysthe firstbit clocked intoor out from:CI andCO pins when MICROWIREserial

NOTE 2: ”P” bit is Power up/down Control bit.P = 1 Means Power Down.

NOTE 3: Bit 2 is write/read select bit.
NOTE 4: Registers CR12, CR13, and CR15 are not accessible.

8/29

port is enabled.
X = reserved: write 0

Bit 1 indicates,if set, the presence ofa secondbyte.

Table 2: ControlRegisterCR0Functions

ST5092

76543210

F1 F0 CM MA IA FF B7 DL

0

0

1

0

0

1

1

1

0
1

0

0

1

0

0

1

1

1

0
1

0
1

*: state at power on initialization
(1): significant in compandedmode only

MCLK = 512 kHz
MCLK = 1.536 MHz
MCLK = 2.048 MHz
MCLK = 2.560 MHz

Linear code
Companded code

Linear Code Companded Code

2-complement *
sign and magnitude
2-complement
1-complement

B1 and B2 consecutive
B1 and B2 separated

8 bits time-slot
7 bits time-slot

01Normal operation

Digital Loop-back

Function

*

*

MU-law: CCITT D3-D4 *
MU-law: Bare Coding
A-law including even bit inversion
A-law:Bare Coding

* (1)

(1)

* (1)

(1)

*

Table 3: Control Register CR1 Functions

76543210

DM1 DM0 DO MR MX EN TS

0

X

1

0

1

1

0
1

0
1

0
1

0
1

0
1

*: state at power on initialization
(1):

X:

significant in companded mode only
reserved: write 0

delayed data timing
non-delayed normal datatiming
non-delayed reverse datatiming

L0 latch set to 1
L0 latch set to 0

D

connected to rec.path

R

CR2 connected torec. path
Trans path connected to D

CR3 connected toD

X

voice data transferdisable
voice data transferenable

B1 channel selected
B2 channel selected

X

Function

X

*

*

*

(1)

*

(1)

*

* (1)

(1)

9/29

ST5092

Table 4: ControlRegisterCR2 Functions

76543210

d7 d6 d5 d4 d3 d2 d1 d0

Function

msb lsb Data sent to Receivepath or Data received fromD

(1) Significant in companded mode only.

Table 5: ControlRegisters CR3 Functions

76543210

d7 d6 d5 d4 d3 d2 d1 d0

msb lsb D

(1) Significant in companded mode only

data transmitted (1)

X

Function

Table 6: ControlRegister CR4 Functions

76543210

VS TE SI OE1 OE2 RTE HPB SE

0

0

1

0

0

1

1

1

0
1

0

0

1

0

0

1

1

1

0
1

0
1

01Receive Signal to V

Transmit input muted
MIC1 Selected
MIC2 Selected
MIC3 Selected

Internal sidetone disabled
Internal sidetone enabled

Receive output muted
VFr output selected
VLr outputselected
NOT ALLOWED

Ring /Tone to V
Ring /Tone to V

or VLrdisabled

Fr

or VLrenabled

Fr

Receive HP filter enabled
Receive HP filter disabled

Receive Signal to V

Fr
Fr

Function

or VLrdisabled
or VLrenabled

input (1)

R

*

*

*

*

*

*

*: state at power on initialization
X: reserved: write 0

10/29

Table 7: ControlRegisterCR5Functions

ST5092

76543210

Transmit amplifier Sidetone amplifier

0

0

0

-

­1

1

*: state at power oninitialization

1

0

-

­1

1

0

0

0
0

-

1

0

0

-

­1

1

0

0

0

Table 8: ControlRegisterCR6Functions

76543210

Earpiece ampifier

[EARA]

0

0

0
0

-

1

*: state at power oninitialization

0

0

-

­1

1

Extra amplifier [EXTA]

0
1

-

1

0

0

0

0

-

­1

1

0
0

-

1

0 dB gain

1.5 dB gain
in 1.5 dBstep

22.5 dBgain

-12.5 dB gain

0

-13.5 dB gain

1

in 1 dB step

-

-27.5 dB gain

1

0 dB gain

-2 dBgain
in 2 dB step

-30 dB gain

0 dB gain

0

-2 dBgain

1

in 2 dB step

-

-30 dB gain

1

Function

*

*

Function

*

*

Table 9: ControlRegisterCR7Functions

7 6 5 4 3 2 1 0 Function

Tone gain F1 F2 SN DE Attenuation f1 V

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

X

1

X

1

1

0

0

1

1

1

0

0

1

0

0

1

1

1

0

X

1

X

0

0

1

0

0

1

1

1

0

0

0

0
1

*: state at power on initialization
(2): value provided iff1or f2 is selected alone.

X reserved: write 0

if f1and f2are selected in the summedmode, f1=0.89V

01Normal operation

....0dB*

-3dB

-6dB

-9dB

-12 dB

-15 dB

-18 dB

-21 dB

-24 dB

-27 dB

f1 andf2 muted
f2 selected
f1 selected
f1 andf2 in summed mode

Squarewave signalselected
Sinewave signalselected

Tone / Ring Generator connected to
Transmit path

whilef2=0.7 Vpp.

pp

pp

...1.6(2)

0.066

f2 V

pp

1.26(2)

0.053
*

*

*

11/29

ST5092

Table 10: ControlRegister CR8 Functions

76543210

f17 f16 f15 f14 f13 f12 f11 f10

msb lsb Binary equivalent of the decimal numberused to calculate f1

Function

Table 11: ControlRegister CR9Functions

76543210

f27 f26 f25 f24 f23 f22 f21 f20

msb lsb Binary equivalent of the decimal numberused to calculate f2

Function

Table 12: ControlRegister CR10 Functions

76543210

DFT HFT

XXXXXX

0
0
1
1

(*) Default values insertedinto theRegister at Power On.

(*) Standard Frequency Tone Range

0

Halved Frequency Tone Range

1

Doubled FrequencyTone Range

0

Forbidden

1

Function

X reserved, write 0.

Table 13: ControlRegister CR11Functions

76543210

BE BI BZ5 BZ4 BZ3 BZ2 BZ1 BZ0

0
1

0
1

msb lsb Binary equivalent of the decimal numberused to calculate the

* state at power on initialization

12/29

Function

Buzzer outputdisabled (set to 0) *
Buzzer outputenabled

Duty Cycle is intended as therelative width of logic 1 *
Duty cycle is intended as the relativewidth of logic 0

duty cycle.

ST5092

CONTROLREGISTERCR0

First byte of a READ or a WRITE instruction to
Control Register CR0 is as shown in TABLE 1.
Secondbyte is asshown in TABLE2.

MasterClock Frequency Selection

A master clock must be provided to ST5092 for
operation of filterand coding/decodingfunctions.
MCLK frequency can be either 512 kHz, 1.536
MHz, 2.048 MHz or 2.56 MHz.
Bit F1 (7) and F0 (6) must be set during initializa­tion to selectthe correct internal divider.
Default value is 512 kHz.
Any clock different from the default one must be
selected prior a Power-Upinstruction.

Coding Law Selection

Bits MA (4) and IA (3) permit selection of Mu-255
law or A law coding with or without even bit inver­sion if companded code (bit CM = 1) is selected.
Bits MA(4) and IA(3) permit selection of 2-com­plement, 1-complement or sign and magnitude if
linear code (bit CM= 0) is selected.

Coding Selection

Bit CM(5) permitsselectioneither of linear coding
(14-bit) or companded coding (8-bit). Default
value islinear coding.

Digital Interface format(1)

Bit FF(2) = 0 selects digital interface in Format 1
where B1 and B2 channelare consecutive.FF=1
selects Format 2 where B1 and B2 channel are
separated by two bits. (See digital interface for­mat section.)

56+8 selection (1)

Bit ’B7’ (1) selects capability for ST5092 to take
into account only the seven most significant bits
of the PCM data byte selected.
When ’B7’ is set, the LSBbit on D
LSB bit on D

is highimpedance. This function al-

X

is ignoredand

R

lows connection of an external ”in band” data
generator directly connected on the Digital Inter­face.

Digitalloopback

Digital loopback mode is entered by setting DL
bit(0) equal 1.
In Digital Loopback mode, data written into Re­ceive PCM Data Register from the selected re­ceivedtime-slot is read-back from thatRegister in
the selectedtransmit time-sloton D

.

X

No PCMdecoding or encoding takes place in this
mode. Transmit and Receive amplifier stages are
muted.

CONTROLREGISTER CR1

First byte of a READ or a WRITE instruction to
Control Register CR1 is as shown in TABLE 1.
Secondbyteis asshownin TABLE 3.

DigitalInterfaceTiming

Bit DM1(7) = 0 selects digital interfacein delayed
timing mode, while DM1 = 1 and DM0 = 0 selects
non-delayed normal data timing mode, and DM1
= 1 and DM0 = 1 selects non-delayed reverse
data timingmode.
Defaultis delayeddata timing.

Latchoutput control

Bit DO controls directly logical statusof latch out­put LO: ie, a ”ZERO” written in bit DO puts the
output LO at logical1, while a ”ONE” written in bit
DOsets the outputLO to zero.

Microwire access to B channel on receive
path (1)

Bit MR (4) selects access from MICROWIRE
Register CR2 to Receive path. When bit MR is
set high, data written to register CR2 is decoded
each frame, sent to the receive path and data in­put at D

isignored.

R

In the other direction, current PCM data input re­ceivedat D

can be read from register CR2 each

R

frame.

Microwire access to B channel on transmit
path (1)

Bit MX (3)selects access from MICROWIRE write
only Register CR3 to D
set high, datawritten to CR3is output at D

output. When bit MX is

X

X

every

frameand the outputof PCM encoder is ignored.

(1) Significant in companded mode only

Mu 255 law

msb lsb msb lsb msb lsb

Vin = + fullscale 1 0 0000001010101011111111
Vin = 0V
Vin = - fullscale 0 0 0000000010101001111111

MSB is always the first PCMbit shifted in or out of: ST5092.

10111111111111111011001100110011100000000000000

True A law even bit

inversion

A law without even bit

inversion

13/29

0

ST5092

Transmit/Receiveenabling/disabling

Bit ’EN’ (2) enables or disables voice data trans­feronD

and DRpins.When disabled, PCM data

X

from DR is not decoded and PCM time-slots are
high impedanceon D

. Default value is disabled.

X

B-channel selection(1)

Bit TS(1) permits selection between B1 or B2
channels.Default value is B1 channel.

CONTROLREGISTERCR2 (1)

Data sent to receive path or data received from

input. Refer to bit MR(4) in ”Control Register

D

R

CR1” paragraph.

CONTROLREGISTERCR3 (1)

data transmitted. Refer to bit MX(3) in ”Control

D

X

Register CR1” paragraph.

CONTROLREGISTERCR4

First byte of a READ or a WRITE instruction to
Control Register CR4 is as shown in TABLE 1.
Secondbyte is asshown in TABLE6.

TransmitInputSelection

MIC1 or MIC2 or MIC3 or transmit mute can be
selected withbits 6 and 7 (V

and TE).

S

Transmit gain can be adjusted within a 22.5 dB
range in 1.5 dB stepwith RegisterCR5.

SidetoneSelection

Bit ”SI” (5) enables or disables Sidetone circuitry.
When enabled, sidetone gain can be adjusted
with Register (CR5). When Transmit path is dis­abled, sidetonecircuit is alsodisabled.

Output Driver Selection

Bits OE1(4) and OE2(3) provide the selection
among the earpiece output or the extra amplifier
output orboth outputsmuted.
OE1 = 1 and OE2 =1 isnotallowed.

Ring/Tone signal selection

Bit RTE (2) provide select capability to connect
on-chip Ring/Tone generator either to an extra
amplifier input or to earpieceamplifierinput.

PCM receive data selection

Bits ”SE” (0) provide select capability to connect
receivedspeechsignal either to an extra amplifier
input or to earpieceamplifierinput.

CONTROLREGISTER CR5

First byte of a READ or a WRITE instuction to
Control Register CR5 is as shown in TABLE 1.
Secondbyteis asshownin TABLE 7.

Transmitgain selection

Transmit amplifier can be programmed for a gain
from0dB to 22.5dBin 1.5dB step with bits 4 to 7.
0 dBmO level at the output of the transmit ampli­fier (A reference point) is 0.492 Vrms (overload
voltageis 0.707 Vrms).

Sidetoneattenuation selection

Transmit signal picked up after the switched ca­pacitor low pass filter may be fed back into both
Receiveamplifiers.
Attenuation of the signal at the output of the
sidetone attenuator can be programmed from
–12.5dBto -27.5d B relative to reference poin t
A in 1 dB step with bits 0 to 3.

CONTROLREGISTER CR6

First byte of a READ or a WRITE instruction to
Control Register CR6 is as shown in TABLE 1.
Secondbyteis asshownin TABLE 8.

Earpieceamplifiergain selection:

Earpiece Receive gain can be programmed in 2
dB step from 0 dB to -30 dB relative to the maxi­mum with bits 4 to 7.
0 dBmO voltageat the output of the amplifier on
pins V

Fr+

andV

is then 1.965 Vrms when 0dB

Fr-

gain is selected down to 61.85 Vrms when -30dB
gain is selected.

Extraamplifiergainselection:

Extra Receive amplifier gain can be programmed
in 2 dB step from 0 dB to -30 dB relative to the
maximumwithbits 0 to 3.
0 dBmO voltage on the output of the amplifier on
pins V

Lr+

and V

1.965 Vrms when 0 dB gain is

Lr-

selected down to 61.85 mVrms when -30 dB gain
is selected.

Receive High PassFilter Selection

Bit HPB (1) provide the selection of the receive
high passfilter cutoff frequency.

(1) Significant in companded mode only

14/29

CONTROLREGISTER CR7:

First byte of a READ or a WRITE instruction to
Control Register CR7 is as shown in TABLE 1.
Secondbyteis asshownin TABLE 9.

ST5092

Tone/Ring amplifiergain selection

Output level of Ring/Tone generator, before at­tenuation by programmableattenuatoris 1.6 Vpk­pk when f1 generator is selected alone or
summed with the f2 generator and 1.26 Vpk-pk
when f2generatoris selectedalone.
Selected output level can be attenuated down to

-27 dB by programmable attenutator by setting
bits 4 to 7.

Frequency mode selection

Bits ’F1’ (3) and ’F2’ (2) permit selection of f1
and/or f2 frequency generator according to TA­BLE 9.
When f1 (or f2) is selected, output of the
Ring/Toneis a squarewave(or a sinewave) signal
at the frequency selected in the CR8 (or CR9)
Register.
When f1 and f2 are selected in summed mode,
output of the Ring/Tone generator is a signal
where f1 and f2 frequencyare summed.
In order to meet DTMF specifications, f2 output
level is attenuatedby 2dB relative to the f1 output
level.
Frequencytemporization must be controlled by the
microcontroller.

Waveformselection

Bit ’SN’ (1) selects waveform of the output of the
Ring/Tone generator. Sinewave or squarewave
signal can beselected.

DTMF selection

Bit DE(0) permits connection of Ring/Tone/DTMF
generator on the Transmit Data path instead of
the Transmit Amplifier output. Earpiece or extra
receive output feed-back may be provided by
sidetone circuitry by setting bit SI or directly by
setting bit RTE in Register CR4. Loudspeaker
feed-back may be provided directly by setting bit
RTL inRegisterCR4.

CONTROLREGISTERSCR8 ANDCR9

First byte of a READ or a WRITE instruction to
Control Register CR8 or CR9 is as shown in TA­BLE 1. Second byte is respectively as shown in
TABLE 10 and11.
If ”standard frequency tone range” is selected,
Tone or Ringsignal frequency value is definedby
the formula:

f1 = CR8/ 0.128 Hz

and

f2 = CR9/ 0.128 Hz

where CR8 and CR9 are decimal equivalents of
the binary values of the CR8 and CR9 registers

respectively.Thus, anyfrequencybetween 7.8 Hz
and 1992 Hzmaybe selected in 7.8 Hz step.
If ”halved frequencytone range”isselected, Tone
or Ring signal frequency value is defined by the
formula:

f1 = CR8/ 0.256Hz

and

f2 = CR9/ 0.256Hz
This any frequency between 3.9Hz and 996Hz
may be selectedin 3.9Hzstep.
If ”doubled frequency tone range”is selected,
Tone or Ring signal frequencyvalue is defined by
the formula:

f1 = CR8/ 0.064Hz
and

f2 = CR9/ 0.064Hz
Thus any frequencybetween 15.6Hz and 3984Hz
may be selectedin 15.6Hzstep.

TABLE 12 gives examples for the main frequen­cies usual for Tone or Ring generation.

CONTROLREGISTER CR10

Bit DFT(1) and HFT(0) permits the selection
among ”standard frequencytone range” (i.e. from

7.8Hz to 1992Hz in 7.8Hz step), ”halved fre­quency tone range” (i.e. from 3.9Hz to 996Hz in

3.9Hz step), and ”doubled frequency tone range”
(i.e. from 15.6Hz to 3984Hz in 15.6Hz step) ac­cording to the values described in CONTROL
REGISTERCR8 and CR9.

CONTROLREGISTERCR11
Bit BE(7) permits connection of a f1 squarewave
PWM Ring signal, amplitude modulated or not by
a f2 squarewave signal, to buzzer driver output
BZ. Bits BZ5 to BZ0 define the duty cycle of the
PWM squarewave,accordingto the following for­mula:

DutyCycle = CR11(5÷0) x0.78125%

where CR11(5÷0) is the decimal equivalent of
the binary value BZ5÷BZ0.

When BE = 1, if bits F1 = 1 and F2 = 0 in regis­ter CR7, a f1 PWM ring signal is present at the
buzzer output, while if bits F1 = 1 and F2 = 1 in
register CR7 the f1 PWM ring signal is also am­plitude modulated by a f2 squarewave fre­quency. Bit BI (6) allows to chose the logic level
at which the duty cycle is referred: BI = 0 means
that duty cycle is intended as the relative width
of the logic1, while BI = 1 means that duty cycle
is intended as the relative width of the logic 0.
When BE = 0 (or during power down) BZ = 0 if
BI = 0 or BZ = 1 if BI = 1.

15/29

ST5092

Table 12:

Tone 250 Hz
Tone 330 Hz
Tone 425 Hz
Tone 440 Hz
Tone 800 Hz
Tone 1330 Hz

DTMF 697 Hz
DTMF 770 Hz
DTMF 852 Hz
DTMF 941 Hz
DTMF 1209 Hz
DTMF 1336 Hz
DTMF 1477 Hz
DTMF 1633 Hz

SOL
LA
SI
DO
RE
MI flat
MI
FA
FA sharp
SOL
SOL sharp
LA
SI
DO
RE
MI

Examplesof Usual FrequencySelection (Standardfrequencytone range)

Description f1 value (decimal) Theoreticvalue (Hz) Typical value (Hz) Error %

32
42
54

56
102
170

89

99
109
120
155
171
189
209

50

56

63

67

75

80

84

89

95
100
106
113
126
134
150
169

250
330
425
440
800

1330

697
770
852

941
1209
1336
1477
1633

392

440

494

523.25

587.33

622.25

659.25

698.5
740
784

830.6
880

987.8

1046.5

1174.66

1318.5

250

328.2

421.9

437.5

796.9

1328.1

695.3

773.4

851.6

937.5

1210.9

1335.9

1476.6

1632.8

390.6

437.5

492.2

523.5

586.0

625.0

656.3

695.3

742.2

781.3

828.2

882.9

984.4

1046.9

1171.9

1320.4

.00
–.56
–.73
–.56
–.39
–.14

–.24
+.44
–.05
–.37
+.16
–.01

.00

.00
–.30

–.56
–.34
+.04
–.23
+.45
–.45
–.45
+.30
–.34
–.29
+.33
–.34
+.04
–.23
+.14

16/29

TIMING DIAGRAM
Non DelayedData TimingMode (Normal) (*)

ST5092

Delayed Data Timing Mode (*)

16

16

17

16

16

17

(*) In the case of compandedcode the timing is appliedto 8 bits instead of 16 bits(see ST5080A data sheet)

16

16

17/29

ST5092

TIMING DIAGRAM (continued)
Non DelayedReverse Data Timing Mode(*)

MCLK

FS

DX

DR

tHMFR

12345671617

tHMFRtSFMR

tDFD

tDMDR

1234567 16

tSDM tHMDR

1234567 16

tRM tFM tWMM

(*) In the case of compandedcode the timing is appliedto 8 bits instead of 16 bits.

tWML

tDMZR

D93TL076A

Serial Control Timing (MICROWIREMODE)

18/29

ABSOLUTE MAXIMUM RATINGS

Parameter Value Unit

to GND 5.5 V

V

CC

Voltage at MIC(V
Current at V

Fr

≤ 3.6V) VCC+1 to GND -1 V

CC

and V

Lr

+ 100 mA
Current at anydigital output + 50 mA
Voltage at any digital input (V

3.6V); limited at + 50mA V

≤

CC

+ 1 to GND - 1 V

CC

Storage temperature range - 65 to + 150 °C
Lead Temperature (wave soldering,10s) + 260 °C

TIMINGSPECIFICATIONS(unles sotherwi s especifi ed,VCC=2.7Vto3.6V ,TA=–30°Cto 85°C;
typical characteristicsare specifiedV

= 3.0V,TA=25°C;

CC

all signalsare referencedto GND,see Note 5 for timing definitions)
NOTICE:All timingspecifications can be changed.

MASTERCLOCK TIMING

Symbol Parameter Test Condition Min. Typ. Max. Unit

f

MCLK

t

WMH

t

WML

t

t

RM
FM

Frequency of MCLK Selection offrequency is

programmable (seetable 2)

Period of MCLK high Measured from VIHto V
Period of MCLK low Measured from VILto V
Rise Time ofMCLK Measured from VILto V
Fall Timeof MCLK Measured from VIHto V

IH
IL
IH

IL

80 ns
80 ns

512

1.536

2.048

2.560

30 ns
30 ns

ST5092

kHz
MHz
MHz
MHz

PCM INTERFACE TIMING

Symbol Parameter Test Condition Min. Typ. Max. Unit

t

HMF

t

SFM

t

DMD

t

DMZ

t

DFD

t

SDM

t

HMD

t

HMFR

t

SFMR

t

DMDR

t

DMZR

t

HMDR

Hold Time MCLK low to FS low 0 ns
Setup Time, FShigh to MCLK

30 ns

low
Delay Time, MCLK high to data

Load = 100 pf 100 ns

valid
Delay Time, MCLK low to DX

10 100 ns

disabled
Delay Time, FS high to data valid Load = 100 pf ;

100 ns
Applies only if FS rises later
than MCLK risingedge in Non
Delayed Mode only

Setup Time, DRvalid toMCLK

20 ns

receive edge
Hold Time, MCLK low to D

R

10 ns

invalid
Hold Time MCLK High to FS low 30 ns
Setup Time,FShighto MCLKHigh 30 ns
DelayTime,MCLK lowtodatavalid Load = 100pF 100 ns
Delay Time, MCLK High to DX

10 100 ns

disabled
Hold Time, MCLK High to D

R

20 ns

invalid

19/29

ST5092

SERIAL CONTROLPORT TIMING

Symbol Parameter Test Condition Min. Typ. Max. Unit

f

CCLK

t

WCH

t

WCL

t

RC

t

FC

t

HCS

t

SSC

t

SDC

t

HCD

t

DCD

t

DSD

t

DDZ

t

HSC

t

SCS

Note 5: A signal is valid if it is above VIHor below VILand invalid if itisbetween VILandVIH.

Frequency of CCLK 2.048 MHz
Period of CCLK high Measuredfrom VIHto V
Period of CCLK low Measured from VILto V
Rise Time ofCCLK Measured from VILto V
Fall Timeof CCLK Measured from VIHto V

IH
IL
IH

IL

160 ns
160 ns

50 ns

50 ns
HoldTime, CCLKhigh to CS–low 10 ns
Setup Time,CS–lowtoCCLKhigh 50 ns
SetupTime,CIvalid to CCLKhigh 50 ns
HoldTime,CCLKhigh to CI invalid 50 ns
Delay Time, CCLK lowto CO

Load = 100 pF 80 ns

data valid
Delay Time, CS–lowto CO data

50 ns
valid

DelayTimeCS–high or 8thCCLK

10 80 ns
low toCO highimpedance
whichever comes first

Hold Time, 8thCCLK high to

100 ns

CS– high
SetupTime,CS–high toCCLKhigh 100 ns

For the purpoesof this specification the following conditions apply:
a) All inputsignal are defined as: V
b) Delay times are measured from the inputs signal valid to the output signal valid.
c) Setuptimes aremeasured from the data input valid to the clock input invalid.
d) Hold times are measured fromthe clock signal valid to the data input invalid.

= 0.2VCC,VIH= 0.8VCC,tR< 10ns, tF< 10ns.

IL

ELECTRICAL CHARACTERISTICS (unlessotherw i s e specified,VCC= 2.7V to 3.6V,TA=–-30°Cto85°C;
typicalcharacteristicarespecifiedatV

=3.0V,TA=25°C; allsignalsarerefer enc edtoGND)

CC

DIGITAL INTERFACES

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

I

OZ

Input Low Voltage All digital inputs DC

AC

Input High Voltage All digitalinputs DCAC0.7V

0.8V

Output Low Voltage Alldigitaloutputs,IL=10µA

Alldigitaloutputs,I

Output High Voltage All digital outputs, IL=10µA

Alldigitaloutputs,I

Input Low Current Any digitalinput,

GND < V

IN<VIL

Input High Current Any digital input,

V

IH<VIN<VCC

Output Current in High

DXand CO -10 10 µA

=2mA

L

=2mA

L

V

CC

V

CC

-10 10 µA

-10 10

CC
CC

-0.1

-0.4

0.3V

0.2V

0.1

0.4

CC
CC

V
V

V
V

V
V

V
V

A

µ

impedance (Tri-state)

A.C. TESTING INPUT,OUTPUTWAVEFORM

INTPUT/OUTPUT

0.8VCC

0.2VCC

0.7VCC

0.3VCC

TEST POINTS

0.7VCC

0.3VCC

D93TL077

AC Testing: inputs aredriven at 0.8VCCfor
a logic ”1”and0.2VCC for a logic ”0”.
Timing measurements are made at 0.7V

CC

for a logic”1”and 0.3VCCfor a logic”0”.

20/29

ANALOGINTERFACES

Symbol Parameter Test Condition Min. Typ. Max. Unit

I

MIC

R

MIC

R

LVFr

C

LVFr

R

OVFr0

V

OSVFr0

R

LvLr

C

LvLr

R

OLVrO

V

OSVLrO

(*) See application note for VFrand VLrconnections.

Input Leakage GND < V
Input Resistance GND < V
Load Resistance (*) V
Load Capacitance (*) From V
Output Resistance Steady zero PCM code applied

Differential offset:
Voltage at V

Fr+,VFr-

Load Resistance (*) V
Load Capacitance (*) from V
Output Resistance Steady zero PCM code applied

Differential offset Voltage at
V

Lr+,VLr-

MIC<VCC
MIC<VCC

to V

Fr+

Fr-

to V

Fr+

Fr-

to DR; I= + 1mA
Alternating + zero PCM code

applied to DR maximum
receive gain; R

to V

Lr+

Lr-

Lr+

to V

Lr-

= 100

L

Ω

to DR; I+ 1mA
Alternating + zero PCM code

applied to DR maximum
receive gain; R

=50Ω

L

-100 +100 µA
50 kΩ
30 Ω

50 nF

1.0

-100 +100 mV

30 Ω

50 nF

1 Ω

–100 +100 mV

ST5092

Ω

POWERDISSIPATION

Symbol Parameter Test Condition Min. Typ. Max. Unit

I

CC0

I

CC1

Powerdown Current CCLK,CI = 0.1V;CS = VCC-0.1V 0.5 5 µA
Power Up Current V

Lr+,VLr-

and V

Fr+,VFr-

not

58mA

loaded

TRANSMISSION CHARACTERISTICS ( unless oth erwise spe cified, VCC=2.7Vto3.6V,TA=
–30°Cto85°C; typical characteristics are specified at V
= 0dBm0

, D

= –6dBm0 PCM code, f = 1015.625 Hz; all signal are referenced to GND)

R

=3.0V,TA=25°C, MIC1/2/3

CC

AMPLITUDERESPONSE(Maximum, Nominal,and Minimum Levels)
Transmit path - Absolutelevels at MIC1 / MIC2/ MIC3

Parameter Test Condition Min. Typ. Max. Unit

0 dBm0level Transmit Amps connected for

20dB gain
Overload level 70.71 mV
0 dBm0level Transmit Amps connected for

42.5dB gain

Overload level 5.302 mV

49.26 mV

3.694 mV

RMS

RMS
RMS

RMS

21/29

ST5092

TRANSMISSIONCHARACTERISTICS
AMPLITUDERESPONSE

(Maximum, Nominal, and Minimum Levels)

Receivepath - Absolutelevels at V

(continued)

(Differentiallymeasured)

FR

Parameter Test Condition Min. Typ. Max. Unit

0 dBM0level Receive Amp programmed for

1.965 V

RMS

0dB gain
0 dBM0level Receive Amp programmed for

61.85 mV

RMS

- 30dB attenuation

AMPLITUDERESPONSE(Maximum, Nominal,and Minimum Levels)
Receivepath - Absolutelevels at V

Parameter Test Condition Min. Typ. Max. Unit

0 dBM0level Receive Amp programmed for

0 dBM0level Receive Amp programmed for

(Differentiallymeasured)

Lr

0dB gain

- 30dB gain

1.965 V

61.85 mV

RMS

RMS

AMPLITUDERESPONSE

Transmit path

Symbol Parameter Test Condition Min. Typ. Max. Unit

G

XA

Transmit Gain Absolute
Accuracy

G

XAG

Transmit Gain Variation with
programmed gain

G

XAT

Transmit Gain Variation with
temperature

G

XAV

Transmit Gain Variation with
supply

G

XAF

Transmit Gain Variation with
frequency

G

XAL

Transmit Gain Variation with
signal level

(*) The limitat frequencies between 4600Hz and 8000Hzlies on astraight lineconnecting the twofrequencies on a linear (dB) scaleversus log
(Hz) scale.

Transmit Gain Programmedfor

minimum.

Measure deviation of Digital

PCM Code fromideal 0dB

PCM code atD

X

m0

Measure Transmit Gainover

the range fromMaximum to

minimum setting.

Calculate the deviation from

the programmed gainrelative

to GXA,

i.e. G

AXG=Gactual-Gprog.-GXA

Measured relative to GXA.

min. gain < G

Measured relative to G

< Max. gain

X

XA

GX= Minimum gain

Relative to 1015,625Hz,

multitone test techniqueused.

min. gain < G

< Max. gain

X

f = 60Hz

f = 100Hz

f = 200Hz

f = 300Hz

f = 400Hz to 3000 Hz

f = 3400Hz

f = 4000Hz

f = 4600Hz (*)

f = 8000Hz (*)

Sinusoidal Test method.

Reference Level = -10 dBm0

V

= -40 dBm0 to +3 dBm0

MIC

V

= -50 dBm0 to -40 dBm0

MIC

V

= -55 dBm0 to -50 dBm0

MIC

-0.5 0.5 dB

-0.5 0.5 dB

-0.1 0.1 dB

-0.1 0.1 dB

dB
dB
dB
dB
dB
dB
dB
dB
dB

dB
dB
dB

-1.5

-0.5

-1.5

-0.5

-0.5

-1.2

-30

-20

-6

0.5

0.5

0.0

-14

-35

-47

0.5

0.5

1.2

22/29

AMPLITUDERESPONSE

Receivepath

Symbol Parameter Test Condition Min. Typ. Max. Unit

G

G

G

G

G

G

G

G

G

RAE

RAL

RAGE

RAGL

RAT

RAV

RAF

RAL E

RAL L

Receive GainAbsolute Accuracy Receive gain programmed for

maximum

Apply -6 dB

Measure V

PCM codeto D

m0

Fr+

Receive GainAbsolute Accuracy Receive gain programmed for

maximum

Receive GainVariation with
programmed gain

Apply -6 dB

Measure V

Measure VFrGain over the

range from Maximum to

PCM codeto D

m0

Lr+

minimum setting.

Calculate the deviation from

the programmed gainrelative

to GRAE,

i.e.G

RAGE=Gactual-Gprog.-GRAE

Receive GainVariation with
programmed gain

Measure VLrGain over the

range from Maximum to

minimum setting.

Calculate the deviation from

the programmed gainrelative

to GRAL,

i.e.G

RAGL=Gactual-Gprog.-GRAL

Receive GainVariation with
temperature

Measured relative to GRA. (V

and VFr)

min. gain < GR < Max. gain

Receive GainVariation with
Supply

Receive GainVariation with
frequency (V

and VFr)

Lr

HPB = 0

Measured relative to GRA. (V

and VFr)

G

= Maximum Gain

R

Relative to 1015,625Hz,

multitone test techniqueused.

min. gain < G

< Max.gain

R

f = 60Hz

f = 100Hz

f = 200Hz

f = 300Hz

f = 400Hz to 3000 Hz

f = 3400Hz

f = 4000Hz

Receive GainVariation with
frequency (V

and VFr)

Lr

HPB = 1

Relative to 1015,625Hz,

multitone test techniqueused.

min. gain < G

< Max.gain

R

f = 50Hz

f = 100Hz to 3000 Hz

f = 3400Hz

f = 4000Hz

Receive GainVariation with
signal level (V

)

Fr

Receive GainVariation with
signal level (V

)

Lr

Sinusoidal Test Method

Reference Level = –10 dBm0

D

= -40 dBm0 to -3 dBm0

R

D

= -50 dBm0 to -40 dBm0

R

D

= -55 dBm0 to -50 dBm0

R

Sinusoidal Test Method

Reference Level = –10 dBm0

D

= -40 dBm0 to -3 dBm0

R

D

= -50 dBm0 to -40 dBm0

R

D

= -55 dBm0 to -50 dBm0

R

-0.5 0.5 dB

R

-0.5 0.5 dB

R

-0.5 0.5 dB

-0.5 0.5 dB

-0.1 0.1 dB

Lr

-0.1 0.1 dB

Lr

-1.5

-0.5

-1.5

-1.5

-0.5

-1.5

-0.5

-0.5

-1.2

-0.5

-0,5

-1.2

-20

-12

-2

0.5

0.5

0.0

-14

0.5

0.5

0.0

-14

0.5

0.5

1.2

0.5

0.5

1.2

ST5092

dB
dB
dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB

dB
dB
dB

23/29

ST5092

ENVELOPEDELAY DISTORTION WITH FREQUENCY

Symbol Parameter Test Condition Min. Typ. Max. Unit

DXA Tx Delay, Absolute f = 1600 Hz 320 µs
DXR Tx Delay, Relative f= 500 - 600Hz

f = 600- 800 Hz

f = 800- 1000 Hz

f = 1000- 1600 Hz

f = 1600- 2600 Hz

f = 2600- 2800 Hz

f = 2800- 3000 Hz

DRA Rx Delay, Absolute f = 1600Hz 280 µs
DRR Rx Delay, Relative f = 500- 600 Hz

f = 600- 800 Hz

f = 800- 1000 Hz

f = 1000- 1600 Hz

f = 1600- 2600 Hz

f = 2600- 2800 Hz

f = 2800- 3000 Hz

290
180

50
20
55
80

180

200
110

50
20

65
100
220

µ
µ
µs
µs
µ
µs
µs

µ
µs
µs
µ
µs
µs
µs

s
s

s

s

s

NOISE

Symbol Parameter Test Condition Min. Typ. Max. Unit

NXP Tx Noise, P weighted (up to

35dB)

NRP Rx Noise, A weighted

(max. gain)

NRS Noise, SingleFrequency MIC = 0V, Loop-around

PPSRx PSRR, Tx MIC = 0V,

PPSRp PSRR, Rx PCM Codeequals Positive Zero,

SOS Spurious Out-Band signal at

the output

(*) A Weighted

= 0V, DE =0 -75 -70 dBm0p

V

MIC

ReceivePCMcode =PositiveZero

120 150µVrms

SI = 0 andRTE = 0

-50 dBm0
measurament fromf = 0 Hz to
100 kHz

V

= 3.3 VDC+50mV

CC

rms

;

30 60 dB

f = 0Hzto 50KHz

V

= 3.3 VDC+ 50 mVrms,

CC

f = 0Hz - 4 kHz
f = 4kHz - 50 kHz

30
30

70
70

DR input setto -6 dBm0 PCM
code
300 -3400 Hz Input PCM Code
applied at DR
4600 Hz -5600 Hz
5600 Hz -7600 Hz
7600 Hz -8400 Hz

-40

-50

-50

(*)

dB
dB

dB
dB
dB

24/29

ST5092

DISTORTION

Symbol Parameter Test Condition Min. Typ. Max. Unit

56
50
48
43
38
29
24
15

50
48
43
38
29
24
15

50
48
43
38
29
24
15

#

65

56

64

50

61

48

52

43

23
13

42
31
26
16

37.5

28.5

64
62
53
43
33
28
18

64
62
53
43
33
28
18

-75 -46 dB

dB
dB
dB
dB
dB
dB
dB
dB

dB
dB
dB
dB
dB
dB
dB

dB
dB
dB
dB
dB
dB
dB

S

TDX

(*)

Signal to TotalDistortion
(up to 35dB gain)

Sinusoidal Test Method
(measured usinglinear 300 to
3400 weighting)
Level =0 dBm0

Typical values are measured with

30.5dB gain

Level =-6 dBm0
Level =-10 dBm0
Level =-20 dBm0
Level =-30 dBm0
Level =-40 dBm0
Level =-45 dBm0
Level =-55 dBm0

S

DFx

Single Frequency Distortion

0 dBm0inputsignal -80 -56 dB

transmit

S

TDRE

(*)

Signal to TotalDistortion (VFr)
( up to 20dB attenuation)

Sinusoidal Test Method
(measured usinglinear 300 to
3400 weighting)

Level =-6 dBm0
Typical values are measured with
20dB attenuation.

Level =-10 dBm0

Level =-20 dBm0

Level =-30 dBm0

Level =-40 dBm0

Level =-45 dBm0

Level =-55 dBm0

S

S

DFr

TDRL

(*)

Single Frequency Distortion
receive (V

)

Fr

Signal to TotalDistortion (VLr)
(up to 20dB attenuation)

-6 dBm0inputsignal -80 -50 dB

Sinusoidal Test Method

(measured usinglinear 300 to

3400 weighting)

Level =-6 dBm0
Typical values are measured with
20dB attenuation

Level =-10 dBm0

Level =-20 dBm0

Level =-30 dBm0

Level =-40 dBm0

Level =-45 dBm0

Level =-55 dBm0

S

DLr

Single Frequency Distortion
receive (V

)

Lr

-6 dBm0inputsignal -80 -50 dB

IMD Intermodulation Loop-around measurement

Voltage at MIC= -10 dBm0

to -27 dBm0,2 Frequencies in

the range300 - 3400 Hz

(*) The limit curve shall be determined by straight lines joining successive coordinates given in the table.
(#) Lower limits used duringthe automatic testing to avoid unrealistic yield loss due to ±2dB imprecision of time-limitednoise measurements.

CROSSTALK

Symbol Parameter Test Condition Min. Typ. Max. Unit

C

Tx-r

Transmit to Receive TransmitLevel = 0 dBm0,

f = 300- 3400 Hz
DR = QuietPCM Code

C

Tr-x

Receive toTransmit Receive Level = -6 dBm0,

f = 300- 3400 Hz
MIC= 0V

-100 -65 dB

-80 -65 dB

25/29

ST5092

APPLICATIONS
ApplicationNote for Microphone Connections

ST5092

ApplicationNote for VFrand VLrConnections

DYNAMIC

RECEIVERS

(32Ω)

VFr+

VFr-

ST5092

ST5090

VLr+

CERAMIC

R

R

ST5092

RECEIVERS

(50nF)

VFr+

VFr-

ST5090

ST5092 ST5092

VLr+

DYNAMIC/CERAMIC

(REVERSIBLE)

VFr+

VFr-

ST5090

R

VLr+

ST5092

RECEIVERS

VLr-

R must be greater than 30Ω
For higher capacitive transducers,lower Rvalues can be used.

VLr-

POWERSUPPLIES

While pins of ST5092 device are well protected
against electrical misuse, it is recommended that
the standardCMOS practise of applyingGND be­fore any other connections are made should al­ways be followed. In applications where the
printed circuit card may be plugged into a hot
socket with power and clocks already present, an
extra long groundpinon the connectorshould be

26/29

VLr-

D93TL078A

used.
To minimize noise sources, all ground connec-

tions to each device should meet at a common
point as closeas possibleto the GND pin in order
to prevent the interaction of ground return cur­rents flowing through a common bus impedance.
A power supply decoupling capacitor of 0.1 µF
should be connected from this common point to

ascloseas possible tothe device pins.

V

CC

TQFP44 (10 x 10) PACKAGEMECHANICAL DATA

ST5092

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.30 0.37 0.45 0.012 0.014 0.018

C 0.09 0.20 0.004 0.008

D 12.00 0.472

D1 10.00 0.394
D3 8.00 0.315

e 0.80 0.031

E 12.00 0.472
E1 10.00 0.394
E3 8.00 0.315

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

K 0°(min.), 3.5°(typ.),7°(max.)

D

D1

2333

34

B

44

1

e

22

E3D3E1

12

11

TQFP44

E

L1

L

0.10mm
.004

Seating Plane

B

K

A1

A

A2

C

27/29

ST5092

SO28 PACKAGE AND MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45° (typ.)

D 17.7 18.1 0.697 0.713
E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299
L 0.4 1.27 0.016 0.050

S8

mm inch

(max.)

°

28/29

ST5092

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of useof suchinformation nor for any infringement of patents or other rights of third partieswhich may resultfrom its use.No
license is granted by implication or otherwise under any patent or patentrightsof SGS-THOMSONMicroelectronics. Specification mentioned
in this publication are subject to change withoutnotice. This publication supersedes and replaces all information previously supplied. SGS­THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.

Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -

 1997 SGS-THOMSON Microelectronics – Printedin Italy– AllRights Reserved

Singapore - Spain - Sweden- Switzerland - Taiwan -Thailand - United Kingdom - U.S.A.

SGS-THOMSON Microelectronics GROUPOF COMPANIES

29/29