Datasheet ST5080A Datasheet (SGS Thomson Microelectronics)

PROGRAMMABLE ISDN AUDIO FRONT END

FEATURES:
Comp leteCODECandFILT ERsyst emin clud in g :

PCM ANALOG TO DIGITAL AND DIGITALTO
ANALOGCONVERTERS

POWERFUL ANALOG FRONT END CAPA­BLE TO INTERFACE DIRECTLY:

- Microphone Dynamic, Piezo or Electrete

- Earpiece down to 100Ω or up to 150nF

- Loudspeakerdown to 50Ω or Buzzer up to
600nF.

TRANSMIT BAND-PASSFILTER
ACTIVERC NOISE FILTER
RECEIVE LOW-PASS FILTER WITH SIN X/X

CORRECTION
MU-LAW OR A-LAW SELECTABLE COM-

PANDINGCODERAND DECODER
PRECISIONVOLTAGE REFERENCE

ST5080A

PIAFE

ADVANCE DATA

SO28

ORDERING NUMBER: ST5080D

Phones Features:

DUAL SWITCHABLE MICROPHONE AMPLI­FIER INPUTS. GAIN PROGRAMMABLE: 15
dBRANGE, 1 dB STEP.

LOUDSPEAKER AMPLIFIER AUXILIARY
OUTPUT. ATTENUATION PROGRAMMABLE:
30 dBRANGE, 2 dB STEP.

SEPARATEEARPIECEAMPLIFIER OUTPUT.
ATTENUATION PROGRAMMABLE: 15 dB
RANGE, 1 dB STEP

AUXILIARY SWITCHABLE EXTERNAL RING
INPUT (EAIN).

TRANSIENT SUPRESSION SIGNAL DURING
POWERON.

INTERNAL PROGRAMMABLE SIDETONE
CIRCUIT. ATTENUATIONPROGRAMMABLE:
15 dBRANGE, 1 dB STEP.

INTERNAL RING OR TONE GENERATORIN­CLUDING DTMF TONES, SINEWAVE OR
SQUAREWAVE WAVEFORMS. ATTENU­ATION PROGRAMMABLE: 27 dB RANGE, 3
dB STEP.

COMPATIBLE WITH HANDS-FREE CIRCUIT
TEA7540.

ON CHIP SWITCHABLE ANTI-ACOUSTIC
FEED-BACKCIRCUIT (ANTI-LARSEN).

GeneralFeatures:

EXTENDED TEMPERATURE RANGE OP­ERATION(*) –40°C TO+85°C.

EXTEN D EDPOWERSUPPLY RANGE5V±10%.
60 mW OPERATINGPOWER (TYPICAL).

1.0 mW STANDBY POWER(TYPICAL).
CMOSDIGITAL INTERFACES.
SINGLE+ 5V SUPPLY.
DIGITALLOOPBACKTEST MODE.
PROGRAMMABLE DIGITAL AND CONTROL

INTERFACES:

–Digital PCM Interface associated with

separate serial Control Interface MI­CROWIRE compatible.

–GCI interface compatible.

(*) Functionalityguaranteed in the range – 40°C to +85°C;

Timing and Electrical Specifications are guaranteed in the range

–25°Cto+85°C.

APPLICATIONS:

ISDN TERMINALS.
DIGITALTELEPHONES
CT2 AND GSMAPPLICATIONS

December 1994

This isadvanced information on anew productnow in development or undergoing evaluation. Details are subject to change without notice.

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ST5080A

PIN CONNECTIONS (Topview)

BLOCK DIAGRAM

2/32

TYPICALISDN TELEPHONE SET APPLICATION

ST5080A

3/32

ST5080A

GENERALDESCRIPTION

ST5080APIAFE is a combined PCM CODEC/FIL­TERdeviceoptimizedfor ISDNTerminalsand Digi­tal Telephone applications. This device is A-law
and Mu-law selectableand offersa numberof pro­grammable functions accessed through a serial
control channel.
Depending on mode selected, channel control is
provided by means of a separate serial channel
control MICROWIRE compatible or multiplexed
with the PCM voice data channel in a GCI com­patible format requiring only 4 digital interface
pins. When separate serial control interface is se­lected, PCM interface is compatible with Combo I
and Combo II families of devices such as
ETC5057/54,TS5070/71.
PIAFE is built using SGS-THOMSON’s advanced
HCMOSprocess.
Transmitsection of PIAFEconsistsof an amplifier
with switchable high impedance inputs followed
by a programmable gain amplifier, an active RC
antialiasingpre-filter to provide attenuationof high
frequency noise, an 8th order switched capacitor
band pass transmit filter and an A-law/Mu-law se­lectablecompandigencoder.
Receive section consist of an A-law/Mu-law se­lectable expanding decoder which reconstructs
the analog sampled data signal, a 3400 Hz low
pass filter with sin X/X correction followed by two

separate programmable attenuation blocks and
two power amplifiers: One can be used to drive
an earpiece, and the other to drive a 50 Ω loud­speaker.
Programmable functions on PIAFE include a
Ring/Tone generator which provides one or two
tones and can be directed to earpiece or to loud­speaker or alternatively a piezo transducer up to
600nF.
A separate programmable gain amplifier allows
gain control of the signal injected. Ring/Tone gen­erator provides sinewave or squarewave signal
with precise frequencies which may be also di­rected to the input of the Transmit amplifier for
DTMFtone generation.
An auxiliary analog input (EAIN) is also provided
to enable for example the output of an external
band limited Ring signal to the Loudspeaker.
Transmit signal may be fed back into the receive
ampifier with a programmableattenuation to pro­videa sidetone circuitry.
A switchable anti-accoustic feed-back system
cancelsthe larsen effect in speech monitoringap­plication.
Two additional pins are provided for insertion of
an external Handfree function in the Loudspeaker
receive path.
An output latch controlled by register program­mingpermitsexternal device control.

PIN FUNCTIONS

Pin Name Description

1,2 HFI, HFO Hands free I/Os:

3,4 V

5V

6,7 LS-,LS+ Receive analog loudspeaker amplifier complementary outputs,

Fr+,VFr–

CC

These two pins can be used to insert an external Handfree
circuit such as the TEA 7540 in the receive path. HFO is an
output which provides the signal issued from output of the
receive low pass filterwhile HFI is a high impendance input
which is connected directly to one ofthe inputs of the
Loudspeaker amplifier.

Receive analog earpiece amplifier complementary outputs,
capable of driving load impedances between 100and 400 Ω or
a piezoup to 150nF. These outputs can drive directly earpiece
transductor. The signal at this output can drive be the summ of:

- Receive Speech signal from D

- Internal Tone Generator,

- Sidetone signal.
Positive power supply input for the digital section.

+5 V + 10%.

intended for driving a Loudspeaker: 80 mW on 50Ω load
impedance can be provided at low distorsion meeting
specifications.
Alternatively this stage can drive a piezo transducer up to
600nF. The signal at these outputs can be the sum of:

- Receive Speech signal from D

- Internal Tone generator,

- External input signal from EAIN input.

,

R

,

R

4/32

PIN FUNCTIONS (continued)

Pin Name Description

9 MS Mode Select: This input selects COMBO I/II interface mode

10 D

X

11 N.C. No Connected.
14 D

R

15 FS Frame Sync input: This signal is a 8kHz clock which defines

16 MCLK Master Clock Input: This signalis used by the switched

17 LO Open drain output:

18 N.C. No Connected.
21 MIC2+ Alternative positive high impedance input to transmit pre-

22 MIC1+ Positive high impedance input to transmit pre-amplifier for

23 MIC1- Negative high impedance input to transmit pre-amplifier for

24 N.C. No connected.
25 V

CCA

26 MIC2- Alternative negative high impedance input to transmit pre-

27 GNDA Analog Ground: All analog signals are referenced to this pin.

28 EAIN External Auxiliary input: This input can be used to provide

with separate MICROWIRE Control interface when tied high
and GCImode when tied low.

Transmit Data ouput: Data is shifted out on this pin during the
assigned transmit time slots. Elsewhere D

output is in the high

X

impendance state. In COMBO I/II mode, voice data byte is
shifted out from TRISTATE output D

at the MCLK frequency

X

on the rising edge of MCLK. In GCI mode, voice data byte and
control bytes are shifted out from OPEN-DRAIN output D
half the MCLK. An external pull up resistor isneeded.

Receive data input: Data is shifted induring the assigned
Received time slots. In the COMBO I/IImode, voice data byte
is shifted in at the MCLK frequency on the falling edges of
MCLK. In the GCI mode, PCM data byte and contol byte are
shifted in at halfthe MCLK frequency on the receive rising
edges of MCLK. There is one period delay between transmit
rising edge and receive rising edge of MCLK.

the start of the transmit and receive frames. Eitherof three
formats may be used for this signal: non delayed timing mode,
delayed timing and GCI compatible timing mode.

capacitor filters and the encoder/decoder sequencing logic.
Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz
selected by means of ControlRegister CRO. MCLK is used
also to shift-in and out data. In GCI mode, 2.56 MHz and 512
kHz are not allowed.

a logic1 writteninto DO (CR1) appears at LO pin as a logic 0
a logic0 writteninto DO puts LO pin in high impedance.

amplifier.

microphone symetricalconnection.

microphone symetricalconnection.

Positive power supply input for the analog section.

+5 V + 10% . V

CC

and V

must be directly connected

CCA

together.

amplifier.

GND and GNDA must be connectedtogether close to the
device.

alternate signals to the Loudspeaker in placeof Internal Ring
generator. Input signal shouldbe voice band limited.

ST5080A

at

X

5/32

ST5080A

Following pin definitions are used only when COMBO I/II mode with separate MICROWIRE com­patible serial control port is selected. (MS input set equal one)

PIN FUNCTIONS (continued)

Pin Name Description

12 CO Control data Output: Serial control/status information is shifted

13 CI Control data Input: Serial Control information is shifted into the

19 CCLK Control Clock input: This clock shifts serial control information

20 CS- Chip Select input: When this pin is low, control information is

Followingpin definitions are used only when the GCI mode is selected. (MS input set equal zero)

out from the PIAFE on this pin when CS- is low on the falling
odges of CCLK.

PIAFE on this pin when CS- is low on the rising edges of CCLK.

into CI and out from CO when the CS- input is low, depending
on the current instruction. CCLK may be asynchronous with the
other system clocks.

written into and out from the PIAFE via CI and CO pins.

PIN FUNCTIONS (continued)

Pin Name Description

19,13,12,20 A0,A1,A2,A3 These pins select the address of PIAFE on GCI interface and

must be hardwired to either V
C4,C5,C6,C7 bits of the first address byte respectively.

or GND. A0,A1,A2,A3 refer to

CC

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ST5080A

FUNCTIONALDESCRIPTION
Power on initialization:

When power is first applied, power on reset
cicuitryinitializes PIAFE and puts it into the power
down state. Gain Control Registersfor the various
programmable gain amplifiersand programmable
switches are initialized as indicated in the Control
Registerdescription section.All CODEC functions
are disabled. Digital Interface is configured in GCI
modeor in COMBOI/II mode dependingon Mode
Selectpin connection.
The desired selection for all programmable func­tions may be intialized prior to a power up com­mand using Monitor channel in GCI mode or MI­CROWIREport in COMBOI/II mode.

Power up/downcontrol:

Following power-on initialization, power up and
powerdown controlmay be accomplishedby writ­ing any of the controlinstructions listed in Table 1
into PIAFE with ”P” bit set to 0 for power up or 1
for powerdown.
Normally, it is recommended that all programma­ble functions be initially programmed while the
device is powered down. Power state control can
then be included with the last programming in­struction or in a separatesingle byte instruction.
Any of the programmable registers may also be
modified while ST5080A is powered up or down
by setting ”P” bit as indicated. When power up or
down control is entered as a single byte instruc­tion, bit 1 must be setto a 0.
When a power up command is given, all de-acti­vated circuits are activated, but output D

will re-

X

main in the high impedancestate on B time slots
until the second Fspulse after power up,even ifa
B channelis selected.

Power downstate:

Following a period of activity, power down state
may be reentered by writing a power down in­struction.
ControlRegistersremain in theircurrent state and
canbe changed either by MICROWIRE control in­terface or GCI control channel depending on
modeselected.
In addition to the power down instruction, detec­tion of loss MCLK (no transition detected) auto­maticallyenters the device in ”reset” power down
state with D

output in the high impedance state

X

and L0in high impedance state.

Transmitsection:

Transmit analog interface is designed in two
stages to enablegains up to 35 dB tobe realized.
Stage 1 is a lownoise differentialamplifier provid­ing 20 dB gain. A microphone may be ca­pacitevely connected to MIC1+, MIC1- inputs,

while the MIC2+ MIC2– inputs may be used to
capacitively connect a second microphone (for
digital handsfree operation) or an auxiliary audio
circuitsuch as TEA 7540 Hands-free circuit. MIC1
or MIC2 source is selected with bit 7 of register
CR4.
Following the first stage is a programmable gain
amplifier which provides from 0 to 15 dB of addi­tional gain in 1 dB step. The total transmit gain
should be adjusted so that, at reference point A,
see Block Diagram description, the internal 0
dBmO voltage is 0.739 V (overload level is 1.06
Vrms). Second stage amplifier can be pro­grammed with bits 4 to 7 of CR5. To temporarily
mute the transmit input, bitTE (6of CR4) maybe
set low. In this case, the analog transmit signal is
grounded and the sidetone path is alsodisabled.
An active RC prefilter then precedes the 8th order
band pass switched capacitor filter. A/D converter
has a compressing characteristic according to
CCITT A or mu255 coding laws, which must be
selected by setting bits MA, IA in register CR0. A
precisionon chip voltagereferenceensures accu­rateand highly stable transmissionlevels.
Anyoffset voltagearising in the gain-setamplifier,
the filters or the comparatoris cancelled by an in­ternalautozero circuit.
Each encode cycle begins immediatly at the be­ginningof theselected Transmittime slot. The to­tal signal delay referenced to the start of the time
slotis approximatively195 µs (due to the transmit
filter) plus 123 µs (due to encoding delay), which
totals 320 µs. Voice data isshifted out on D

X

dur­ing the selected time slot on the transmit rising
adgesof MCLK.

Receivesection:

Voice Data is shifted into the decoder’s Receive
voice data Register via the D

pin during the se-

R

lected time slot on the8 receive edges of MCLK.
The decoder consists of an expanding DAC with
either A or MU255 law decoding characteristic
which is selected by the same control instruction
used to select the Encode law during intitializa­tion. Following the Decoder is a 3400 Hz 6th or­der low pass switchedcapacitor filter withintegral
SinX/X correctionfor the8 kHzsample and hold.
0 dBmO voltage at this (B) reference point (see
Block Diagram description) is 0.49 Vrms. A tran­scient suppressing circuitry ensure interference
noisesuppressionat power up.
The analog speech signal output can be routed
either to earpiece(V

FR+,VFR-

outputs) or to loud­speaker (LS+, LS- outputs) by setting bits SL and
SE(1 and 0 of CR4).
Total signal delay is approximatively190 µs (filter
plus decoding delay) plus 62.5 µs (1/2 frame)
whichgives approximatively252 µs.
Differential outputs V

FR+,VFR-

are intendedto di-

7/32

ST5080A

rectly drive an earpiece. Precedingthe outputs is
a programmableattenuationamplifier,which must
be set by writing to bits 4 to 7 in register CR6. At­tenuations in the range 0 to -15 dB relative to the
maximum level in 1 dB step can be programmed.
The input of this programmable amplifier is the
summ of several signals which can be selected
by writing to registerCR4.:

- Receive speech signal which has been de­codedand filtered,

- Internally generated tone signal, (Tone ampli­tude is programmed with bits 4 to 7 ofregister
CR7),

- Sidetonesignal, the amplitude of which is pro­grammedwith bits 0 to 3 of registerCR5

V

FR+

andV

outputsarecapableof drivingoutput

FR-

power level up to 14mW into differentially con­nectedloadimpedancebetween100 and 400Ω.

Differential outputs LS+,LS- are intended to di­rectlydrive a Loudspeaker.Precedingthe outputs
is a programmable attenuation amplifier, which
must be set by writing to bits 0 to 3 in register
CR6. Attenuationsin the range 0 to -30 dB rela­tive to the maximum level in 2.0 dB step can be
programmed.The input of this programmable am­plifier can be the summ of signals which can be
selectedby writing to register CR4:

- Receive speech signal which has been de­codedand filtered,

- Internally generated tone signal, (Tone ampli­tude is programmed with bits 4 to 7 ofregister
CR7),

- EAIN input which may be an alternate Ring
signal or any voice frequency band limited
signal. (An external decoupling capacitor of
about0.1µF is necessary).

Receive voice signal may be directed to output
HFO by means of bit HFE in Register CR4. After
processing,signal must be re-entered through in­put HFI to Loudspeakeramplifierinput. (An exter­nal decoupling capacitor of about 0.1µF is neces­sary).
LS+and LS- outputsare capable of driving output
power level up to 80 mW into 50 Ω differentially
connectedload impedanceat low distortion meet­ing PCM channel specifications. When the signal
source is a Ring squarewave signal, power levels
up to approximatively200 mW can bedelivered.

Anti-acoustic feed-back for loudspeaker to hand­set microphone loop with squelch effect: on chip
switchable anti-larsen for loudspeaker to handset
microphone feedback is implemented. A 12dB
depth gain control on both transmit and receive
path is provided to keep constant the loop gain.
On the transmit path the 12dB gain control is pro­vided starting from the CR5 transmit gain defini­tion; at the same time, on the receive path the
12dB gain control is provided starting from CR6

receive gain definition.

Digitaland Control Interface:

PIAFE provides a choice of either of two types of
DigitalInterfacefor both control data and PCM.
For compatibility with systemswhichuse time slot
oriented PCM busses with a separate Control In­terface, as used on COMBO I/II families of de­vices, PIAFE functions are described in next sec­tion.
Alternatively,for systems in which PCM and con­trol data are multiplexed together using GCI inter­face scheme, PIAFE functions are described in
the section following the next one.
PIAFE will automatically switch to one of these
two types of interface by sensing the MS pin.
Due to Line Transceiverclock recovery circuitry, a
low jitter may be provided on F
clocks. F

and MCLK must be always in phase.

S

and MCLK

S

For ST5421S Transceiver, as an example,
maximun value of jitter amplitude is a step of 65
ns at each GCI frame (125µs). So, the maximum
jitteramplitude is 130 ns pk-pk.

COMBOI/II mode.
Digital Interface (Fig. 1)

F

Frame Sync input determines the beginningof

S

frame. It may have any duration from a single cy­cle of MCLK to a squarewave. Two differentrela­tionships may be established between the Frame
Sync input and the first time slot of frame by set­tingbit 3 in register CR0. Non delayed data mode
is similar to long frame timing on ETC5057/
TS5070 series of devices (COMBO I and
COMBO II respectively): first time slot begins
nominally coincident with the rising edge of F

S

Alternativeis to use delayed data mode, which is
similar to short framesync timing on COMBO I or
COMBOII, in which F

input must be high at least

S

a half cycle of MCLK earlier the frame beginning.
A time slot assignment circuit on chip may be
used with both timingmodes, allowing connection
to one of the two B1 and B2 voice data channels.
Two data formats are available: in Format 1, time
slot B1 corresponds to the 8 MCLK cycles follow­ing immediately the rising edge of FS, while time
slot B2 corresponds to the 8 MCLK cycles follow­ing immediatelytime slot B1.
In Format 2, time slot B1 is identical to Format1.
Time slot B2 appears two bit slots after time slot
B1. This two bits space is left available for inser­tionof the D channeldata.
Data format is selected by bit FF (2) in register
CR0. Time slot B1 or B2 is selected by bit T0 (0)
in ControlRegister CR1.
Bit EN (2) in control register CR1 enables or dis­ables the voice data transfer on D

and DRas

X

appropriate. During the assigned time slot, D

.

X

8/32

Figure1: DigitalInterface Format

ST5080A

Figure2: GCI InterfaceFrame Structure

output shifts data out from the voice data register
on the rising edges of MCLK. Serialvoice data is
shifted into D

input during the same time slot on

R

the falling edges of MCLK.
D

is in the high impedance Tristate condition

X

when in the non selectedtime slots.

ControlInterface:

Control informationor data is written into or read­back from PIAFE via the serial control port con­sisting of control clock CCLK, serial data input CI
and output CO, and Chip Select input, CS-. All
controlinstructions require 2 bytes as listedin Ta-

ble 1, with the exception of a single byte power­up/downcommand.
To shift control data into ST5080A, CCLK must
be pulsed high 8 times while CS- is low. Data on
CI input is shifted into the serial input register on
the rising edge of each CCLK pulse. After all data
is shifted in, the content of the input shift register
is decoded, and may indicate that a 2nd byte of
control data will follow. This second byte may
either be defined by a second byte-wide CS­pulse or may follow the first contiguously,i.e. it is
not mandatory for CS- to return high in between
the first and second control bytes. At the end of

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ST5080A

the 2nd control byte, data is loaded into the ap­propriate programmable register. CS- must return
high at the end of the 2ndbyte.
To read-back status information from PIAFE, the
first byte of the appropriate instruction is strobed
in during the first CS- pulse, as defined in Table

1. CS- must be set low for a further 8 CCLK cy­cles, during which data is shifted out of the CO
pin on the falling edgesof CCLK.
When CS- is high, CO pin is in the high imped­ance Tri-state, enabling CO pins of several de­vices to be multiplexedtogether.
Thus, to summarise, 2 byte READand WRITE in­structions may use either two 8-bit wide CS­pulses or a single16 bitwide CS-pulse.

Controlchannel access to PCM interface:

It is possible to access the B channel previously
selectedin RegisterCR1.
A byte written into Control Register CR3 will be
automatically transmitted from D

output in the

X

followingframe in place of the transmit PCMdata.
A byte written into Control Register CR2 will be
automaticallysent through the receivepath to the
Receiveamplifiers.
In order to implement a continuousdata flow from
the Control MICROWIRE interface to a B chan­nel, it is necessary to send the control byte on
eachPCM frame.
A current byte received on D

input can be read

R

in the register CR2. In order to implement a con­tinuous data flow from a B channel to MI­CROWIREinterface,it is necessaryto read regis­ter CR2at each PCM frame.

GCI COMPATIBLE MODE

GCI interface is an European standardized inter­face to connect ISDN dedicated components in
the different configurations of equipment as Ter­minals,Network Terminations,PBX,etc...
In a Terminal equipment, this interface called
SCIT for Special Circuit Interface for Terminals al­lows for example connection between:

- ST5421 (SID-GCI) and ST5451 (HDLC/GCI
controller)used for 16 kbit/s D channel packet
framesprocessingand SIDcontrol,

- Peripheral devices connected to a 64 kbit/s B
channel and ST5451 used for GCI peripheral
control.

ST5080A may be assignedto one of the B chan­nels present on the GCI interface and is moni­tored via a control channel which is multiplexed
with the 64 kbit/sVoice Datachannels.

Figure 2 shows the frame structure at the GCI in­terface.Two 256 kbit/s channel are supported.

a)GCI channel 0: It is structured in four sub-

channels:

–B1 channel8 bits per frame

–B2 channel8 bits per frame
–M channel8 bits per frameignored byPIAFE
–SC channel 8 bits per frame ignored by

PIAFE
Only B1 or B2 channelcan be selectedin
PIAFEfor PCM data transfer.

b)GCI channel 1: It is structured also in four

subchannels:

–B1* channel8 bits per frame
–B2* channel8 bits per frame
–M* channel8 bits per frame

–SC* which is structured as follows:
6 bits ignored by PIAFE
A* bit associated with M* channel
E* bit associated with M* channel.

B1* or B2* channelcan be selectedin PIAFE
for PCM data transfer.
M* channeland two associatedbits E* and A*
are used for PIAFE control.

Thus, to summarize, B1, B2, B1* or B2* channel
can be selected to transmit PCM data and M*
channelis used toread/write status/commandpe­ripheral device registers. Protocol for byte ex­changeon the M* channel uses E* and A* bits.

PhysicalInterface

Theinterface is physicallyconstitued with 4 wires:
InputData wire: D
OutputData wire: D

R
X

Bit Clock: MCLK
Frame Synchronization: F

S

Data is synchronized by MCLK and FSclock in­puts.

insures reinitialization of time slot counter at

F

S

each frame beginning. The rising edge or FS is
the reference time for the first GCI channelbit.
Data is transmitted in both directions at half the
MCLK input frequency. Data is transmitted on the
the rising edge of MCLK and is sampled one pe­riod after the transmitrising edge, also on a rising
edge.
Note: Transmit data may be sampled by far-end
device ie SID ST5421on the falling edge 1.5 pe­riodafter the transmitrisingedge.
Unused channel are high impedance. Data out­puts are OPEN-DRAINand need an external pull
up resistor.

COMBOactivation/deactivation

ST5080A is automatically set in power down
modewhen GCIclocks are idle. GCI section is re­activatedwhen GCI clocks are detected. PIAFE is
completly reactivated after receiving of a power
up command.

Exchangeprotocol on M* channel

10/32

ST5080A

Protocol allows a bidirectional transfer of bytes
between ST5080A and GCI controller with ac­knowledgment at each received byte. For PIAFE,
standard protocol is simplified to provide read or
write register cycles almost identical to MI­CROWIREserial interface.

Write cycle

Control Unit sends through the GCI controller fol­lowingbytes:

- First byte is the chip selectbyte. The first four
bits indicate the device address:
(A3,A2,A1,A0). The four last bits are ignored.
ST5080A compare the validated byte re­ceived internally with the address defined by
pins A3, A2, A1, A0. If comparison is true,
byte is acknowledged, if not, ST5080A does
not acknowledgethe byte.

NOTE: An internal ”message in progress” flag re­mains active till the end of the complete message
transmission to avoid irrelevant acknowledgement
of any further byte.

- Second byte is structured as defined in Ta­ble 1.

- Third byte is the Data byte to write into the
Registeras indicatedin Table1.

It is possible but optional to writeto several differ­ent registers in a single message. In this case the
Chip Select byte is sent only once at the begin­ning of the message, the device automatically
togglesbetween address byte and data byte.

Readcycle

Control Unit sends two bytes. First byte is the
chip select byteas defined above. Second byte is
structuredas defined in Table1.
If PIAFE identifies a read-backcycle, bit 2 of byte
1 in Table 1 equal 1, it has to respond to theCon­trol Unit by sending a single byte message which
is the content of the addressedregister.
It is possible but optional to request several differ­ent read-backregister cycles in a single message
but it is recommended to wait the answer before
requesting a new read back to avoid loss of data.
ST5080A responds by sending a single data byte
messageat each request.

Received byte validation:

A received byte is validated if it is detected two
consecutivetimes identical.

ExchangeProtocol:

Exchangeprotocol is identicalfor both directions.
Sender uses E* bit to indicatethat it is sending a
M* byte while receiveruses A* bit to acknowledge
received byte.
When no message is transferred,E* bitand A* bit

are forced to inactivestate.
A transmission is initialized by sender putting E*
bit from inactive state to active state and by send­ing first byte on M* channelin the sameframe.
Transmission of a message is allowed only if A*
bit from the receiver has been set inactive for at
least two frames.
When receiver is ready, it validates the received
byte internally when received in two consecutive
framesidentical. Then the receiver sets first A* bit
from inactive to active state (pre-acknow­legement), and maintains A* bit activeat least in
the following frame (acknowledgement). If valida­tion is not possible, (two last bytes received are
notidentical), receiver aborts the message setting
A* bit active for only a singleframe.
For the first byte received, Abort sequence is not
allowed.PIAFEdoes not respond eitherif two last
bytesare not identical or if the byte received does
not meet the Chip Select byte defined by A0-A3
pinsbias.
A second byte may be transmitted by the sender
putting E* bit from active to inactive state and
sendingthe second byte on the M* channel in the
same frame. E* bit is set inactive for only one
frame. If it remains inactive more than oneframe,
it is an end of message (i.e. not second byte
available).
Thesecond byte may be transmittedonly after re­ceiving the pre-acknowledgment of the previous
byte transmitted (see Fig. 3). The same protocol
is used if a third byte is transmitted. Each byte
has to be transmitted at least in two consecutive
frames.
The receiver validates current received byte as
done on first byte and then set A* bit in the next
two frames first from active to inactive state (pre­acknowledgement),and after from inactive to ac­tive state (acknowledgement). If the receiver can­not validate the received current byte (two bytes
received are not identical), it pre-acknowledges
normally, but let A* bit in the inactive state in the
next frame which indicatesan abort request.
If a message sent by ST5080A is aborted, it will
stop the message and wait for a new read cycle
instructionfromthe controller.
A message received by ST5080A is acknow­ledgedor aborted without flowControl.
Figures 3 gives timing of a write cycle. Most sig­nificant bit (MSB) of a Monitorbyte is sent first on
M*channel.
E*and A* bits are active low and inactive state on
DOUT is high impedance.

PROGRAMMABLE FUNCTIONS

11/32

ST5080A

Figure3: E and A bits Timing

12/32

ST5080A

For both formats of Digital Interface,programma­ble functions are configuredby writing to a num­ber of registers using a 2-byte write cycle (not in­cludingchip select byte in GCI).

verification. Byte one is always register address,
while byte two is Data.
Table 1 lists the register set and their respective
adresses.

Most of these registers can also be read-back for

Table 1: ProgrammableRegister Intructions

Function Address byte

76543210
Single bytePower up/down PXXXXX0Xnone
Write CR0 P 0 0 0 0 0 1 X see CR0 TABLE 2
Read-back CR0 P 0 0 0 0 1 1 X see CR0
Write CR1 P 0 0 0 1 0 1 X see CR1 TABLE 3
Read-back CR1 P 0 0 0 1 1 1 X see CR1
Write Data to receive path P 0 0 1 0 0 1 X see CR2 TABLE 4
Read data from D
Write Data to D
Write CR4 P 0 1 0 0 0 1 X see CR4 TABLE 6
Read-back CR4 P 0 1 0 0 1 1 X see CR4
Write CR5 P 0 1 0 1 0 1 X see CR5 TABLE 7
Read-back CR5 P 0 1 0 1 1 1 X see CR5
Write CR6 P 0 1 1 0 0 1 X see CR6 TABLE 8
Read-back CR6 P 0 1 1 0 1 1 X see CR6
Write CR7 P 0 1 1 1 0 1 X see CR7 TABLE 9
Read-back CR7 P 0 1 1 1 1 1 X see CR7
Write CR8 P 1 0 0 0 0 1 X see CR8 TABLE 10
Read-back CR8 P 1 0 0 0 1 1 X see CR8
Write CR9 P 1 0 0 1 0 1 X see CR9 TABLE 11
Read-back CR9 P 1 0 0 1 1 1 X see CR9
Write Test Register CR10 P 1 0 1 0 0 1 X reserved

R

X

P001011XseeCR2
P 0 0 1 1 0 1 X see CR3 TABLE 5

Data byte

NOTE 1: bit 7 of theaddress byte anddata byte is always the firstbit clocked intoor out from: CI and CO pins when MICROWIRE serial

NOTE 2: ”P” bitis Power up/down Controlbit. P = 1 Means Power Down.

NOTE 3: Bit 2 is write/read select bit.

port is enabled,or into and out from D
X =reserved: write 0

Bit 1 indicates, if set, the presence of a second byte.

andDXpins when GCI mode selected.

R

13/32

ST5080A

Table 2: Control RegisterCR0Functions

76543210

F1 F0 MA IA DN FF B7 DL

0

0

1

0

0

1

1

1

0

X

1

0

1

1

0
1

0
1

0
1

*: state at power on initialization
(1): significant in COMBO I/II modeonly

MCLK = 512 kHz
MCLK = 1.536 MHz
MCLK = 2.048 MHz
MCLK = 2.560 MHz

Select MU-255 law
A-law includingeven bit inversion
A-law; No bit inversion

Delayed data timing
Non delayeddata timing

B1 and B2 consecutive
B1 and B2 separated

8 bits time-slot
7 bits time-slot

01Normal operation

Digital Loop-back

Function

(1)

*

(1)

*

* (1)

(1)

* (1)

(1)

*

*

Table 3: Control Register CR1 Functions

76543210

HFE ALE DO MR MX EN T1 T0

0
1

0
1

0
1

0
1

0
1

0
1

0
0
1
1

*: state at power oninitialization
(1): significant in COMBO I / II mode only
(2): significant in GCI mode only.

HFO / HFI pins disabled
HFO / HFipins enabled

Anti-larsen disabled
Anti-larsen enabled

L0 latch is put in high impedance
L0 latch set to 0

D

connected to rec. path

R

CR2 connected to rec. path
Trans path connected to D

CR3 connected to D

X

voice data transfer disable
voice data transfer enable

B1 channelselected

0

B2 channelselected

1

B1* channel selected

0

B2* channel selected

1

Function

X

*

*

*

* (1)

(1)

* (1)

(1)

*

*

(2)
(2)

14/32

Table 4: Control Register CR2 Functions

ST5080A

76543210

d7 d6 d5 d4 d3 d2 d1 d0

msb lsb Data sent to Receive path or Data received from D

Function

Table 5: Control RegistersCR3 Functions

76543210

d7 d6 d5 d4 d3 d2 d1 d0

msb lsb D

data transmitted

X

Function

Table 6: Control RegisterCR4 Functions

76543210

VS TE SI EE RTL RTE SL SE

0
1

0
1

0
1

0
1

0

0

1

0

0

1

1

1

0

0

1

0

0

1

1

1

MIC1 selected
MIC2 selected

Transmit input muted
Transmit input enabled

Internal sidetone disabled
Internal sidetone enabled

EAIN disconnected
EAIN selected to Loudspeaker

Ring / Tone muted
Ring / Tone to Earpiece
Ring / Tone to Loudspeaker
Ring / Tone to Earpiece and Loudspeaker

Receive signalmuted
Receive signalconnected toearpiece amplifer
Receive signalconnected toloudspeaker amplifier
Receive signalconnected toloudspeaker and
earpiece amplifier

Function

R

input

*

*

*

*

*

*

*: state at power on initialization

15/32

ST5080A

Table 7: Control RegisterCR5Functions

76543210

Transmit amplifier Sidetone amplifier

0

0

0

0

0

0

-

­1

1

*: state at power on initialization

1

0

-

­1

1

0

0

0

0

0

0

-

1

-

­1

1

Table 8: Control RegisterCR6Functions

76543210

Earpiece ampifier Loudspeaker

0

0

0

0

0

0

-

­1

1

1

0

-

­1

1

0

0

0
0

-

1

0

0

-

­1

1

0 dB gain
1 dB gain
in 1dB step
15 dB gain

-12.5 dB gain

0

-13.5 dB gain

1

in 1 dB step

-

-27.5 dB gain

1

0 dB gain

-1 dB gain
in 1 dB step

-15 dBgain

0 dB gain

0

-2 dB gain

1

in 2 dB step

-

-30 dBgain

1

Function

*

*

Function

*

*

*: state at power on initialization

16/32

Table 9: Control RegisterCR7Functions

76543210 Function

Tone gain F1 F2 SN DE Attenuation f1 V

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

X

1

X

1

1

0

0

1

1

1

0

0

1

0

0

1

1

1

0

X

1

X

0

0

1

0

0

1

1

1

0

0

0

0
1

....0dB *

-3 dB

-6 dB

-9dB

-12 dB

-15 dB

-18 dB

-21 dB

-24 dB

-27 dB

f1 and f2 muted
f2 selected
f1 selected
f1 and f2 in summed mode

Squarewave signal selected
Sinewave signal selected

01Normal operation

Tone / Ring Generator connected to
Transmit path

...2.4 (1)

1.70

1.20

0.85

0.60

0.43

0.30

0.21

0.15

0.10

ST5080A

pp

f2 V

pp

....1.9 (1)

1.34

0.95

0.67

0.47

0.34

0.24

0.17

0.12

0.08
*

*

*

*: state at power on initialization
(1): value provided if f1 or f2 is selected alone.

X reserved: write 0

if f1 and f2 are selected in the summed mode, f1=1.34 V
Outputgenerator is 2.4 V

pp

while f2=1.06 Vpp.

pp

Table 10: ControlRegister CR8Functions

76543210

f17 f16 f15 f14 f13 f12 f11 f10

msb lsb Binary equivalent of the decimalnumber used to calculate f1

Function

Table 11: ControlRegister CR9 Functions

76543210

f27 f26 f25 f24 f23 f22 f21 f20

msb lsb Binary equivalent of the decimalnumber used to calculate f2

Function

17/32

ST5080A

CONTROLREGISTER CR0

First byte of a READ or a WRITE instruction to
Control Register CR0 is as shown in TABLE 1.
Secondbyte is as shown in TABLE2.

2.048MHz.
512KHzand 2.56MHz are not allowed.
Default value is 1.536 MHz forboth modes.
Any clock different from the default one must be
selected prior a Power-Up instruction for both

Master Clock Frequency Selection

modes.
A masterclock must be providedto PIAFEfor op­erationof filter and coding/decodingfunctions.
In COMBO I/II mode, MCLK frequency can be
either 512 kHz, 1.536 MHz, 2.048 MHz or 2.56
MHz.
Bit F1 (7) and F0 (6) must be set during initializa­tion to select the correctinternal divider.

CodingLaw Selection

Bits MA (5) and IA (4) permit selection of Mu-255

law or A law coding with orwithout even bit inver-

sion.

Afterpower on initialization,the Mu-255law is se-

lected.
In GCI mode, MCLK must be either 1.536MHz or

Mu 255 law

msb lsb msb lsb msb lsb

Vin = + full scale 1 0 0000001010101011111111
Vin = 0 V
Vin = - full scale 0 0 0000000010101001111111

MSB isalways the firstPCM bitshifted in or out of PIAFE.

10111111111111111011001100110011100000000000000

True A law even bit

inversion

A law without even bit

inversion

0

Digital Interface timing

Bit DN=0 (3) selects digital interface in delayed
timing mode while DN=1 selects non delayed
data timing.
In GCImode, bit DN is not significant.
After reset and if COMBO I/II mode is selected,
delayeddata timingis selected.

Digital Interface format

Bit FF=0 (2) selects digital interface in Format 1
where B1 and B2 channelare consecutive. FF=1
selects Format 2 where B1 and B2 channel are
separatedby two bits. (seedigital interface format
section).
In GCImode, bit FF is not significant.

56+8 selection

Bit ’B7’ (1) selects capability for PIAFE to take
into account only the seven most significant bits
of the PCM data byte selected.
When’B7’ is set, theLSB biton D
LSB bit on D

ishigh impedance.This function al-

X

isignored and

R

lows connection of an external ”in band” data
generator directly connected on the Digital Inter­face.

Digital loopback

Digital loopback mode is entered by setting DL
bit(0) equal 1.
In Digital Loopback mode, data written into Re­ceive PCM Data Register from the selected re­ceived time-slot is read-back from that Register in

the selected transmit time-slot on D

. Time slot is

X

selectedwith Register CR1.

No PCM decodingor encoding takes place in this

mode. Transmit and Receive amplifier stages are

muted.

CONTROL REGISTERCR1

First byte of a READ or a WRITE instruction to

Control Register CR1 is as shown in TABLE 1.

Secondbyte is as shown in TABLE3.

Hands-free I/Os selection

Bit HFE set to one enables HFI, HFO pins for

connectionof an externalhandfree circuit such as

TEA 7540. HFO is an analog output that provides

the receive voice signal. 0 dBMO level on that

output is 0.491 Vrms (1.4V

). HFI is an analog

pp

high impedance input (10 KΩ typ.) intended to

send back the processed receive signal to the

Loudspeaker. 0 dBMO level on that input is

0.491Vrms.

Anti-larsenselection

Bit ALE set to one enableson-chip antilarsen and

squelcheffect system.

Latch output control

Bit DO controls directly logical status of latchout-

put LO: ie, a ”ZERO” written in bit DO puts output

LO in high impedance,a ”ONE” written in bit DO

setsoutput LO to zero.

18/32

ST5080A

Microwire access to B channel on receive
path

Bit MR (4) selects access from MICROWIRE
Register CR2 to Receive path. When bit MR is
set high, data written to register CR2 is decoded
each frame, sent to the receive path and data in­put at D

isignored.

R

In the other direction, current PCM data input re­ceived at D

can be read from register CR2 each

R

frame.

Microwire access to B channel on transmit
path

Bit MX(3) selects access from MICROWIREwrite
only Register CR3 to D
set high, data written to CR3 is output at D

output. When bit MX is

X

X

every

frameand the output of PCM encoder is ignored.

B channelselection

Bit ’EN’ (2) enables or disables voice data trans­fer on D

and DRpins. When disabled, PCM data

X

from DR is not decoded and PCM time-slots are
high impedance on D

.

X

In GCI mode, bits ’T1’ (1) and ’T0’ (0) select one
of the four channelsof the GCI interface.
In COMBO I/II mode, only B1 or B2 channel can
be selected according to the interface format se­lected.Bit ’T1’ isignored.

CONTROLREGISTER CR2

Data sent to receive path or data received from
D

input. Refer to bit MR(4) in ”Control Register

R

CR1” paragraph.

CONTROLREGISTER CR3

data transmitted.Refer to bit MX(3) in ”Control

D

X

RgisterCR1” paragraph.

CONTROLREGISTER CR4

First byte of a READ or a WRITE instruction to
Control Register CR4 is as shown in TABLE 1.
Secondbyte is as shown in TABLE6.

TransmitInput Selection

MIC1 or MIC2 source is selectedwith bitVS (7).
Transmit input selected can be enabled or muted
with bit TE (6).
Transmit gain can be adjusted within a 15 dB
rangein 1 dB step with Register CR5.

loudspeakeramplifier input.

Ring/Tone signal routing

Bits ”RTL” (3) and RTE(2) provide select capabil-

ity to connect on-chip Ring/Tone generator either

to loudspeaker amplifier input or to earpiece am-

plifierinput or both.

PCMreceive data routing

Bits ”SL”(1) and ”SE”(0) provideselect capability

to connect received speech signal either to Loud-

speaker amplifier input or to earpiece amplifier in-

put or both.

CONTROL REGISTERCR5

First byte of a READ or a WRITE instuction to

Control Register CR5 is as shown in TABLE 1.

Secondbyte is as shown in TABLE7.

Transmit gain selection

Transmit amplifier can be programmed for a gain

from0dB to15dB in 1dB step with bits 4 to7.

0 dBmO level at the output of the transmit ampli-

fier (A reference point) is 0.739 Vrms (overload

voltageis 1.06 Vrms).

Sidetone attenuationselection

Transmit signal picked up after the switched ca-

pacitor low pass filter may be fed back into the

ReceiveEarpiece amplifier.

Attenuation of the signal at the output of the

sidetone attenuator can be programmed from

–12.5dB to -27.5dB relative to reference point

A in 1 dB step with bits 0 to 3.

CONTROL REGISTERCR6

First byte of a READ or a WRITE instruction to

Control Register CR6 is as shown in TABLE 1.

Secondbyte is as shown in TABLE8.

Earpieceamplifier gain selection:

Earpiece Receive gain can be programmed in 1

dB step from 0 dB to -15 dB relative to the maxi-

mumwith bits 4 to7.

0 dBmO voltage at the output of the amplifier on

pins V

Fr+

and V

is then 824.5 mVrms when

Fr-

0dB gain is selected down to 146.6 mVrms

when –15 dB gain is selected.

Sidetoneselect

Bit ”SI” (5) enablesor disables Sidetone circuitry.
When enabled, sidetone gain can be adjusted
with Register (CR5). When Transmit path is dis­abled, bit TE set low, sidetone circuit is also dis­abled.

ExternalAuxiliarysignal select

Bit ”EE” (4) set to one connectsEAIN input to the

Loudspeakeramplifiergain selection:

Loudspeaker Receive amplifier gain can be pro-

grammed in 2 dB step from 0 dB to -30 dB rela-

tive to the maximumwith bits0 to 3.

0 dBmO voltage on the output of the amplifieron

pins LS+ and LS- on 50 Ω is then 1.384 Vrms

(3.91V

43.7 mVrms (123.6mV

) when 0 dB gain is selected down to

pp

) when -30 dB gain is se-

pp

lected.

19/32

ST5080A

Currentlimitation is approximatively150 mApk.

CONTROLREGISTER CR7:

First byte of a READ or a WRITE instruction to
Control Register CR7 is as shown in TABLE 1.
Secondbyte is as shown in TABLE9.

Tone/Ring amplifiergain selection

Output level of Ring/Tone generator, before at­tenuation by programmable attenuatoris 2.4 Vpk­pk when f1 generator is selected alone or
summed with the f2 generator and 1.9 Vpk-pk
when f2 generatoris selected alone.
Selected output level can be attenuated down to

-27 dB by programmable attenutator by setting
bits 4 to 7.

Frequencymode selection

Bits ’F1’ (3) and ’F2’ (2) permit selection of f1
and/or f2 frequency generator according to TA­BLE 9.
When f1 (or f2) is selected, output of the
Ring/Toneis a squarewave(or asinewave) signal
at the frequency selected in the CR8 (or CR9)
Register.
When f1 and f2 are selected in summed mode,
output of the Ring/Tone generator is a signal
where f1 and f2 frequencyaresummed.
In order to meet DTMF specifications, f2 output
level is attenuatedby 2dB relative to the f1output
level.
Frequencytemporizationmust be controlled by the

microcontroller.

Waveformselection

Bit ’SN’ (1) selects waveform of the output of the

Ring/Tone generator. Sinewave or squarewave

signalcan be selected.

DTMFselection

Bit DE (0) permitsconnection of Ring/Tone/DTMF

generator on the Transmit Data path instead of

the Transmit Amplifier output. Earpiece feed-back

may be provided by sidetone circuitry by setting

bit SI or directly by setting bit RTE in Register

CR4.Loudspeakerfeed-back may be provideddi-

rectly by setting bit RTL in RegisterCR4.

CONTROL REGISTERSCR8 ANDCR9

First byte of a READ or a WRITE instruction to

Control Register CR8 or CR9 is as shown in TA-

BLE 1. Second byte is respectively as shown in

TABLE10 and 11.

Tone or Ring signal frequency value is definedby

the formula:

f1 = CR8 / 0.128Hz

and

f2 = CR9 / 0.128Hz

where CR8 and CR9 are decimal equivalents of

the binary values of the CR8 and CR9 registers

respectively. Thus, any frequencybetween 7.8 Hz

and 1992 Hz maybe selected in 7.8 Hz step.

TABLE 12 gives examples for the main frequen-

ciesusual for Toneor Ring generation.

20/32

Table 12: Examplesof Usual FrequencySelection

Description f1 value (decimal) Theoric value (Hz) Typical value (Hz) Error %

Tone 250 Hz
Tone 330 Hz
Tone 425 Hz
Tone 440 Hz
Tone 800 Hz
Tone 1330 Hz

DTMF 697 Hz
DTMF 770 Hz
DTMF 852 Hz
DTMF 941 Hz
DTMF 1209 Hz
DTMF 1336 Hz
DTMF 1477 Hz
DTMF 1633 Hz

SOL
LA
SI
DO
RE
MI flat
MI
FA
FA sharp
SOL
SOL sharp
LA
SI
DO
RE
MI

32
42
54

56
102
170

89

99
109
120
155
171
189
209

50

56

63

67

75

80

84

89

95
100
106
113
126
134
150
169

250
330
425
440
800

1330

697
770
852

941
1209
1336
1477
1633

392

440

494

523.25

587.33

622.25

659.25

698.5
740
784

830.6
880

987.8

1046.5

1174.66

1318.5

250

328.2

421.9

437.5

796.9

1328.1

695.3

773.4

851.6

937.5

1210.9

1335.9

1476.6

1632.8

390.6

437.5

492.2

523.5

586.0

625.0

656.3

695.3

742.2

781.3

828.2

882.9

984.4

1046.9

1171.9

1320.4

ST5080A

.00
–.56
–.73
–.56
–.39
–.14

–.24
+.44
–.05
–.37
+.16
–.01

.00

.00
–.30

–.56
–.34
+.04
–.23
+.45
–.45
–.45
+.30
–.34
–.29
+.33
–.34
+.04
–.23
+.14

POWERSUPPLIES

While pins of PIAFE device are well protected
against electrical misuse, it is recommended that
the standard CMOS practiseof applying GND be­fore any other connections are made should al­ways be followed. In applications where the
printed circuit card may be plugged into a hot
socket with power and clocks already present, an
extralong groundpin on the connector should be

used.
To minimize noise sources, all ground connec­tions to each device should meet at a common
point as close as possible to the GND pin in order
to prevent the interaction of ground return cur­rents flowing through a common bus impedance.
A power supply decoupling capacitor of 0.1 µF
should be connected from this common point to
V

as close as possibleto thedevicepins.

CC

21/32

ST5080A

TIMINGDIAGRAM
NonDelayed Data Timing Mode

DelayedData Timing Mode

22/32

TIMINGDIAGRAM (continued)
GCI Timing Mode

ST5080A

Serial Control Timing (MICROWIRE MODE)

23/32

ST5080A

ABSOLUTE MAXIMUMRATINGS

Parameter Value Unit

to GND 7V

V

CC

Current at V
Current at V

MIC(VCC
RxO

Current atany digitaloutput + 50 mA
Voltage at any digitalinput (V
Storage temperature range - 65 to + 150 °C
Lead Temperature (wave soldering, 10s) + 260 °C

TIMINGSPECIFICATIONS (unlessotherwise specified,VCC=5V + 10%, TA= –25°Cto 85°C;
typicalcharacteristicsare specified V
all signals are referencedto GND,seeNote 5 for timingdefinitions)

MASTERCLOCK TIMING

Symbol Parameter Test Condition Min. Typ. Max. Unit

f

MCLK

t

WMH

t

WML

t

RM

t

FM

≤ 5.5V) ±50 mA

andLS + 100 mA

≤ 5.5V); limited at + 50mA VCC+ 1 to GND - 1 V

CC

= 5V,TA=25°C;

CC

Frequency of MCLK Selection of frequency is

programmable (see table 2)

512

1.536

2.048

2.560
Period of MCLK high Measured from VIHto V
Period of MCLK low Measured from VILto V
Rise Time of MCLK Measured from VILto V
Fall Time of MCLK Measured from VIHto V

IH
IL
IH

IL

80 ns
80 ns

30 ns
30 ns

kHz
MHz
MHz
MHz

PCM INTERFACETIMING (COMBO I / II and GCImodes)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Hold Time MCLK low to FS low 10 ns
Setup Time, FS high to MCLK

30 ns

low
Delay Time, MCLK high to data

Load = 100 pf 100 ns

valid
Delay Time, MCLK low to DX

15 100 ns

disabled
Delay Time, FS high to data valid Load = 100 pf ;

100 ns
Applies only if FS rises later
than MCLK risingedge in Non
Delayed Mode only

Setup Time, DRvalid to MCLK

20 ns

receive edge
Hold Time, MCLK low to D

R

20 ns

invalid

24/32

t

HMF

t

SFM

t

DMD

t

DMZ

t

t

SDM

t

HMD

DFD

ST5080A

SERIALCONTROL PORT TIMING (Usual COMBOI / II modeonly)

Symbol Parameter Test Condition Min. Typ. Max. Unit

f

CCLK

t

WCH

t

WCL

t

RC

t

FC

t

HCS

t

SSC

t

SDC

t

HCD

t

DCD

t

DSD

t

DDZ

t

HSC

t

SCS

Note 5: A signalis valid if it is above VIHorbelow VILand invalid if itisbetween VILand VIH.

Frequency of CCLK 2.048 MHz
Period of CCLK high Measured from VIHto V
Period of CCLK low Measured from VILto V
Rise Time of CCLK Measured from VILto V
Fall Time of CCLK Measured from VIHto V
Hold Time, CCLK high to CS–

IH
IL
IH

IL

160 ns
160 ns

50 ns
50 ns

10 ns

low
Setup Time, CS– low to CCLK

50 ns

high
Setup Time, CI valid to CCLK

50 ns

high
Hold Time, CCLK high to CI

50 ns

invalid
Delay Time, CCLK low to CO

data valid
Delay Time, CS–low to CO data

Load = 100 pF ,
plus 1 LSTTL load

80 ns

50 ns

valid
Delay Time CS–high or 8th

15 80 ns
CCLK low to CO high
impedance whichever comes
first

Hold Time, 8th CCLK high to

100 ns

CS– high
Set up Time, CS– high to CCLK

100 ns

high

For the purpoesof this specification thefollowing conditionsapply:
a) All input signal are defined as: V
b) Delay times are measured from the inputs signal valid to theoutput signal valid.
c) Setup times are measured from the data input valid to the clock input invalid.
d) Hold times are measured from the clock signal valid to thedata input invalid.

= 0.4V, VIH= 2.7V, tR< 10ns, tF< 10ns.

IL

ELECTRICALCHARACTERISTICS (unlessotherwisespecified,VCC=5V + 10%, TA= –25°Cto 85°C;
typicalcharacteristicare specified at V

=5V, TA=25°C; all signals are referenced to GND)

CC

DIGITALINTERFACES

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

IL

Input Low Voltage All digital inputs DC

AC

V

IH

Input High Voltage All digital inputs DCAC2.0 V

2.7 V

V

OL

Output Low Voltage DX,IL= -2.0mA; DC

all otherdigital outputs, AC
I

= –1mA

L

V

OH

I

IL

I

IH

I

OZ

Output High Voltage DX,IL= 2.0mA; DC

all otherdigital outputs, AC
I

= 1mA

L

Input Low Current Any digital input,

GND < V

IN<VIL

Input High Current Any digital input,

V

IH<VIN<VCC

Output Current in High

DXand CO -10 10 µA

2.4

2.0

-10 10 µA

-10 10 µA

impedance (Tri-state)

0.7 V

0.4 V

0.4

0.7

V
V

V
V

25/32

ST5080A

ANALOGINTERFACES

Symbol Parameter Test Condition Min. Typ. Max. Unit

I

R
R
C

R

OVFr0

V

OSVFr0

R

C
R

V

OSLS

MIC

MIC
LVFr
LVFr

LLS

LLS

OLS

Input Leakage GND < V
Input Resistance GND < V
Load Resistance V
Load Capacitance V

Fr+
Fr+

to V
to V

MIC<VCC

MIC<VCC
Fr­Fr-

Output Resistance Steady zero PCM code applied

to DR; I = + 1mA

Differential offset:
Voltage at V

Fr+,VFr-

Load Resistance LS+to L
Load Capacitance LS+to L

Alternating + zero PCM code
applied to DR maximum
receive gain; R

S­S-

= 100Ω

L

Output Resistance Steady zero PCM code applied

to DR; I + 1mA

Differential offset Voltage at LS+,
L

S-

Alternating + zero PCM code
applied to DR maximum
receive gain; R

=50Ω

L

-100 +100 µA
50 kΩ

100 Ω

150 nF

1.0 Ω

-100 +100 mV

50 Ω

600 nF

1 Ω

–100 +100 mV

POWERDISSIPATION

Symbol Parameter Test Condition Min. Typ. Max. Unit

I

CC0

Power down Current CCLK,CI = 0.4V;CS = 2.4V

0.2

0.5

mA
(µwire only)
All other inputs active

I

CC1

GCI mode only:

Power Up Current LS+,LS-and V

Fr+,VFr-

not

0.2

0.5

mA

12.0 17.0 mA

loaded

TRANSMISSION CHARACTERISTICS (unless otherwise specified, VCC= 5V + 10%, TA= –25°Cto
85°C; typical characteristics are specified at V

= 5V, TA=25°C, MIC1/2 = 0dBm0,DR= 0dBm0PCM

CC

code, f = 1015.625 Hz; all signalare referencedto GND)

AMPLITUDE RESPONSE (Maximum, Nominal,and MinimumLevels)
Transmitpath - Absolutelevels at MIC1 / MIC2

Parameter Test Condition Min. Typ. Max. Unit

0 dBM0 level Transmit Amps connected for

0dB gain

Overload level A law selected 106.08 mV
Overload level mu law selected 106.47 mV
0 dBM0 level Transmit Amps connected for

15dB gain

Overload level A law selected 18.86 mV
Overload level mu law selected 18.93 mV

73.9 mV

13.14 mV

RMS

RMS
RMS
RMS

RMS
RMS

26/32

ST5080A

TRANSMISSION CHARACTERISTICS (continued)
AMPLITUDE RESPONSE (Maximum, Nominal,and MinimumLevels)

Receivepath - Absolutelevels at V

Parameter Test Condition Min. Typ. Max. Unit

0 dBM0 level Receive Amp programmed for

0 dBM0 level Receive Amp programmed for

AMPLITUDE RESPONSE (Maximum, Nominal,and MinimumLevels)
Receivepath - Absolutelevels at L

Parameter Test Condition Min. Typ. Max. Unit

0 dBM0 level Receive Amp programmed for

0 dBM0 level Receive Amp programmed for

AMPLITUDE RESPONSE

Transmitpath

Symbol Parameter Test Condition Min. Typ. Max. Unit

G

XA

G

XAG

G

XAT

G

XAV

G

XAF

Transmit Gain Absolute
Accuracy

Transmit Gain Variation with
programmed gain

Transmit Gain Variation with
temperature

Transmit Gain Variation with
supply

Transmit Gain Variation with
frequency

(Differentiallymeasured)

FR

0dB gain

- 15dB attenuation

(Differentiallymeasured)

S

0dB gain

- 30dB gain

Transmit Gain Programmed for
maximum.
Measure deviation of Digital
PCM Code from ideal 0dB
PCM code at D

Measure Transmit Gainover
the rangefrom Maximum to
minimum setting.
Calculate the deviation from
the programmed gain relative
to GXA,
i.e. G

AXG=Gactual-Gprog.-GXA

Measured relative to GXA.
min. gain < G

Measured relative to G
GX= Maximum gain

Relative to 1015,625 Hz,
multitone testtechnique used.
min. gain < G

X

< Max. gain

X

< Max. gain

X

XA

824.5 mV

146.6 mV

1.384 V

43.7 mV

-0.30 0.30 dB

m0

-0.5 0.5 dB

-0.1 0.1 dB

-0.1 0.1 dB

RMS

RMS

RMS

RMS

f = 60 Hz
f = 200 Hz
f = 300 Hz to 3000 Hz
f = 3400 Hz

-1.5

-0.3

-0.8
f = 4000 Hz
f = 4600 Hz (*)
f = 5000 Hz to 6000 Hz
f = 8000 Hz (*)
f > 8000 Hz

G

XAL

(*) The limit at frequencies between 4600Hz and 8000Hz lies on a stright line connecting the two frequencies on a linear (dB) scale versuslog
(Hz) scale.

Transmit Gain Variation with
signal level

Sinusoidal Test method.
Reference Level = -10 dB
V

= -40 dBm0to +3 dB

MIC

V

= -50 dBm0to -40dB

MIC

V

= -55 dBm0to -50 dB

MIC

m0

m0

m0

m0

-0.25

-0.5

-1.2

-26

-0.1

0.3

0.0

-14

-35

-40

-47

-40

0.25

0.5

1.2

dB
dB
dB
dB
dB
dB
dB
dB
dB

dB
dB
dB

27/32

ST5080A

AMPLITUDE RESPONSE

Receivepath

Symbol Parameter Test Condition Min. Typ. Max. Unit

G

G

G

G

G

G

G

RAE

RAL

RAGE

RAGL

RAT

RAV

RAF

Receive Gain Absolute Accuracy Receive gain programmed for

maximum
Apply 0 dB
Measure V

PCM code to D

m0
Fr+

Receive Gain Absolute Accuracy Receive gain programmed for

maximum

Receive Gain Variation with
programmed gain

Apply 0 dB
Measure L

Measure Earpiece Gain over
the rangefrom Maximum to

PCM code to D

m0

S+

minimum setting.
Calculate the deviation from
the programmed gain relative
to GRAE,
i.e.G

RAGE=Gactual-Gprog.-GRAE

Receive Gain Variation with
programmed gain

Measure Loudspeaker Gain
over the range from Maximum
to minimum setting.
Calculate the deviation from
the programmed gain relative
to GRAL,
i.e.G

RAGL=Gactual-Gprog.-GRAL

Receive Gain Variation with
temperature

Receive Gain Variation with
Supply

Receive Gain Variation with
frequency
(Earpieceor Loudspeaker)

Measured relative to GRA. (LS
and V

)

Fr

G

= Maximum Gain

R

Measured relative to GRA. (LS
and V

)

Fr

G

= Maximum Gain

R

Relative to 1015,625 Hz,
multitone testtechnique used.
min. gain < G

< Max. gain

R

-0.3 0.3 dB

R

-0.6 0.6 dB

R

-0.5 0.5 dB

-1.0 1.0 dB

-0.1 0.1 dB

-0.1 0.1 dB

28/32

G

G

RAL E

RAL L

Receive Gain Variation with
signal level (Earpiece)

Receive Gain Variation with
signal level (Loudspeaker)

f = 200 Hz
f = 300 Hz to 3000 Hz
f = 3400 Hz
f = 4000 Hz

Sinusoidal Test Method
Reference Level = –10 dBm0
D

= 0 dBm0 to +3 dBm0

R

D

= -40 dBm0 to 0 dBm0

R

D

= -50 dBm0 to -40 dBm0

R

D

= -55 dBm0 to -50 dBm0

R

Sinusoidal Test Method
Reference Level = –10 dBm0
D

= 0 dBm0 to +3 dBm0

R

D

= -40 dBm0 to 0 dBm0

R

D

= -50 dBm0 to -40 dBm0

R

D

= -55 dBm0 to -50 dBm0

R

-0.3

-0.3

-0.8

-0.25

-0.25

-0.5

-1.2

-0.25

-0.25

-0,5

-1.2

0.3

0.3

0.0

-14

0.25

0.25

0.5

1.2

0.25

0.25

0.5

1.2

dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB
dB

ST5080A

ENVELOPE DELAY DISTORTION WITH FREQUENCY

Symbol Parameter Test Condition Min. Typ. Max. Unit

DXA Tx Delay, Absolute f = 1600 Hz 320 µs
DXR Tx Delay, Relative f = 500 - 600 Hz

f = 600 - 800 Hz
f = 800 - 1000 Hz
f = 1000 - 1600Hz
f = 1600 - 2600Hz
f = 2600 - 2800Hz
f = 2800 - 3000Hz

DRA Rx Delay, Absolute f = 1600 Hz 252 µs
DRR Rx Delay, Relative f = 500 - 1000 Hz

f = 1000 - 1600Hz
f = 1600 - 2600Hz
f = 2600 - 2800Hz
f = 2800 - 3000Hz

NOISE

Symbol Parameter Test Condition Min. Typ. Max. Unit

NXC Tx Noise, C weighted V
NXP Tx Noise, P weighted V

NREC Rx Noise, C weighted

(Earpiece)

NREP Rx Noise, P weighted

(Earpiece)

NRLC Rx Noise, C weighted

(Loudspeaker)

NRLP Rx Noise,P weighted

(Loudspeaker)

NRS Noise, Single Frequency V

PPSRx Positive PSRR, Tx V

PPSRp Positive PSRR, Rx PCM Code equalsPositive Zero,

SOS Spurious Out-Band signal at

the output

= 0V Max. Gain 16 dBrnC0

MIC

= 0V Max. Gain -70 dBm0p

MIC

Receive PCM code = Alternating
Positive and Negative Code
Max. Gain

Receive PCMcode= Positive Zero
Max. Gain

Receive PCM code = Alternating
Positive and Negative code
Max. Gain

Receive PCMcode= Positive Zero
Max. Gain

= 0V, Loop-around

MIC

measurament from f = 0 Hz to
100 kHz

= 0V,

MIC

V

= 5.0 VDC+ 100 mV

CC

rms

;

30 dB

f = 0Hz to 50KHz

30

V

= 5.0 VDC + 100 mVrms,

CC

measure V
f=0Hz-4kHz
f = 4 kHz - 50 kHz

Fr+

30
30

DR input set to 0 dBm0 PCM
code
300 - 3400 Hz Input PCM Code
appliedat DR
4600Hz - 5600 Hz
5600Hz - 7600 Hz
7600Hz - 8400 Hz
8400Hz - 100 kHz

225
125

50
20
55
80

130

10

30
105
135
185

18 dBrnC0

-70 dBm0p

21 dBrnC0

-67 dBm0p

-50 dBm0

-40

-50

-50

-50

µs
µs
µs
µs
µs
µs
µs

µs
µs
µs
µs
µs

dB

dB
dB

dB
dB
dB
dB

29/32

ST5080A

DISTORTION

Symbol Parameter Test Condition Min. Typ. Max. Unit

S

TDx

S

TDr

S

DFx

S

DFr

IMD Intermodulation Loop-around measurament

CROSSTALK

Symbol Parameter Test Condition Min. Typ. Max. Unit

C

Tx-r

C

Tr-x

Signal to Total Distortion Sinusoidal Test Methode

(measured using C message
weighting Filter)
Level = 0 dBm0 to - 20 dBm0
Level = - 20 to -30 dBm0
Level = - 40 dBm0
Level = - 45 dBm0

Single Frequency Distortion

0 dBm0 input signal -46 dB

transmit
Single Frequency Distortion

0 dBm0 input signal -46 dB

receive

Voltage at V

= -4 dBm0

MIC

to -21 dBm0, 2 Frequencies in
the range300 - 3400 Hz

Transmit to Receive Transmit Level = 0 dBm0,

f = 300 - 3400 Hz
DR = QuietPCM Code

Receive to Transmit Receive Level = 0 dBm0,

f = 300 - 3400 Hz
V

=0V

MIC

37
36
29
24

-41 dB

-65 dB

-65 dB

dBC
dBC
dBC
dBC

APPLICATIONNOTE FOR MICROPHONE CONNECTIONS

The 4 connectionmodes (since the MIXED MODE is symmetrical with respectto MIC1 and MIC2) allow
one microphoneat a time to be selectedvia the V

bit (bit7 of Control Register CR4).

S

30/32

SO28PACKAGE MECHANICAL DATA

ST5080A

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45° (typ.)

D 17.7 18.1 0.697 0.713
E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299

L 0.4 1.27 0.016 0.050

S8°(max.)

mm inch

31/32

ST5080A

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement ofpatents or otherrights of third parties which may result from itsuse. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men­tioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex­press writtenapproval of SGS-THOMSON Microelectronics.

 1994 SGS-THOMSON Microelectronics - All RightsReserved

SGS-THOMSON Microelectronics GROUPOF COMPANIES

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32/32