Datasheet ST24E64, ST25E64 Datasheet (ST)

查询ST24E64EB1TR供应商

SERIALEXTENDED ADDRESSING COMPATIBLE

COMPATIBLEwith I2C EXTENDED
ADDRESSING

TWO WIRE SERIAL INTERFACE,
SUPPORTS400kHz PROTOCOL

1 MILLION ERASE/WRITECYCLES, OVER
the FULL SUPPLYVOLTAGERANGE

40 YEARSDATA RETENTION
SINGLESUPPLYVOLTAGE
– 4.5V to 5.5V for ST24E64 version
– 2.5V to 5.5V for ST25E64 version
WRITECONTROLFEATURE
BYTEand PAGEWRITE (up to 32 BYTES)
BYTE, RANDOM and SEQUENTIALREAD

MODES
SELFTIMED PROGRAMINGCYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCEDESD/LATCHUP

PERFORMANCES

WITH I

ST24E64
ST25E64

2

C BUS 64K (8K x 8) EEPROM

PRELIMINARYDATA

8

1

PSDIP8 (B)

0.25mm Frame

Figure 1. Logic Diagram

8

1

SO8 (M)

200mil Width

V

CC

DESCRIPTION

The ST24/25E64 are 64K bit electrically erasable
programmable memories (EEPROM), organized
as8 blocksof 1024x 8bits.TheST25E64operates
with a power supply value as low as 2.5V. Both
PlasticDual-in-LineandPlasticSmallOutlinepack-

E0-E2 SDA

SCL

3

ST24E64
ST25E64

ages are available.

WC

Table 1. Signal Names

V

E0 - E2 Chip Enable Inputs
SDA Serial Data Address Input/Output
SCL Serial Clock
WC Write Control
V

CC

V

SS

November 1996 1/16

This is preliminary information on a newproduct now in development or undergoing evaluation.Details are subject to change without notice.

Supply Voltage
Ground

SS

AI01204B

ST24E64, ST25E64

Figure2A. DIP Pin Connections

ST24E64
ST25E64

E0 V

1
2

E2

3
4

SS

Table2. Absolute MaximumRatings

Symbol Parameter Value Unit

T

A

T

STG

Ambient Operating Temperature –40 to 125 °C
Storage Temperature –65 to 150 °C

8
7
6
5

AI01205B

CC

WCE1
SCL
SDAV

(1)

Figure2B. SO Pin Connections

ST24E64
ST25E64

E0 V

1
2

E2

SS

3
4

8
7
6
5 SDAV

AI01206C

CC

WCE1
SCL

T

LEAD

V

IO

V

CC

V

ESD

Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table”Absolute Maximum Ratings”

may cause permanent damage to the device. Theseare stress ratings only and operation of the device atthese or any other
conditions above thoseindicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affectdevice reliability. Refer also to the SGS-THOMSON SURE Program and
other relevantquality documents.

2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

3. 200pF through 0Ω; EIAJ IC-121 (condition C)

Lead Temperature, Soldering (SO8)

Input or Output Voltages –0.6 to 6.5 V
Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

(PSDIP8)

(3)

DESCRIPTION (cont’d) slave devices in the I

2

Each memory is compatible with the I

Cextended
addressing standard, two wire serial interface
which uses a bi-directional data bus and serial
clock.TheST24/25E64carrya built-in4bit, unique
deviceidentification code(1010) correspondingto

2

C bus definition.The ST24/25E64behaveas

the I

operationssynchronizedby the serial clock. Read
and write operations are initiated by a START
conditiongeneratedbythebusmaster.TheSTART
conditionis followed by a stream of 4 bits(identifi­cation code 1010), 3 bit Chip Enable input to form
a 7 bit DeviceSelect, plus one read/write bit and
terminatedby an acknowledgebit.

40 sec
10 sec

(2)

2

C protocol with all memory

215
260

4000 V

500 V

°C

2/16

ST24E64, ST25E64

Table 3. Device Select Code

Device Code Chip Enable RW

Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 E2 E1 E0 RW

Note: The MSB b7 is sent first.

Table 4. OperatingModes

Mode RW bit Bytes Initial Sequence

Current Address Read ’1’ 1 START,Device Select, RW = ’1’

Random Address Read

Sequential Read ’1’ 1 to 8192 As CURRENT or RANDOM Mode
Byte Write ’0’ 1 START,Device Select, RW = ’0’
Page Write ’0’ 32 START, Device Select, RW = ’0’

’0’
’1’ reSTART, Device Select, RW = ’1’

1

Whenwritingdata tothememoryit respondsto the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
busmaster,itacknowledgesthereceiptof the data
bytes in the same way.

Data transfers are terminated with a STOP condi­tion. In this way, up to 8 ST24/25E64 may be
connectedto the same I

2

C bus and selected indi­vidually, allowing a total addressing field of 512
Kbit.

Power On Reset: V

lock out write protect. In

CC

order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset(POR) circuit is implemented.Untill the V

CC

voltagehas reachedthe POR thresholdvalue,the
internal reset is active:all operationsare disabled
and the device will not respondto any command.
In the same way, when V

drops down from the

CC

operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V

CC

mustbe appliedbefore applying any logic signal.

START, Device Select, RW = ’0’, Address,

resistorcan be connected fromtheSCLlineto V
to act as a pull up (see Figure 3)

Serial Data (SDA). The SDA pin is bi-directional
and isusedtotransferdatain oroutof the memory.
It is an opendrain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus.AresistormustbeconnectedfromtheSDA
bus line to V

to act as pull up (seeFigure 3).

CC

Chip Enable (E0 - E2). These chip enableinputs
are used to set the 3 least significant bits of the 7
bit deviceselectcode.Theymaybedrivendynami­cally or tied to V
selectcode. Note that theV

or VSSto establish the device

CC

IL

inputs are CMOS, not TTL compatible.
Write Control (WC). The Write Control feature

WC isuseful to protectthe contentsof the memory
from any erroneous erase/write cycle. The Write
Control signal is used to enable (WC at V
disable (WC at V

) the internal write protection.

IL

When pin WC is unconnected, the WC input is
internallyread as V

(seeTable 5).

IL

When WC = ’1’, Device Select and Addressbytes
are acknowledged; Data bytes are not acknow-

SIGNALSDESCRIPTION
Serial Clock (SCL). The SCLinput pin is used to

synchronize all data in and out of the memory. A

ledged.
Refer to the AN404 ApplicationNote for morede-

tailed information about WriteControl feature.

CC

and VIHlevelsfor the

)or

IH

3/16

ST24E64, ST25E64

Figure3. Maximum RLValueversusBus Capacitance(C

20

16

12

max (kΩ)

L

R

8

4

0

VCC=5V

25 50 75 100

C

(pF)

BUS

) foran I2C Bus, fC= 400kHz

BUS

V

CC

R

L

SDA

MASTER

SCL

C

BUS

R

L

C

BUS

AI01115

DEVICE OPERATION

2

I

C Bus Background

TheST24/25E64supportthe extendedaddressing

2

I

C protocol.This protocol defines any devicethat
sends data onto the bus as a transmitterand any
devicethatreadsthedataas areceiver. Thedevice
that controls the data transfer is known as the
masterand the other as the slave. The masterwill
always initiate a data transfer and will provide the
serial clock for synchronisation. The ST24/25E64
arealways slavedevices in allcommunications.

Start Condition. STARTis identified by a high to
low transition of the SDA line while the clock SCL
isstable in the high state. ASTARTcondition must
precede any command for data transfer. Except
duringa programmingcycle,the ST24/25E64con­tinuously monitor the SDA and SCL signals for a
START conditionand will not respond unless one
isgiven.

StopCondition. STOPisidentifiedbyalowtohigh
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi­nates communication between the ST24/25E64
and the bus master.A STOP condition at the end
of a Read command forces the standby state. A

STOP condition at the end of a Write command
triggersthe internalEEPROM write cycle.

Acknowledge Bit (ACK). Anacknowledgesignal
is used to indicate a successfuldata transfer.The
bustransmitter, eithermasteror slave,will release
theSDAbusaftersending8 bits of data.Duringthe
9th clock pulse the receiverpulls the SDAbus low
to acknowledgethe receiptof the 8 bitsofdata.

Data Input. During data input the ST24/25E64
sample the SDA bus signal on the rising edge of
the clock SCL. For correct device operation the
SDAsignal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL lineis low.

Device Selection. To start communication be­tween the bus master and the slave ST24/25E64,
the master must initiate a STARTcondition.The 8
bitssent after a STARTcondition aremadeup ofa
deviceselectof4bitsthatidentifiesthedevicetype,
3 Chip Enable bits and one bit for a READ (RW =

1) or WRITE (RW = 0) operation. There are two
modesboth for read andwrite. Theseare summa­risedinTable4 anddescribedhereafter.Acommu­nicationbetweenthemasterandtheslaveis ended
witha STOP condition.

4/16

ST24E64, ST25E64

Table5. InputParameters

(1)

(TA=25°C, f =400 kHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IN

Z

WCL

Z

WCH

t

LP

Note: 1. Sampled only,not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance VIN≤ 0.3 V
WC Input Impedance VIN≥ 0.7 V
Low-pass filter input time constant

(SDAand SCL)

CC

CC

520kΩ

500 kΩ

100 ns

Table 6. DC Characteristics

= –40 to 85°C or 0to 70 °C; VCC=4.5V to 5.5Vor 2.5V to 5.5V)

(T

A

Symbol Parameter Test Condition Min Max Unit

I

LI

I

LO

I

CC

Input Leakage Current
(SCL, SDA, E0-E2)

Output LeakageCurrent

Supply Current (ST24 series)
Supply Current (ST25 series) 1 mA

0V ≤ V

0V ≤ V

IN

OUT

≤ V

≤ V

CC

CC

SDAin Hi-Z
f

= 400kHz

C

(Rise/Fall time < 30ns)

±2 µA

±2 µA

2mA

I

I

V

V

V

CC1

CC2

V

V

OL

V

IN=VSS

Supply Current (Standby)
(ST24 series)

V

IN=VSS

V

=5V,fC= 400kHz

CC

V

IN=VSS

Supply Current (Standby)
(ST25 series)

IL

IH

IL

IH

Input Low Voltage (SCL, SDA) –0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage (E0-E2, WC) –0.3 0.5 V
Input High Voltage (E0-E2, WC) VCC– 0.5 VCC+1 V

V

IN=VSS

V

= 2.5V,fC= 400kHz

CC

or VCC,

V

=5V

CC

or VCC,

or VCC,

V

= 2.5V

CC

or VCC,

CC

100 µA

300 µA

5 µA

50 µA

CC

V

VCC+1 V

Output Low Voltage IOL= 3mA, VCC= 5V 0.4 V
Output Low Voltage (ST25 series) I

= 2.1mA, VCC= 2.5V 0.4 V

OL

5/16

ST24E64, ST25E64

Table 7. AC Characteristics

(T

= –40 to 85 °C or0 to 70 °C; VCC= 4.5V to 5.5V or 2.5V to 5.5V)

A

Symbol Alt Parameter Min Max Unit

t

CH1CH2

t

CL1CL2

(1)

t

DH1DH2

(1)

t

DL1DL1

(2)

t

CHDX

t

CHCL

t

DLCL

t

CLDX

t

CLCH

t

DXCX

t

CHDH

t

DHDL

(3)

t

CLQV

t

CLQX

f

C

t

W

Notes: 1. Sampled only, not 100% tested.

2. For a reSTART condition, or following a write cycle.

3. The minimum value delays the falling/rising edge of SDAaway from SCL = 1 in order to avoidunwanted STARTand/or STOP
conditions.

t
t
t
t

t

SU:STA

t

HIGH

t

HD:STA

t

HD:DAT

t

LOW

t

SU:DAT

t

SU:STO

t

BUF

t

AA

t

DH

f

SCL

t

WR

R

F

R

F

Clock Rise Time 300 ns
Clock Fall Time 300 ns
SDA Rise Time 20 300 ns
SDA Fall Time 20 300 ns
Clock High to InputTransition 600 ns
Clock Pulse Width High 600 ns
Input Low to Clock Low (START) 600 ns
Clock Low to Input Transition 0 µs
Clock Pulse Width Low 1.3 µs
Input Transition to Clock Transition 100 ns
Clock High to Input High (STOP) 600 ns
Input High to Input Low (Bus Free) 1.3 µs
Clock Low to Next Data Out Valid 200 1000 ns
Data Out Hold Time 200 ns
Clock Frequency 400 kHz
Write Time 10 ms

AC MEASUREMENT CONDITIONS

Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages 0.2V
Input and Output Timing Ref. Voltages 0.3VCCto 0.7V

CC

to 0.8V

CC

CC

Figure4. AC TestingInput Output Waveforms

0.8V

6/16

0.2V

CC

CC

0.7V

0.3V

AI00825

CC

CC

DEVICEOPERATION(cont’d)
MemoryAddressing. A data byte in the memory

is addressed through 2 bytes of addressinforma­tion. The MostSignificant Byte is sent first andthe
Leastsignificant Byte is sent after. The Least Sig­nificant Byte addresses a block of 256 bytes, bits
b12,b11,b10,b9,b8 of the Most Significant Byte
selectoneblock among 32 blocks(one blockis 256
bytes).

MostSignificant Byte

X X X b12 b11 b10 b9 b8

X = Don’t Care.

Least SignificantByte

b7 b6 b5 b4 b3 b2 b1 b0

Figure5. ACWaveforms

ST24E64, ST25E64

SCL

SDA IN

SCL

SDA OUT

SCL

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLQV tCLQX

tDHDL

tCLDX

SDA

INPUT

DATA VALID

DATA OUTPUT

SDA

CHANGE

tW

tCLCH

tDXCX

tCHDH

tDHDL

STOP &

BUS FREE

SDA IN

tCHDH

STOP

CONDITION

WRITE CYCLE

tCHDX

START

CONDITION

AI00795

7/16

ST24E64, ST25E64

Figure6. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

123 789

MSB

123 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

Write Operations

Following a STARTcondition the master sends a
deviceselect code withthe RW bit reset to ’0’. The
ST24/25E64 acknowledge this and waits for 2
bytes of address. These 2 address bytes (8 bits
each)provideaccesstoanyof the 32 blocksof 256
bytes each. Writing in the ST24/25E64 may be
inhibitedif input pin WC is takenhigh.

For the ST24/25E64versions, any writecommand
with WC = ’1’ (during a period of time from the
START condition untill the end of the 2 Bytes
Address) will not modify data and will NOT be
acknowledgedon data bytes, as in Figure 9.

Byte Write. In the Byte Write mode the master
sendsonedatabyte,whichisacknowledgedby the

8/16

AI00792

ST24/25E64. The master then terminates the
transfer by generatinga STOPcondition.

PageWrite. The Page Writemode allows up to 32
bytesto be written in a single write cycle,provided
thattheyare all locatedinthe samerowof 32bytes
in the memory, that is the same Address bits (b12
tob5).Themastersendsone upto32 bytesofdata,
whichareeachacknowledgedby the ST24/25E64.
After each byte is transfered, the internal byte
address counter (5 Least Significant Bits only) is
incremented. The transfer is terminated by the
mastergeneratingaSTOPcondition.Caremustbe
taken to avoid address counter ’roll-over’ which
couldresult in data being overwritten.Notethat for
anywritemode,thegenerationbythemasterofthe
STOP condition starts the internal memory pro-

ST24E64, ST25E64

gram cycle. This STOP condition will trigger an
internal memory program cycle only if the STOP
conditionis internally decoded right after the ACK
bit; any STOP condition decoded out of this ”10th
bit” time slot will not trigger the internal program­mingcycle.Allinputsaredisableduntilthecomple­tion of this cycle and the ST24/25E64 will not
respondto any request.

Minimizing System Delay by Polling On ACK.

During the internal Write cycle, the ST24/25E64
disableitself from the bus in order to copy the data
fromthe internal latches to thememory cells. The
maximumvalue oftheWritetime(t

) isgiveninthe

W

AC Characteristics table, this timingvalue maybe
reducedbyan ACKpollingsequenceissuedby the
master.

Figure7. WriteCycle Polling using ACK

WRITE

Cycle

in Progress

START Condition

The sequenceis:
– Initialcondition:a Write is in progress (see Fig-

ure 7).

– Step 1: the Masterissues a STARTcondition

followed by a Device Selectbyte. (1st byte of
the newinstruction)

– Step 2: if the ST24/25E64are internallywrit-

ing, no ACK will be returned.The Master goes
back to Step1.If the ST24/25E64have termi­nated the internalwriting, it will issue an ACK.
The ST24/25E64are ready to receive the sec­ond partof the instruction(the first byte of this
instructionwas already sentduring Step1).

First byte of
with RW = 0
decoded by ST24xxx

instruction

already

ReSTART

STOP

DEVICE SELECT

with RW = 0

ACK

NO

Returned

YES

Next

Operation is

Addressing the

Memory

WRITE Operation

YESNO

Proceed

Send

Byte Address

Proceed

Random

Address

READ Operation

AI01099B

9/16

ST24E64, ST25E64

Figure8. Write Modes Sequence with Write Control = 0

WC

ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

WC

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont’d)

ACKACK

PAGE WRITE
(cont’d)

DATA IN N

ACK ACK ACK

STOP

DATA IN 2

STOP

Read Operations

On delivery,the memory content is set at all ”1’s”
(or FFh).

Current Address Read. The ST24/25E64 have
an internal 13 bits address counter. Each time a
byte is read, this counter is incremented.For the
Current Address Read mode, following a START
condition, the master sends a Device Select with
theRWbit setto’1’.TheST24/25E64acknowledge
thisand outputs thebyte addressedby the internal
addresscounter.Thiscounteris then incremented.
The master does NOT acknowledge the byte out­put, but terminates the transfer with a STOPcon­dition.

10/16

AI01106

Random Address Read. A dummy write is per­formed to load the address into the address
counter,see Figure 10. Thisis followed byanother
START condition from the master and the byte
address repeated with the RW bit set to ’1’. The
ST24/25E64 acknowledge this and outputs the
byte addressed. The master does NOT acknow­ledge the byte output, but terminates the transfer
witha STOP condition.

SequentialRead. This mode can be initiatedwith
either a Current Address Read or a Random Ad­dress Read. However, in this case the master
DOES acknowledge the data byte output and the
ST24/25E64 continue to output the next byte in

Figure9. WriteModes Sequence with Write Control = 1

WC

ACK ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

ST24E64, ST25E64

R/W

START

WC

ACK ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont’d)

NO ACK NO ACK

PAGE WRITE
(cont’d)

DATA IN N

STOP

STOP

DATA IN 2

AI01120

sequence. To terminate the stream of bytes, the
master must NOT acknowledgethe last byte out­put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat­ically incremented after each byte output. After a
count of the last memory address, the address

counterwill’roll-over’ andthe memorywillcontinue
to output data.

Acknowledge in Read Mode. In all read modes
the ST24/25E64 wait for an acknowledge during
the 9th bittime. If the masterdoes notpull the SDA
linelowduringthistime,theST24/25E64terminate
the data transferand switch to a standbystate.

11/16

ST24E64, ST25E64

Figure10. Read Modes Sequence

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK ACK

DEV SEL * BYTE ADDR BYTE ADDR

NO ACK

STOP

ACK ACK ACK

DEV SEL * DATA OUT

R/W

START

DATA OUT N

STOP

ACK ACK

DEV SEL * DATA OUT 1

NO ACK

STOP

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note: * The 7 Most Significantbits of DEV SEL bytes of a Random Read (1st byte and 4th byte)must be identical.

START

R/W

AI01105B

12/16

ORDERING INFORMATIONSCHEME

Example: ST24E64 M 1 TR

ST24E64, ST25E64

Operating Voltage

24 4.5V to 5.5V
25 2.5V to 5.5V

Note: 3 * Temperature Range on special request only.

Range

E Extended

Addressing

Package

B PSDIP8

0.25mm Frame

M SO8

200mil Width

Temperature Range

1 0 to 70 °C
6 –40 to 85 °C

3 * –40 to 125 °C

Option

TR Tape& Reel

Packing

Parts are shipped with the memorycontent set at all ”1’s” (FFh).
For a list of available options (Operating Voltage,Range, Package, etc...) refer to the current Memory

Shortformcatalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office

nearestto you.

13/16

ST24E64, ST25E64

PSDIP8 - 8 pin Plastic Skinny DIP,0.25mm lead frame

Symb

Typ Min Max Typ Min Max

A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.150

N8 8

PSDIP8

mm inches

Drawing is not o scale

14/16

A2A1A

L

B

e1

B1

D

N

C

eA
eB

E1 E

1

PSDIP-a

ST24E64, ST25E64

SO8 - 8 lead Plastic Small Outline, 200 mils body width

Symb

Typ Min Max Typ Min Max

A 2.03 0.080
A1 0.10 0.25 0.004 0.010
A2 1.78 0.070

B 0.35 0.45 0.014 0.018

C 0.20 – – 0.008 – –
D 5.15 5.35 0.203 0.211

E 5.20 5.40 0.205 0.213

e 1.27 – – 0.050 – –

H 7.70 8.10 0.303 0.319

L 0.50 0.80 0.020 0.031

α 0° 10° 0° 10°

N8 8

CP 0.10 0.004

SO8b

mm inches

Drawing is notto scale

A2

A

C

B

e

CP

D

N

E

H

1

LA1 α

SO-b

15/16

ST24E64, ST25E64

Information furnished is believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patentor patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for useascritical components inlife supportdevices or systems without express
written approval of SGS-THOMSON Microelectronics.

 1996 SGS-THOMSON Microelectronics - AllRights Reserved

Purchase of I

2

I

C Patent.Rights to use these components in an I2C system, is granted provided that the system conformsto

Australia - Brazil -Canada - China- France - Germany - Hong Kong - Italy - Japan - Korea- Malaysia - Malta - Morocco - The Netherlands -

2

C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips

2

the I

C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Singapore- Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom- U.S.A.

16/16