Datasheet ST25E16, ST24E16 Datasheet (SGS Thomson Microelectronics)

16 Kbit Serial I2C EEPROM with Ex tende d Addressin g

COMPATIBLE with I2C EXTENDED
ADDRESSING

TWO WIRE SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL

1 MILLION ERASE/WRI T E CYCLES, O VER
the FULL SUPPLY VOLTAGE RANG E

40 YEARS DA TA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST24E16 version
– 2.5V to 5.5V for ST25E16 version
WRITE CONTROL FEATURE
BYTE and PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ

MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCE D ESD/LATCH UP

PERFORMANCES

8

1

PSDIP8 (B)

0.25mm Frame

Figure 1. Logic Diagram

ST24E16

ST25E16

8

1

SO8 (M)

150mil Width

DESCRIPTION

V

CC

The ST24/25E16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. It is manufactured in
STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur­ance of one million erase/write cycles over the full
supply voltage range, and a data retention of over

E0-E2 SDA

SCL

3

ST24E16
ST25E16

40 years. The ST25E16 operates with a power
supply value as low as 2.5V.

WC

T ab le 1. Signal Names

V

E0 - E2 Chip Enable Inputs
SDA Serial Data Address Input/Output
SCL Serial Clock
WC Write Control
V

CC

V

SS

February 1999 1/16

Supply Voltage
Ground

SS

AI01102B

ST24E16, ST25E16

Figure 2A. DIP Pin Connections

ST24E16
ST25E16

1

E0 V

2
3

E2

4

SS

T ab le 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

Ambient Operating Temperature –40 to 125
Storage Temperature –65 to 150

8
7
6
5

AI01103B

CC

WCE1
SCL
SDAV

(1)

Figure 2B. SO Pin Connections

ST24E16
ST25E16

1

E0 V

2
3

E2

SS

4

8
7
6
5

AI01104C

CC

WCE1
SCL
SDAV

C

°

C

°

T

LEAD

V

IO

V

CC

V

ESD

Notes:

1. Except for the rating "Operating T emperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.

2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

3. 200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d) the I

Lead T e mperature, Soldering (SO8)

Input or Output Voltages –0.6 to 6.5 V
Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

(PSDIP8)

(3)

2

C bus definition. The ST24/25E16 behave as

slave devices in the I
Both Plastic Dual-in-Line and Plastic Small Out line
packages are available.

2

Each memory is compatible with the I

C extended
addressing standard, two wire serial interface
which uses a bi-directional data bus and serial
clock. The ST24/25E16 carry a built-in 4 bit, unique
device identification code (1010) corresponding to

operations synchronized by the serial clock. Read
and write operations are initiated by a START
condition generated by the bus master. The ST ART
condition is followed by a stream of 4 bits (identifi­cation code 1010), 3 bit Chip Enable input to form
a 7 bit Device Select, plus one r ead/write bit and
terminated by an acknowledge bit.

40 sec
10 sec

(2)

2

C protocol with all memory

215
260

4000 V

500 V

C

°

2/16

ST24E16, ST25E16

T ab le 3. Device Select Code

Device Code Chip Enable RW

Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 E2 E1 E0 R

Note:

The MSB b7 is sent first.

T ab le 4. Operating Modes

Mode RW bit Bytes Initial Sequence

Current Address Read ’1’ 1 START, Device Select, R

Random Address Read

Sequential Read ’1’ 1 to 2048 As CURRENT or RANDOM Mode
Byte Write ’0’ 1 START, Device Select, R
Page Write ’0’ 16 START, Device Select, R

’0’
’1’ reSTART, Device Select, R

1

When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way.

Data transfers are terminated with a STOP condi­tion. In this way, up to 8 ST24/25E16 may be
connected to the same I

2

C bus and selected indi­vidually, allowing a total addressing field of 128
Kbit.

Power On Reset: V

lock out write protect . In

CC

order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V

CC

voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any c ommand.
In the same way, when V

drops down from the

CC

operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V

CC

must be applied before applying any logic signal.

START, Device Select, R

Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V

to act as pull up (see Figure 3).

CC

Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits of the 7
bit device select code. They may be driven dynami­cally or tied to V

CC

select code. Note that the V
inputs are CMOS, not TTL compatible.

Write Control (

WC). The Write Control feature

WC is useful to protect the contents of the memory
from any erroneous erase/write cycle. The Write
Control signal is used to enable (
disable (

WC at VIL) the internal write protection.
The devices with this Write Control feature no
longer supports the multibyte mode of oper ation.
When unconnected, the

(see Table 5).

as V

IL

When

WC = ’1’, Device Select and Address bytes

W = ’1’
W = ’0’, Address,

W = ’1’

W = ’0’
W = ’0’

or VSS to establish the device

and VIH levels for the

IL

WC at VIH) or

WC input is internally read

are acknowledged; Data bytes are not acnowl-

SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V

CC

edged.
Refer to the AN404 Application Note for more de-

tailed information about Write Control feature.

to act as a pull up (see Figure 3)

W

3/16

ST24E16, ST25E16

Figure 3. Maximum RL Value versus Bus Capacitance (C

20

16

12

max (kΩ)

L

R

8

4

0

VCC = 5V

25 50 75 100

C

(pF)

BUS

) for an I2C Bus, fC = 400kHz

BUS

V

CC

R

L

SDA

MASTER

SCL

C

BUS

R

L

C

BUS

AI01115

DEVICE O PERATION

2

I

C Bus Background

The ST24/25E16 support the extended addr essing

2

C protocol. This protocol defines any device that

I
sends data onto the bus as a transmitter and any
device that reads the data as a rec eiver.The device
that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The ST24/25E16
are always slave devices in all communications.

Start Condition . START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A ST AR T condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25E16 con­tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.

Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi­nates communication between the ST24/25E16
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A

STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a suc cessful data transfer. The
bus transmitter, eit her master or s lave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse the receiver pulls the SDA bus low
to acknowledge the receipt of the 8 bits of data.

Data Input. During data input the ST24/25E16
sample the SDA bus signal on the rising edge of
the clock SCL. For correct device operation the
SDA s ignal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL line is low.

Device Selection. To start communication be­tween the bus master and the slave ST24/25E16,
the master must initiate a START condition. The 8
bits sent after a STA RT c ondition are made up of a
device select of 4 bits that identifies the device type,
3 Chip Enable bits and one bit for a READ (R

1) or WRITE (R

W = 0) operation. There are two

W =

modes both for read and write. These are summa­rised in T able 4 and described hereafter. A commu­nication between the master and the slave is ended
with a STOP condition.

4/16

ST24E16, ST25E16

Table 5. Input Parameters

(1)

(TA = 25 °C, f = 400 kHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IN

Z

WCL

Z

WCH

t

LP

Note:

1. Sampled only, not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance VIN ≤ 0.3 V
WC Input Impedance VIN ≥ 0.7 V
Low-pass filter input time constant

(SDA and SCL)

CC

CC

520k

500 k

100 ns

T ab le 6. DC Characteristics

(T

= 0 to 70 ° or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)

A

Symbol Parameter Test Condition Min Max Unit

I

LI

I

LO

I

CC

Input Leakage Current
(SCL, SDA, E0-E2)

Output Leakage Current

0V ≤ V

0V ≤ V

Supply Current (ST24 series)
Supply Current (ST25 series) 1 mA

(Rise/Fall time < 30ns)

≤ V

IN

≤ VCC

OUT

SDA in Hi-Z
f

= 400kHz

C

CC

2

±

2

±

2mA

Ω
Ω

A

µ

A

µ

I

CC1

I

CC2

V

V

V

V

V

OL

VIN = VSS or VCC,

= 5V

V

Supply Current (Standby)
(ST24 series)

V

CC

V

= VSS or VCC,

IN

= 5V, fC = 400kHz

CC

VIN = VSS or VCC,

= 2.5V

V

Supply Current (Standby)
(ST25 series)

V

IL

IH

IL

IH

Input Low Voltage (SCL, SDA) –0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage (E0-E2, WC) –0.3 0.5 V
Input High Voltage (E0-E2, WC) VCC – 0.5 VCC + 1 V

CC

V

= VSS or VCC,

IN

= 2.5V, fC = 400kHz

CC

CC

100

300

5

50

CC

µ

µ

µ

µ

VCC + 1 V

A

A

A

A

V

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
Output Low Voltage (ST25 series) I

= 2.1mA, VCC = 2.5V 0.4 V

OL

5/16

ST24E16, ST25E16

T ab le 7. AC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)

A

Symbol Alt Parameter Min Max Unit

t

CH1CH2

t

CL1CL2

(1)

t

DH1DH2

(1)

t

DL1DL1

(2)

t

CHDX

t

CHCL

t

DLCL

t

CLDX

t

CLCH

t

DXCX

t

CHDH

t

DHDL

(3)

t

CLQV

t

CLQX

f

C

t

tWRWrite Time 10 ms

W

Notes:

1. Sampled only, not 100% tested.

2. For a reSTART condition, or following a write cycle.

3. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.

t

R

t

F

t

R

t

F

t

SU:STA

t

HIGH

t

HD:STA

t

HD:DAT

t

LOW

t

SU:DAT

t

SU:STO

t

BUF

t

AA

t

DH

f

SCL

Clock Rise Time 300 ns
Clock Fall Time 300 ns
SDA Rise Time 20 300 ns
SDA Fall Time 20 300 ns
Clock High to Input Transition 600 ns
Clock Pulse Width High 600 ns
Input Low to Clock Low (START) 600 ns
Clock Low to Input Transition 0
Clock Pulse Width Low 1.3
Input Transition to Clock Transition 100 ns
Clock High to Input High (STOP) 600 ns
Input High to Input Low (Bus Free) 1.3
Clock Low to Next Data Out Valid 200 1000 ns
Data Out Hold Time 200 ns
Clock Frequency 400 kHz

s

µ

s

µ

s

µ

Tabl e 8. AC Measurement Conditions

Input Rise and Fall Times
Input Pulse Voltages 0.2V
Input and Output Timing Ref.

Voltages

50ns

≤

0.3V

to 0.8V

CC

to 0.7V

CC

CC

CC

Figure 4. AC Testing Input Output Waveforms

0.8V

6/16

0.2V

CC

CC

0.7V

0.3V

AI00825

CC

CC

DEVICE OPERATION (cont’d)
Memory Addressing. A data byt e in the memory

is addressed through 2 bytes of address inf orma­tion. The Most Significant Byte is sent first and the
Least significant Byte is sent after. The Least Sig­nificant Byte addresses a block of 256 bytes, bits
b10,b9,b8 of the Most Significant Byte select one
block among 8 blocks (one block is 256 bytes).

Most Significant Byte

XXXXXb10b9b8

X = Don’t Care.

Least Significant Byte

b7 b6 b5 b4 b3 b2 b1 b0

Figure 5. AC Waveforms

ST24E16, ST25E16

SCL

SDA IN

SCL

SDA OUT

SCL

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLQV tCLQX

tCLDX

SDA

INPUT

DATA VALID

DATA OUTPUT

SDA

CHANGE

tW

tCLCH

tDXCX

tCHDH

tDHDL

STOP &

BUS FREE

SDA IN

tCHDH

STOP

CONDITION

WRITE CYCLE

tCHDX

START

CONDITION

AI00795B

7/16

ST24E16, ST25E16

Figure 6. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

AI00792

Write Operations

Following a START condition the master sends a
device select code with the R

W bit reset to ’0’. The
ST24/25E16 acknowledge this and waits for 2
bytes of address. These 2 address bytes (8 bits
each) provide access to any of the 8 blocks of 256
bytes each. Writing in the ST24/25E16 may be
inhibited if input pin

WC is taken high.

For the ST24/25E16 v ersions, any write command

WC = ’1’ (during a period of time from the

with
START condition untill the end of the 2 Bytes
Address) will not modify data and will NOT be
acknowledged on data bytes, as in Figure 9.

8/16

Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
ST24/25E16. The master then terminates the
transfer by generating a STOP condition.

Page Write. The Page Write mode allows up to 16
bytes to be written in a single write cycle, provided
that they are all located in the sam e row of 16 bytes
in the memory, that is the same Address bits (b10­b4). The master sends one up to 16 bytes of data,
which are each acknowledged by the ST24/25E16.
After each byte is transfered, the internal byte
address counter (4 Least Significant Bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which

ST24E16, ST25E16

could result in data being overwritten. Note that for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro­gram cycle. All inputs are disabled until the comple­tion of this cycle and the ST24/25E16 will not
respond to any request.

Minimizing System Delay by Polling On ACK.

During the internal Write cycle, the ST24/25E16
disable itself from the bus in order to copy the data
from the internal latches to the m emory cells. The
maximum value of the Write time (t

) is given in the

W

AC Characteristics table, this timing value may be
reduced by an ACK polling sequence is sued by the
master.

Figure 7. Write Cycle Polling using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

The sequence is:
– Initial condition: a Write is in progress (see Fig-

ure 7).

– Step 1: the Master issues a START condition

followed by a Device Select byte. (1st byte of
the new instruction)

– Step 2: if the ST24/25E16 are internally writ-

ing, no ACK will be returned. The Master goes
back to Step1. If the ST24/25E16 have termi­nated the internal writing, it will issue an ACK.
The ST24/25E16 are ready to receive the sec­ond part of the instruction (the first byte of this
instruction was already sent during Step1).

First byte of instruction
with RW = 0 already
decoded by ST24xxx

ReSTART

STOP

ACK

NO

Returned

Next

Operation is

Addressing the

Memory

YES

YESNO

Proceed

WRITE Operation

Send

Byte Address

Proceed

Random Address

READ Operation

AI01099B

9/16

ST24E16, ST25E16

Figure 8. Write Modes Sequence with Write Control = 0

WC

ACK ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

WC

ACK ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

NO ACK NO ACK

PAGE WRITE
(cont'd)

DATA IN N

STOP

STOP

DATA IN 2

AI01120B

Read Operations

On delivery, the memory content is set at all "1’s"
(or FFh).

Current Address Read. The ST24/25E16 have
an internal 11 bits address counter. Each time a
byte is read, this counter is incremented. For the
Current Address Read mode, following a START
condition, the master sends a Device Select with
the R

W bit set to ’1’. The ST24/25E16 acknowledge
this and outputs the byte addressed by the internal
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out­put, but terminates the tr ansfer with a STOP con­dition.

10/16

Random Address Read. A dummy write is per­formed to load the address into the address
counter, see Figure 10. This is followed by another
START condition from the master and the byte
address repeated with the R

W bit set to ’1’. The
ST24/25E16 acknowledge this and outputs the
byte addressed. The master does NOT acknow­ledge the byte output, but t erminates the transfer
with a STOP condition.

Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad­dress Read. However, in this case the master
DOES acknowledge the data byte output and t he
ST24/25E16 continue to output the next byte in

Figure 9. Write Modes Sequence with Write Control = 1

WC

ST24E16, ST25E16

ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

WC

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

ACKACK

PAGE WRITE
(cont'd)

DATA IN N

ACK ACK ACK

STOP

DATA IN 2

STOP

sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out­put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat­ically incremented after each byte output. After a
count of the last memory address, the address

AI01106B

counter will ’roll-over’ and the memory w ill continue
to output data.

Acknowledge in Read Mode. In all read modes
the ST24/25E16 wait for an acknowledge during
the 9th bit time. If the master does not pull the SDA
line low during this time, the ST24/25E16 terminate
the data transfer and switch to a s tandby state.

11/16

ST24E16, ST25E16

Figure 10. Read Modes Sequence

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK ACK

DEV SEL * BYTE ADDR BYTE ADDR

NO ACK

STOP

ACK ACK ACK

DEV SEL * DATA OUT

R/W

START

DATA OUT N

STOP

ACK ACK

DEV SEL * DATA OUT 1

NO ACK

STOP

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note:

* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 4th byte) must be identical.

START

R/W

AI01105C

12/16

ORDERING INFORMATION SCHEME

Example: ST24E16 M 1 TR

ST24E16, ST25E16

Operating Voltage

24 4.5V to 5.5V
25 2.5V to 5.5V

Note:

1. Temperature range on special request only.

Range

E Extended

Addressing

Package

B PSDIP8

0.25mm Frame

M SO8

150mil Width

Temperature Range

1 0 to 70 °C
6 –40 to 85 °C

(1)

3

–40 to 125 °C

Option

TR Tape & Reel

Packing

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.

13/16

ST24E16, ST25E16

PSDIP8 - 8 pin Plastic S kinny DIP, 0.25mm lead frame

Symb

Typ Min Max Typ Min Max

A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –

E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB – 10.00 – 0.394

L 3.00 3.80 0.118 0.150

N8 8

mm inches

Drawing is not to scale.

14/16

A2

A1AL

B

e1

B1

D

N

C

eA

eB

E1 E

1

PSDIP-a

ST24E16, ST25E16

SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157

e1.27– –0.050– –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035

α

N8 8

CP 0.10 0.004

mm inches

0

°

8

°

0

°

8

°

Drawing is not to scale.

B

SO-a

h x 45˚

A

C

e

CP

D

N

E

H

1

LA1 α

15/16

ST24E16, ST25E16

Information furnished is believ ed to be accurate and reliable. How ever, STMicroelectronics ass umes no responsib ility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is gr an ted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and repl aces all information previous ly supplied. STMicroelect ronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelect roni cs

© 1999 STMicroelectronics - All Rights Reserved

All other names are the property of their respective owners

2

2

I

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Purchase of I

C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to

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C Components by STMicroelectroni cs, conveys a license under the Philips

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C Standard Specifications as defined by Philips.

the I

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