Datasheet ST25W02, ST25C02, ST24W02, ST24C02 Datasheet (SGS Thomson Microelectronics)

ST24/25C02, ST24C02R

ST24/25W02

SERIAL 2K (256 x 8) EEPROM

NOT FOR NEW DESIGN

November 1997 1/16

This is information on a product still in production but not recommended for new design

AI00788D

3

E0-E2 SDA

V

CC

ST24x02
ST25x02

ST24C02R

MODE/WC*

SCL

V

SS

Figure 1. Logic Diag ra m

1 MILLION ERASE /WRI T E CYCLES with
40 YEARS DATA RETENTION

SINGL E SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x02 v ersions
– 2.5V to 5.5V for ST25x02 versions
– 1.8V to 5.5V for ST24C02R version only
HARDWARE WRITE CONTROL VERSIONS:

ST24W02 and ST25W02
TWO WIRE SERIAL INTERFACE, FULLY I2C

BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4

BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQ UE NTIA L READ

MODES
SELF TIME D PRO G RA MM ING CY C LE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATC H-UP

PERFORMA NCES

ST24C/W02 are replaced by the M24C02
ST25C/W02 are replaced by the M24C02-W
ST24C02R is replaced by the M24C02-R

DESCRIP TION

This specification cov ers a range of 2K bits I

2

C bus
EEPROM products, the ST24/25C02, the
ST24C02R and ST24/25W02. In the text, products
are referred t o as ST24/25x02, where " x" is: " C" for
Standard version and "W" for hardware Write Con­trol version.

E0-E2 Chip Enable Inputs
SDA Serial Data Address Input/Output
SCL Serial Clock

MODE

Multibyte/Page Write Mode

(C version)
WC Write Control (W version)
V

CC

Supply Voltage
V

SS

Ground

T able 1. Signal Names

8

1

SO8 (M)

150mil Width

8

1

PSDIP8 (B)

0.25mm Frame

Note: WC signal is only available for ST24/25W02 products.

The ST24/25x02 are 2K bit electrically erasable
programmable memories (EEPROM), organized
as 256 x 8 bits. They are manufactured in SGS­THOMSON’s Hi-Endurance Advanced CMOS
technology which guarantees an endurance of one
million erase/write cycles with a data retention of
40 years. The memories operate with a power
supply value as low as 1.8V for the ST24C02R only .

Both Plastic Dual- in-Line and Plastic Small Out line
packages are available.

The memories are compatible with the I

2

C stand-

ard, two wire serial interface whic h uses a bi- direc-

tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I

2

C bus defini­tion. This is used t ogether with 3 chip enable inputs
(E2, E1, E0) so that up to 8 x 2K devices may be
attached to the I

2

C bus and selected individually.

The memories behave as a s lave devic e in the I

2

C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master . The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.

SDAV

SS

SCL

MODE/WCE1

E0 V

CC

E2

AI00789D

ST24x02
ST25x02

ST24C02R

1
2
3
4

8
7
6
5

Figure 2A. DIP Pin Connect io ns

1

AI00790E

2
3
4

8
7
6
5

SDAV

SS

SCL

MODE/WCE1

E0 V

CC

E2

ST24x02
ST25x02

ST24C02R

Figure 2B. SO Pin Connecti ons

DESCRIP TION (co nt’d)

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature –40 to 125 °C

T

STG

Storage Temperature –65 to 150 °C

T

LEAD

Lead Temperature, Soldering (SO8 package)

(PSDIP8 package)

40 sec
10 sec

215
260

°C

V

IO

Input or Output Voltages –0.6 to 6.5 V

V

CC

Supply Voltage –0.3 to 6.5 V

V

ESD

Electrostatic Discharge Voltage (Human Body model)

(2)

4000 V

Electrostatic Discharge Voltage (Machine model)

(3)

500 V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicat ed in the Operati ng sections of this specific ati on is not implied. Expos ure to Absolut e Maximum
Rating conditions for extended periods may affect device rel i abi lity. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

T ab le 2. Absolut e Maximu m Ra t ings

(1)

2/16

ST24/25C02, ST24C02R, ST24/25W02

Mode RW bit MODE Bytes Initial Sequence

Current Address Read ’1’ X 1 START, Device Select, R

W = ’1’

Random Address Read

’0’

X1

START, Device Select, R

W = ’0’, Address,

’1’ reSTART, Device Select, R

W = ’1’
Sequential Read ’1’ X 1 to 256 Similar to Current or Random Mode
Byte Write ’0’ X 1 START, Device Select, R

W = ’0’

Multibyte Write

(2)

’0’ V

IH

4 START, Device Select, RW = ’0’

Page Write ’0’ V

IL

8 START, Device Select, RW = ’0’

Notes: 1. X = VIH or V

IL

2. Multibyte Write not available in ST24/25W02 versions.

T ab le 4. Operating Modes

(1)

Device Code Chip Enable RW

Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 E2 E1 E0 R

W

Note: The MSB b7 is sent first.

T ab le 3. Device Select Co de

When writing data to the mem ory it responds to th e
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master , it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi­nated with a STOP condition.

Power On Reset: V

CC

lock out write protect. In

order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V

CC

voltage has reached the POR threshold v alue, th e
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V

CC

drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V

CC

must be applied before applying any logic signal.

SIGNAL DES CRIPTIONS
Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V

CC

to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory .
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A res istor must be connected from the SDA
bus line to V

CC

to act as pull up (see Figure 3).

Chip Enable (E2 - E0). These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or t ied to V

CC

or VSS to

establish the device select code.
Mode (MO DE). T he MODE input is available on pin

7 (see also

WC feature) and may be driven dynami-

cally. It must be at V

IL

or VIH for the Byte Write

mode, V

IH

for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as a V

IH

(Multibyte Write mode).

Write Control (

WC). An hardware Write Control

feature (

WC) is offered only for ST24W02 and
ST25W02 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cy cle. The W rite Control s ig­nal is used to enable (

WC = VIH) or disable (WC =

V

IL

) the internal write protection. When uncon-

nected, the

WC input is internally read as VIL and

the memory area is not write protected.

3/16

ST24/25C02, ST24C02R, ST24/25W02

AI01100

V

CC

C

BUS

SDA

R

L

MASTER

R

L

SCL

C

BUS

100 200 300 400

0

4

8

12

16

20

C

BUS

(pF)

R

L

max (kΩ)

VCC = 5V

Figure 3. Maximum RL Value versus Bus Capacitance (C

BUS

) for an I2C Bus

The devices with this Write Control feature no
longer support the Multibyte Write mode of opera­tion, however all other write modes are fully sup­ported.

Refer to the AN404 Application Note for more de­tailed information about Write Contr ol feature.

DEVICE OPER ATION
I

2

C Bus Background

The ST24/25x02 support the I

2

C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device t hat reads
the data as a receiver . The device that c ontrols th e
data transfer is known as the master and the other
as the slave. The master will alway s initiate a dat a
transfer and will provide the serial clock for syn­chronisation. The ST24/25x02 are always slave
devices in all communications.

Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x02 con­tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.

Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi­nates communication between the ST24/25x02
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter , either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.

Data Input. During data input the ST24/25x02
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera­tion the SDA signal must be stable during the c lock
low to high transition and the data must change
ONLY when the SCL line is lo w.

Memory Addressi ng. To start com munic ation be­tween the bus master and the slave ST24/25x02,
the master must initiate a ST ART co ndition. Follow­ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.

SIGNAL DES CRIPTIONS (cont’d)

4/16

ST24/25C02, ST24C02R, ST24/25W02

Symbol Parameter Test Condition Min Max Unit

C

IN

Input Capacitance (SDA) 8 pF

C

IN

Input Capacitance (other pins) 6 pF

Z

WCL

WC Input Impedance (ST24/25W02) VIN ≤ 0.3 V

CC

520kΩ

Z

WCH

WC Input Impedance (ST24/25W02) VIN ≥ 0.7 V

CC

500 kΩ

t

LP

Low-pass filter input time constant
(SDA and SCL)

100 ns

Note: 1. Sampled only, n ot 100% tested.

T able 5. Input Parameters

(1)

(TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit

I

LI

Input Leakage Current 0V ≤ VIN ≤ V

CC

±2 µA

I

LO

Output Leakage Current

0V ≤ V

OUT

≤ VCC

SDA in Hi-Z

±2 µA

I

CC

Supply Current (ST24 series)

V

CC

= 5V, fC = 100kHz

(Rise/Fall time < 10ns)

2mA

Supply Current (ST25 series) V

CC

= 2.5V, fC = 100kHz 1 mA

I

CC1

Supply Current (Standby)
(ST24 series)

V

IN

= VSS or VCC,

V

CC

= 5V

100 µA

V

IN

= VSS or VCC,

V

CC

= 5V, fC = 100kHz

300 µA

I

CC2

Supply Current (Standby)
(ST25 series)

V

IN

= VSS or VCC,

V

CC

= 2.5V

5 µA

V

IN

= VSS or VCC,

V

CC

= 2.5V, fC = 100kHz

50 µA

I

CC3

Supply Current (Standby)
(ST24C02R)

V

IN

= VSS or VCC,

V

CC

= 3.6V

20 µA

V

IN

= VSS or VCC,

V

CC

= 3.6V, fC = 100kHz

60 µA

I

CC4

Supply Current (Standby)
(ST24C02R)

V

IN

= VSS or VCC,

V

CC

= 1.8V

10 µA

V

IN

= VSS or VCC,

V

CC

= 1.8V, fC = 100kHz

20 µA

V

IL

Input Low Voltage (SCL, SDA) –0.3 0.3 V

CC

V

V

IH

Input High Voltage (SCL, SDA) 0.7 V

CC

VCC + 1 V

V

IL

Input Low Voltage
(E0-E2, MODE,

WC)

–0.3 0.5 V

V

IH

Input High Voltage
(E0-E2, MODE,

WC)

V

CC

– 0.5 VCC + 1 V

V

OL

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
Output Low Voltage (ST25 series) I

OL

= 2.1mA, VCC = 2.5V 0.4 V

Output Low Voltage
(ST24C02R)

I

OL

= 1mA, VCC = 1.8V 0.3 V

T ab le 6. DC Characteristics
(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)

5/16

ST24/25C02, ST24C02R, ST24/25W02

Symbol Alt Parameter Min Max Unit

t

CH1CH2

t

R

Clock Rise Time 1 µs

t

CL1CL2

t

F

Clock Fall Time 300 ns

t

DH1DH2

t

R

Input Rise Time 1 µs

t

DL1DL1

t

F

Input Fall Time 300 ns

t

CHDX

(1)

t

SU:STA

Clock High to Input Transition 4.7 µs

t

CHCL

t

HIGH

Clock Pulse Width High 4 µs

t

DLCL

t

HD:STA

Input Low to Clock Low (START) 4 µs

t

CLDX

t

HD:DAT

Clock Low to Input Transition 0 µs

t

CLCH

t

LOW

Clock Pulse Width Low 4.7 µs

t

DXCX

t

SU:DAT

Input Transition to Clock Transition 250 ns

t

CHDH

t

SU:STO

Clock High to Input High (STOP) 4.7 µs

t

DHDL

t

BUF

Input High to Input Low (Bus Free) 4.7 µs

t

CLQV

(2)

t

AA

Clock Low to Next Data Out Valid 0.3 3.5 µs

t

CLQX

t

DH

Data Out Hold Time 300 ns

f

C

f

SCL

Clock Frequency 100 kHz

t

W

(3)

t

WR

Write Time 10 ms

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted ST ART and/or STOP
conditions.

3. In the Multibyte Write m ode only , if accessed bytes are on two consecutiv e 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.

T ab le 7. AC Characteristics

(T

A

= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)

The 4 most significant bits of the devic e select code
are the device type identifier , corres ponding to the
I

2

C bus definition. For these memories the 4 bits
are fixed as 1010b. T he following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
2K memories can be connected on the same bus
giving a memory capacity total of 16K bits. After a
ST AR T condition a ny memory on the bus will iden­tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.

The 8th bit sent is the read or write bit (R

W), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.

Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages 0.2V

CC

to 0.8V

CC

Input and Output Timing Ref. Voltages 0.3VCC to 0.7V

CC

AC MEASUREMENT CONDITIONS

AI00825

0.8V

CC

0.2V

CC

0.7V

CC

0.3V

CC

Figure 4. AC T estin g Inpu t Outp ut Waveforms

DEVICE OPERATION (cont’d)

6/16

ST24/25C02, ST24C02R, ST24/25W02

SCL

SDA IN

SCL

SDA OUT

SCL

SDA IN

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLCH

tDXCX

tCLDX

SDA

INPUT

SDA

CHANGE

tCHDH

tDHDL

STOP &

BUS FREE

DATA VALID

tCLQV tCLQX

DATA OUTPUT

tDHDL

tCHDH

STOP

CONDITION

tCHDX

START

CONDITION

WRITE CYCLE

tW

AI00795

Figure 5. AC Waveforms

7/16

ST24/25C02, ST24C02R, ST24/25W02

SCL

SDA

SCL

SDA

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

1 23 789

MSB

ACK

START

CONDITION

SCL

1 23 789

MSB ACK

STOP

CONDITION

Figure 6. I2C Bus Protocol

Write Operations

The Multibyte Write mode (only available on the
ST24/25C02 and ST24C02R versions ) is select e d
when the MODE pin is at V

IH

and the Page Write

mode when MODE pin is at V

IL

. The MODE pin may

be driven dynamically with CMOS input levels.
Following a START condition the master sends a

device select code with the R

W bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides ac­cess to 256 bytes of the memory. After receipt of
the byte address the device again responds with
an acknowledge.

For the ST24/25W02 versions , any write command
with

WC = 1 will not modify the memory content.

Byte Write. In the Byte Write mode the master
sends one data byte, w hich is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operatin g
mode, as this pin has to be co nnected to either V

IH

or VIL, to minimize the stand-by current.

8/16

ST24/25C02, ST24C02R, ST24/25W02

Multibyte W rite. For the Multiby te Write mode, t he

MODE pin must be at V

IH

. The Multibyte Write
mode can be started from any address in the
memory . The mast er sends from one up to 4 bytes
of data, which are each acknowledged by the mem­ory. The transfer is terminated by the master gen­erating a ST OP co ndition. The durat ion of the write
cycle i s t

W

= 10ms maximum except when bytes
are accessed on 2 rows (that is have different
values for the 6 most significant address bits A7­A2), the programming time is then doubled to a
maximum of 20ms. Wr iting more than 4 bytes in th e
Multibyte W rite mode m ay modify data byt es in a n
adjacent row (one row is 8 bytes long). However,
the Multibyte Write can properly write up to 8
consecutive bytes only if the first address of these
8 bytes is the first address of the row , the 7 following
bytes being written in the 7 following bytes of this
same row.

Page Write. For the Page Wr ite mode, the MODE
pin must be at V

IL

. The Page Write mode allows up
to 8 bytes to be written in a single write cycle,
provided that they are all locat ed in the s ame ’r ow’
in the memory: that is the 5 most significant mem­ory address bits (A7-A3) are the s ame. The master
sends from one up to 8 bytes of data, which are
each acknowledged by the memory. After each
byte is transfered, the internal byte address count er
(3 least significant bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid ad­dress counter ’roll-over’ which could result in data
being overwritten. Note that, for any write mode,
the generation by the master of the STOP c ondition
starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.

WRITE Cycle

in Progress

AI01099B

Next

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

NO

YESNO

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction
with RW = 0 already
decoded by ST24xxx

Figure 7. Write Cycle Polling u sing A CK

9/16

ST24/25C02, ST24C02R, ST24/25W02

Minimizing System Delays by Polling On ACK.

During the internal write cycle, the memory discon­nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t

W

) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re­duced by an ACK polling sequence issued by the
master. The sequence is as follows:

– Initial condition: a Write is in progress (see Fig-

ure 7).

– Step 1: the master issues a START condition

followed by a device select byte (1st byte of
the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem­ory is ready to receive the second part of the
next instruction (the firs t byte of this instruc­tion was already sent during Step 1).

Read Operations

Read operations are independent of the state of the
MODE pin. On delivery, the memory content is set
at all "1’s" (or FFh).

Current Address Read. The memory has an inter­nal byte address counter . Each time a byte is read,
this counter is incremented. For the Current Ad­dress Read mode, following a START condition,
the master sends a memory address with the R

W
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter . This counter is then incremented.
The master does NOT acknowledge the byte out­put, but terminates the transfer with a STOP con­dition.

Random Address Read. A dummy write is per­formed to load the address into the address
counter, see Figure 10. This is f ollowed by another
START condition from the master and the byte
address is repeated with the R

W bit set to ’1’. The
memory acknowledges this and outputs the byte
addressed. The mas ter have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condit ion.

STOP

START

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

MULTIBYTE
AND
PAGE WRITE

DEV SEL BYTE ADDR

DATA IN 1 DATA IN 2

AI00793

STOP

DATA IN N

ACK ACK ACK

R/W

ACK ACK ACK

R/W

ACK ACK

Figure 8. Write Mod es Sequen ce (ST24/25C02 an d ST24C02R)

10/16

ST24/25C02, ST24C02R, ST24/25W02

STOP

START

BYTE WRITE DEV SEL BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1

WC

DATA IN 2

AI01101B

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK ACK

R/W

ACK ACK ACK

R/W

ACK ACK

Figure 9. Write Modes Seq uence w ith W rite Co n tro l = 1 (ST24/25W02)

Sequential Read. This mode can be initiated with

either a Current Address Read or a Random Ad­dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se­quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out­put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-

ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.

Acknowledge in Read Mode. In all read modes
the ST24/25x02 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x02 terminate t he
data transfer and switches to a standby state.

11/16

ST24/25C02, ST24C02R, ST24/25W02

START

DEV SEL * BYTE ADDR

START

DEV SEL DATA OUT 1

AI00794C

DATA OUT N

STOP

START

CURRENT
ADDRESS
READ

DEV SEL DATA OUT

RANDOM
ADDRESS
READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL
CURRENT
READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR

SEQUENTIAL
RANDOM
READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

Figure 10. Read Modes Sequ en ce

Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

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ST24/25C02, ST24C02R, ST24/25W02

ORDERI NG INFO RM ATION SCH EM E

Notes: 3 * Temperature range on special request only.

5 * Temperature range for ST24C02R only.

Parts are shipped with the memory content set at all "1’s" (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory

Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office

nearest to you.

Operating Voltage

ST24C02 3V to 5.5V
ST24W02 3V to 5.5V
ST25C02 2.5V to 5.5V
ST25W02 2.5V to 5.5V
ST24C02R 1.8V to 5.5V

Range

Standard
Hardware Write Control
Standard
Hardware Write Control
Standard

Package

B PSDIP8

0.25mm Frame

M SO8 150mil Width

Temperature Range

1 0 to 70 °C

5 * –20 to 85 °C

6 –40 to 85 °C

3 * –40 to 125 °C

Option

TR Tape & Reel

Packing

Example: ST24C02 M 1 TR

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ST24/25C02, ST24C02R, ST24/25W02

PSDIP-a

A2

A1AL

e1

D

E1 E

N

1

C

eA
eB

B1

B

Symb

mm inches

Typ Min Max Typ Min Max

A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.150

N8 8

PSDIP8

Drawing is not to scale

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

14/16

ST24/25C02, ST24C02R, ST24/25W02

SO-a

E

N

CP

B

e

A

D

C

LA1 α

1

H

h x 45˚

Symb

mm inches

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α 0° 8° 0° 8°
N8 8

CP 0.10 0.004

SO8

Drawing is not to scale

SO8 - 8 lead Plastic Small Outline, 150 mils body width

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ST24/25C02, ST24C02R, ST24/25W02

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificat ions mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.

© 1997 SGS-THOMSON Microelectronics - All Rights Reserved

Purchase of I

2

C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips

I

2

C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to

the I

2

C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

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ST24/25C02, ST24C02R, ST24/25W02