Datasheet SST38VF6401, SST38VF6402, SST38VF6403, SST38VF6404 Datasheet

A

64 Mbit (x16) Advanced Multi-Purpose Flash Plus

Microchip Technology Company

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

The SST38VF6401/6402/6403/6404 are 4M x16 CMOS Advanced Multi-Purpose
Flash Plus (Advanced MPF+) devices manufactured with SST proprietary, high­performance CMOS Super- Flash technology. The split-gate cell design and thick­oxide tunneling injector attain better reliability and manufacturability compared
with alternate approaches. The SST38VF6401/6402/6403/6404 write (Program or
Erase) with a 2.7-3.6V power supply. This device conforms to JEDEC standard
pin assignments for x16 memories.

Features

• Organized as 4M x16

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles minimum
– Greater than 100 years Data Retention3

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 4 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)

• 128-bit Unique ID

• Security-ID Feature

– 256 Word, user One-Time-Programmable

• Protection and Security Features

– Hardware Boot Block Protection/WP# Input Pin, Uni-

form (32 KWord) and Non-Uniform (8 KWord) options
available

– User-controlled individual block (32 KWord) protection,

using software only methods

– Password protection

Data Sheet

• Fast Erase Times:

– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)

• Erase-Suspend/-Resume Capabilities

• Fast Word and Write-Buffer Programming Times:

– Word-Program Time: 7 µs (typical)
– Write Buffer Programming Time: 1.75 µs / Word (typical)

- 16-Word Write Buffer

• Automatic Write Timing

– Internal VPPGeneration

• End-of-Write Detection

– Toggle Bits
– Data# Polling
– RY/BY# Output

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• CFI Compliant

• Hardware Reset Pin (RST#)

• Fast Read and Page Read Access Times:

– 90 ns Read access time
– 25 ns Page Read access times

- 4-Word Page Read buffer

• Packages Available

– 48-lead TSOP
– 48-ball TFBGA

• All devices are RoHS compliant

• Latched Address and Data

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64 Mbit (x16) Advanced Multi-Purpose Flash Plus

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SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Product Description

The SST38VF6401, SST38VF6402, SST38VF6403, and SST38VF6404 devices are 4M x16 CMOS
Advanced Multi-Purpose Flash Plus (Advanced MPF+) manufactured with SST proprietary, high-per­formance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with alternate approaches. The SST38VF6401/
6402/6403/6404 write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to
JEDEC standard pin assignments for x16 memories.

Featuring high performance Word-Program, the SST38VF6401/6402/6403/6404 provide a typical Word­Program time of 7 µsec. For faster word-programming performance, the Write-Buffer Programming
feature, has a typical word-program time of 1.75 µsec. These devices use Toggle Bit or Data# Polling
to indicate Program operation completion. In addition to single-word Read, Advanced MPF+ devices
provide a Page-Read feature that enables a faster word read time of 25 ns, for words on the same
page.

To protect against inadvertent write, the SST38VF6401/6402/6403/6404 have on-chip hardware and
Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of appli­cations, these devices are available with 100,000 cycles minimum endurance. Data retention is rated
at greater than 100 years.

Data Sheet

The SST38VF6401/6402/6403/6404 are suited for applications that require the convenient and econom­ical updating of program, configuration, or data memory. For all system applications, Advanced MPF+
significantly improve performance and reliability, while lowering power consumption. These devices
inherently use less energy during Erase and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, current, and time of application. For any given
voltage range, the SuperFlash technology uses less current to program and has a shorter erase time;
therefore, the total energy consumed during any Erase or Program operation is less than alternative
flash technologies.

These devices also improve flexibility while lowering the cost for program, data, and configuration stor­age applications. The SuperFlash technology provides fixed Erase and Program times, independent of
the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware
does not have to be modified or de-rated as is necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated Erase/Program cycles.

The SST38VF6401/6402/6403/6404 also offer flexible data protection features. Applications that
require memory protection from program and erase operations can use the Boot Block, Individual
Block Protection, and Advanced Protection features. For applications that require a permanent solu­tion, the Irreversible Block Locking feature provides permanent protection for memory blocks.

To meet high-density, surface mount requirements, the SST38VF6401/6402/6403/6404 devices are
offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 2 and 3 for pin assignments and
Table 1 for pin descriptions.

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SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Functional Block Diagram

Memory Address

RESET#

CE#

OE#
WE#
WP#

Address Buffer Latches

Control Logic

X-Decoder

RY/BY#

Data Sheet

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

DQ

-DQ

15

0

1309 B1.1

Figure 1: Functional Block Diagram

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Pin Assignments

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

A15
A14
A13
A12
A11
A10

A19
A20

WE#

RST#

A21

WP#

RY/BY#

A18
A17

1
2
3
4
5

A9

A8

A7

A6

A5

A4

A3

A2

A1

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Standard Pinout

Top View

Die Up

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1309 48-tsop P1.0

A16
NC
V

SS

DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

DD

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V

SS

CE#
A0

Figure 2: Pin Assignments for 48-lead TSOP

TOP VIEW (balls facing down)

6

5

4

3

2

1

A13

A9

WE#

RY/BY#

A7

A3

A12

A8

RST#

WP#

A17

A4

A14

A10

A21

A18

A6

A2

ABCDEFGH

Figure 3: Pin assignments for 48-ball TFBGA

A15

A11

A19

A20

A5

A1

A16

DQ7

DQ5

DQ2

DQ0

A0

NC

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

V

DD

DQ11

DQ9

OE#

V

SS

DQ6

DQ4

DQ3

DQ1

V

SS

1309 48-tfbga P1.0

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Table 1: Pin Description

Symbol Pin Name Functions

A

DQ

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when

RY/BY# Ready/Busy To indicate when the device is actively programming or erasing.

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

V

V

NC No Connection Unconnected pins.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

1

-A0Address Inputs To provide memory addresses.

MS

-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

15

DD

SS

1. AMS= Most significant address

Power Supply To provide power supply voltage: 2.7-3.6V

Ground

AMS=A21for SST38VF6401/6402/6403/6404

During Sector-Erase A
During Block-Erase A

MS-A15

address lines will select the sector.

MS-A12

address lines will select the block.

Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

grounded.

T1.0 25015

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Memory Maps

Table 2: SST38VF6401and SST38VF6402 Memory Maps

SST38VF6401

Block

B0
B1 S8-S15 0000001XXX YES YES NO
B2 S16-S23 0000010XXX YES YES NO
B3 S24-S31 0000011XXX YES YES NO
B4 S32-S39 0000100XXX YES YES NO
B5 S40-S47 0000101XXX YES YES NO
B6 S48-S55 0000110XXX YES YES NO
B7 S56-S63 0000111XXX YES YES NO
B8 - B119 follow the same pattern
B120 S960-S967 1111000XXX YES YES NO
B121 S968-S975 1111001XXX YES YES NO
B122 S976-S983 1111010XXX YES YES NO
B123 S984-S991 1111011XXX YES YES NO
B124 S992-S999 1111100XXX YES YES NO
B125 S1000-S1007 1111101XXX YES YES NO
B126 S1008-S1015 1111110XXX YES YES NO
B127 S1016-S1023 1111111XXX YES YES NO

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

1,2

6

Sectors

S0-S7 0000000XXX YES YES YES

3

Address A21-A

4

12

VPB

5

NVPB

5

WP#

6

SST38VF6402

1,2

Block

Sectors

B0 S0-S7 0000000XXX YES YES NO
B1 S8-S15 0000001XXX YES YES NO
B2 S16-S23 0000010XXX YES YES NO
B3 S24-S31 0000011XXX YES YES NO
B4 S32-S39 0000100XXX YES YES NO
B5 S40-S47 0000101XXX YES YES NO
B6 S48-S55 0000110XXX YES YES NO
B7 S56-S63 0000111XXX YES YES NO
B8 - B119 follow the same pattern
B120 S960-S967 1111000XXX YES YES NO
B121 S968-S975 1111001XXX YES YES NO
B122 S976-S983 1111010XXX YES YES NO
B123 S984-S991 1111011XXX YES YES NO
B124 S992-S999 1111100XXX YES YES NO
B125 S1000-S1007 1111101XXX YES YES NO
B126 S1008-S1015 1111110XXX YES YES NO

7

B127

1. Each block, B0-B127 is 32KWord.

2. Each block consists of eight sectors.

3. Each sector, S0-S1023 is 4KWord.

4. X=0or1.Block Address (BA) = A21-A15; Sector Address (SA) = A21-A

5. Each block has an associated VPB and NVPB.

6. Block B0 is the boot block.

7. Block B127 is the boot block.

S1016-S1023 1111111XXX YES YES YES

3

Address A21-A

4

12

VPB

5

12

NVPB

5

WP#

7

T2.0 25015

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Table 3: SST38VF6403and SST38VF6404 Memory Maps (1 of 2)

SST38VF6403

Block

B0

B1 S8-S15 0000001XXX YES YES NO

B2 S16-S23 0000010XXX YES YES NO

B3 S24-S31 0000011XXX YES YES NO

B4 S32-S39 0000100XXX YES YES NO

B5 S40-S47 0000101XXX YES YES NO

B6 S48-S55 0000110XXX YES YES NO

B7 S56-S63 0000111XXX YES YES NO

B8 - B119 follow the same pattern

B120 S960-S967 1111000XXX YES YES NO

B121 S968-S975 1111001XXX YES YES NO

B122 S976-S983 1111010XXX YES YES NO

B123 S984-S991 1111011XXX YES YES NO

B124 S992-S999 1111100XXX YES YES NO

B125 S1000-S1007 1111101XXX YES YES NO

B126 S1008-S1015 1111110XXX YES YES NO

B127 S1016-S1023 1111111XXX YES YES NO

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

5,6

1,2

Sectors

S0 0000000000 YES YES YES

S1 0000000001 YES YES YES

S2 0000000010 YES YES NO

S3 0000000011 YES YES NO

S4 0000000100 YES YES NO

S5 0000000101 YES YES NO

S6 0000000110 YES YES NO

S7 0000000111 YES YES NO

3

Address A21-A

4

12

VPB

5

NVPB

5

WP#

6

SST38VF6404

1,2

Block

Sectors

B0 S0-S7 0000000XXX YES YES NO

B1 S8-S15 0000001XXX YES YES NO

B2 S16-S23 0000010XXX YES YES NO

B3 S24-S31 0000011XXX YES YES NO

B4 S32-S39 0000100XXX YES YES NO

B5 S40-S47 0000101XXX YES YES NO

B6 S48-S55 0000110XXX YES YES NO

B7 S56-S63 0000111XXX YES YES NO

B8 - B119 follow the same pattern

B120 S960-S967 1111000XXX YES YES NO

B121 S968-S975 1111001XXX YES YES NO

B122 S976-S983 1111010XXX YES YES NO

B123 S984-S991 1111011XXX YES YES NO

B124 S992-S999 1111100XXX YES YES NO

©2011 Silicon Storage Technology, Inc. DS-25015A 04/11

3

Address A21-A

4

12

VPB

5

NVPB

5

WP#

7

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Table 3: SST38VF6403and SST38VF6404 Memory Maps (Continued) (2 of 2)

B125 S1000-S1007 1111101XXX YES YES NO

B126 S1008-S1015 1111110XXX YES YES NO

Block

B127

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

1,2

5, 7

Sectors

S1016 1111111000 YES YES NO

S1017 1111111001 YES YES NO

S1018 1111111010 YES YES NO

S1019 1111111011 YES YES NO

S1020 1111111100 YES YES NO

S1021 1111111101 YES YES NO

S1022 1111111110 YES YES YES

S1023 1111111111 YES YES YES

1. Each block, B0-B127 is 32KWord.

2. Each block consists of eight sectors.

3. Each sector, S0-S1023 is 4KWord.

4. X=0or1.Block Address (BA) = A21-A15; Sector Address (SA) = A21-A

5. Each block has an associated VPB and NVPB, except for some blocks in SST39VF6403 and SST39VF6404.
In SST39VF6403, Block B0 does not have a single VPB or NVPB for all 32 KWords. Instead, each sector (4 KWord) in
Block B0 has its own VPB and NVPB.
In SST39VF6404, Block B127 does not have a single VPB or NVPB for all 32 KWords. Instead, each sector (4 KWord)
in Block B127 has its own VPB and NVPB.

6. The 8KWord boot block consists of S0 and S1 in Block B0.

7. The 8KWord boot block consists of S1022 and S1023 in Block B127.

3

Address A21-A

4

12

VPB

5

12

NVPB

5

WP#

7

T3.0 25015

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Device Operation

The memory operations functions of these devices are initiated using commands written to the device
using standard microprocessor Write sequences. A command is written by asserting WE# low while
keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs
last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST38VF6401/6402/6403/6404 also have the Auto Low Power mode which puts the device in a
near-standby mode after data has been accessed with a valid Read operation. This reduces the I
active read current from typically 4 mA to typically 3 µA. The Auto Low Power mode reduces the typical
IDDactive read current to the range of 2 mA/MHz of Read cycle time. The device requires no access
time to exit the Auto Low Power mode after any address transition or control signal transition used to
initiate another Read cycle. The device does not enter Auto-Low Power mode after power-up with CE#
held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST38VF6401/6402/6403/6404 is controlled by CE# and OE#, both of which
have to be low for the system to obtain data from the outputs. CE# is used for device selection. When
CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in high impedance state when either CE# or
OE# is high. Refer to Figure 5, the Read cycle timing diagram, for further details.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

DD

Page Read

The Page Read operation utilizes an asynchronous method that enables the system to read data from
the SST38VF6401/6402/6403/6404 at a faster rate. This operation allows users to read a four-word
page of data at an average speed of 41.25 ns per word.

In Page Read, the initial word read from the page requires T
words in the page require only T
which are used to select the page. Address bits A1and A0are toggled, in any order, to read the words
within the page.

The Page Read operation of the SST38VF6401/6402/6403/6404 is controlled by CE# and OE#. Both
CE# and OE# must be low for the system to obtain data from the output pins. CE# controls device
selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the
output control and is used to gate data from the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to Figure 6, the Page Read cycle timing diagram, for further
details.

Word-Program Operation

The SST38VF6401/6402/6403/6404 can be programmed on a word-by-word basis. Before program­ming, the sector where the word exists must be fully erased. The Program operation is accomplished
in three steps. The first step is the three-byte load sequence for Software Data Protection. The second
step is to load word address and word data. During the Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the ris­ing edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation
which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for WE# and CE# con­trolled Program operation timing diagrams and Figure 24 for flowcharts.

to be valid, while the remaining three

ACC

. All four words in the page have the same address bits, A21-A2,

PACC

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During the Program operation, the only valid reads are Data# Polling, Toggle Bits, and RY/BY#. During
the internal Program operation, the host is free to perform additional tasks. Any commands issued dur­ing the internal Program operation are ignored. During the command sequence, WP# should be stati­cally held high or low.

When programming more than a few words, SST recommends Write-Buffer Programming.

Write-Buffer Programming

The SST38VF6401/6402/6403/6404 offer Write-Buffer Programming, a feature that enables faster
effective word programming. To use this feature, write up to 16 words with the Write-to-Buffer com­mand, then use the Program Buffer-to-Flash command to program the Write-Buffer to memory.

The Write-to-Buffer command consists of between 5 and 20 write cycles. The total number of write
cycles in the Write-to-Buffer command sequence is equal to the number of words to be written to the
buffer plus four.

The first three cycles in the command sequence tell the device that a Write-to-Buffer operation will
begin.

The fourth cycle tells the device the number of words to be written into the buffer and the block address
of these words. Specifically, the write cycle consists of a block address and a data value called the
Word Count (WC), which is the number of words to be written to the buffer minus one. If the WC is
greater than 15, the maximum buffer size minus 1, then the operation aborts.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

For the fifth cycle, and all subsequent cycles of the Write-to-Buffer command, the command sequence
consists of the addresses and data of the words to be written into the buffer. All of these cycles must
have the same A21-A4address, otherwise the operation aborts. The number of Write cycles required
is equal to the number of words to be written into the Write-Buffer, which is equal to WC plus one. The
correct number of Write cycles must be issued or the operation will abort. Each Write cycle decre­ments the Write-Buffer counter, even if two or more of the Write cycles have identical address values.
Only the final data loaded for each buffer location is held in the Write-Buffer.

Once the Write-to-Buffer command sequence is completed, the Program Buffer-to-Flash command
should be issued to program the Write-Buffer contents to the specified block in memory. The block
address (i.e. A21-A15) in this command must match the block address in the 4th write cycle of the
Write-to-Buffer command or the operation aborts. See Table 11 for details on Write-to-Buffer and Pro­gram-Buffer-to-Flash commands.

While issuing these command sequences, the Write-Buffer Programming Abort detection bit (DQ1)
indicates if the operation has aborted. There are several cases in which the device can abort:

• In the fourth write cycle of the Write-to-Buffer command, if the WC is greater than 15, the opera­tion aborts.

• In the fifth and all subsequent cycles of the Write-to-Buffer command, if the address values, A21-
A4, are not identical, the operation aborts.

• If the number of write cycles between the fifth to the last cycle of the Write-to-Buffer command is
greater than WC +1, the operation aborts.

• After completing the Write-to-Buffer command sequence, issuing any command other than the
Program Buffer-to-Flash command, aborts the operation.

• Loading a block address, i.e. A21-A
match the block address used in the Write-to-Buffer command aborts the operation.

in the Program Buffer-to-Flash command that does not

15,

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If the Write-to-Buffer or Program Buffer-to-Flash operation aborts, then DQ1= 1 and the device enters
Write-Buffer-Abort mode. To execute another operation, a Write-to-Buffer Abort-Reset command must
be issued to clear DQ1and return the device to standard read mode.

After the Write-to-Buffer and Program Buffer-to-Flash commands are successfully issued, the pro­gramming operation can be monitored using Data# Polling, Toggle Bits, and RY/BY#.

Sector/Block-Erase Operations

The Sector-Erase and Block-Erase operations allow the system to erase the device on a sector-by­sector, or block-by-block, basis. The SST38VF6401/6402/6403/6404 offer both Sector-Erase and Block­Erase modes.

The Sector-Erase architecture is based on a sector size of 4 KWords. The Sector-Erase command can
erase any 4 KWord sector (S0 - S1023).

The Block-Erase architecture is based on block size of 32 KWords. In SST38VF6401 and
SST38VF6402 devices, the Block-Erase command can erase any 32KWord Block (B0-B127). For the
non-uniform boot block devices, SST38VF6403 and SST38VF6404, the Block-Erase command can
erase any 32 KWord block except the block that contains the boot area. In the boot area, Block-Erase
behaves like Sector-Erase, and only erases a 4KWord sector. For the SST38VF6403 device, a Block­Erase executed on the Boot Block (B0), will result in the device erasing a 4KWord sector in B0 located
at A21-A12. For the SST38VF6404 device, a Block-Erase executed on the Boot Block (B127), will result
in the device erasing a 4KWord sector in B127 located at A21-A12.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase
command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated
by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA)
in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse,
while the command (50H or 30H) is latched on the rising edge of the sixth WE# pulse. The internal
Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined
using either Data# Polling or Toggle Bit methods. The RY/BY# pin can also be used to monitor the
erase operation. For more information, see Figures 14 and 15 for timing waveforms and Figure 29 for
the flowchart.

Any commands, other than Erase-Suspend, issued during the Sector- or Block-Erase operation are
ignored. Any attempt to Sector- or Block-Erase memory inside a block protected by Volatile Block Pro­tection, Non-Volatile Block Protection, or WP# (low) will be ignored. During the command sequence,
WP# should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read or programmed into any sector or block that is not engaged in an Erase operation. The
operation is executed with a one-byte command sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs (max) after the Erase-Suspend command had
been issued. Valid data can be read, using a Read or Page Read operation, from any sector or block
that is not being erased. Reading at an address location within Erase-Suspended sectors or blocks will
output DQ2toggling and DQ6at ‘1’. While in Erase-Suspend, a Word-Program or Write-Buffer Pro­gramming operation is allowed anywhere except the sector or block selected for Erase-Suspend.

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To resume a suspended Sector-Erase or Block-Erase operation, the system must issue the Erase­Resume command. The operation is executed by issuing one byte command sequence with Erase­Resume command (30H) at any address in the last Byte sequence.

When an erase operation is suspended, or re-suspended, after resume the cumulative time needed for
the erase operation to complete is greater than the erase time of a non-suspended erase operation. If
the hold time from Erase-Resume to the next Erase- Suspend operation is less than 200µs, the accu­mulative erase time can become very long Therefore, after issuing an Erase-Resume command, the
system must wait at least 200µs before issuing another Erase-Suspend command. The Erase-Resume
command will be ignored until any program operations initiated during Erase-Suspend are complete.

Bypass mode can be entered while in Erase-Suspend, but only Bypass Word-Program is available for
those sectors or blocks that are not suspended. Bypass Sector-Erase, Bypass Block-Erase, and
Bypass Chip-Erase, Erase-Suspend, and Erase-Resume are not available. In order to resume an
Erase operation, the Bypass mode must be exited before issuing Erase-Resume. For more information
about Bypass mode, see “Bypass Mode” on page 17.

Chip-Erase Operation

The SST38VF6401/6402/6403/6404 devices provide a Chip-Erase operation, which erases the entire
memory array to the ‘1’ state. This operation is useful when the entire device must be quickly erased.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads
are Toggle Bit, Data# Polling, or RY/BY#. See Table 11 for the command sequence, Figure 13 for tim­ing diagram, and Figure 29 for the flowchart. Any commands issued during the Chip-Erase operation
are ignored. If WP# is low, or any VPBs or NVPBs are in the protect state, any attempt to execute a
Chip-Erase operation is ignored. During the command sequence, WP# should be statically held high
or low.

Write Operation Status Detection

To optimize the system Write cycle time, the SST38VF6401/6402/6403/6404 provide two software
means to detect the completion of a Write (Program or Erase) cycle The software detection includes
two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system. Therefore, Data# Poll­ing or Toggle Bit maybe be read concurrent with the completion of the write cycle. If this occurs, the
system may possibly get an incorrect result from the status detection process. For example, valid data
may appear to conflict with either DQ7or DQ6. To prevent false results, upon detection of failures, the
software routine should loop to read the accessed location an additional two times. If both reads are
valid, then the device has completed the Write cycle, otherwise the failure is valid.

For the Write-Buffer Programming feature, DQ1informs the user if either the Write-to-Buffer or Pro­gram Buffer-to-Flash operation aborts. If either operation aborts, then DQ1=1.DQ1must be cleared to
'0' by issuing the Write-to-Buffer Abort Reset command.

The SST38VF6401/6402/6403/6404 also provide a RY/BY# signal. This signal indicates the status of a
Program or Erase operation.

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If a Program or Erase operation is attempted on a protected sector or block, the operation will abort.
After the device initiates an abort, the corresponding Write Operation Status Detection Bits will stay
active for approximately 200ns (program or erase) before the device returns to read mode.

For the status of these bits during a Write operation, see Table 4.

Data# Polling (DQ7)

When the SST38VF6401/6402/6403/6404 are in an internal Program operation, any attempt to read
DQ7will produce the complement of true data. For a Program Buffer-to-Flash operation, DQ7 is the
complement of the last word loaded in the Write-Buffer using the Write-to-Buffer command. Once the
Program operation is completed, DQ7will produce valid data. Note that even though DQ7may have valid
data immediately following the completion of an internal Write operation, the remaining data outputs may still be
invalid. Valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1
µs.

During an internal Erase operation, any attempt to read DQ7will produce a ‘0’. Once the internal Erase
operation is completed, DQ7will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is
valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 11 for Data# Polling timing diagram
and Figure 26 for a flowchart.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

Toggle Bits (DQ6and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce
alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal Program or Erase opera­tion is completed, the DQ6bit will stop toggling, and the device is then ready for the next operation. For
Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#)
pulse. DQ6will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector or Block.
If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6will toggle.

An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6to check
whether a particular sector or block is being actively erased or erase-suspended. Table 4 shows
detailed bit status information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or
CE#) pulse of Write operation. See Figure 12 for Toggle Bit timing diagram and Figure 26 for a flow­chart.

DQ

1

If an operation aborts during a Write-to-Buffer or Program Buffer-to-Flash operation, DQ1is set to ‘1’.
To reset DQ1to ‘0’, issue the Write-to-Buffer Abort Reset command to exit the abort state. A power-off/
power-on cycle or a Hardware Reset (RST# = 0) will also clear DQ1.

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RY/BY#

The RY/BY# pin can be used to determine the status of a Program or Erase operation. The RY/BY# pin
is valid after the rising edge of the final WE# pulse in the command sequence. If RY/BY# = 0, then the
device is actively programming or erasing. If RY/BY# = 1, the device is in Read mode. The RY/BY# pin
is an open drain output pin. This means several RY/BY# can be tied together with a pull-up resistor to
V

DD..

Table 4: Write Operation Status

Status DQ

Normal
Operation

Erase-Suspend Mode Read from Erase-Suspended

Program Buffer-to-Flash Busy DQ

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

1

DQ

7

Standard Program DQ7# Toggle No Toggle 0 0

Standard Erase 0 Toggle Toggle N/A 0

1 No toggle Toggle N/A 1

Sector/Block

Read from Non- Erase­Suspended Sector/Block

Program DQ

Abort DQ

1. DQ7and DQ2require a valid address when reading status information.

2. RY/BY# is an open drain pin. RY/BY# is high in Read mode, and Read in Erase-Suspend mode.

3. During a Program Buffer-to-Flash operation, the datum on the DQ7pin is the complement of DQ7of the last word
loaded in the Write-Buffer using the Write-to-Buffer command.

Data Data Data Data 1

# Toggle N/A N/A 0

7

3

#

7

#3Toggle N/A 1 0

7

6

Toggle N/A 0 0

DQ

1

2

DQ1RY/BY#

2

T4.0 25015

Data Protection

The SST38VF6401/6402/6403/6404 provide both hardware and software features to protect nonvolatile
data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.

VDDPower Up/Down Detection: The Write operation is inhibited when VDDis less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre­vents inadvertent writes during power-up or power-down.

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Hardware Block Protection

The SST38VF6402 and SST39VF6404 devices support top hardware block protection, which protects
the top boot block of the device. For SST38VF6402, the boot block consists of the top 32 KWord block,
and for SST39VF6404 the boot block consists of the top two 4 KWord sectors (8 KWord total).

The SST38VF6401 and SST38VF6403 devices support bottom hardware block protection, which pro­tects the bottom boot block of the device. For SST38VF6401, the boot block consists of the bottom 32
KWord block, and for SST39VF6403 the Boot Block consists of the bottom two 4 KWord sectors (8
KWord total). The boot block addresses are described in Table 5.

Table 5: Boot Block Address Ranges

Product Size Address Range

Bottom Boot Uniform

Top Boot Uniform

Bottom Boot Non-Uniform

Top Boot Non-Uniform

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

SST38VF6401 32 KW 000000H-007FFFH

SST38VF6402 32 KW 3F8000H-3FFFFFH

SST38VF6403 8 KW 000000H-001FFFH

SST38VF6404 8 KW 3FE000H-3FFFFFH

T5.0 25015

Program and Erase operations are prevented on the Boot Block when WP# is low. If WP# is left float­ing, it is internally held high via a pull-up resistor. When WP# is high, the Boot Block is unprotected,
which allows Program and Erase operations on that area.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least T
no internal Program/Erase operation is in progress, a minimum period of T

any in-progress operation will terminate and return to Read mode. When

RP,

is required after RST#

RHR

is driven high before a valid Read can take place. See Figure 20 for more information.

The interrupted Erase or Program operation must be re-initiated after the device resumes normal oper­ation mode to ensure data integrity.

Software Data Protection (SDP)

The SST38VF6401/6402/6403/6404 devices implement the JEDEC approved Software Data Protection
(SDP) scheme for all data alteration operations, such as Program and Erase. These devices are
shipped with the Software Data Protection permanently enabled. See Table 11 for the specific software
command codes.

All Program operations require the inclusion of the three-byte sequence. The three-byte load sequence
is used to initiate the Program operation, providing optimal protection from inadvertent Write opera­tions. SDP for Erase operations is similar to Program, but a six-byte load sequence is required for
Erase operations.

During SDP command sequence, invalid commands will abort the device to read mode within T
contents of DQ15-DQ8can be VILor VIH, but no other value, during any SDP command sequence.

RC.

The

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The SST38VF6401/6402/6403/6404 devices provide Bypass Mode, which allows for reduced Program
and Erase command sequence lengths. In this mode, the SDP portion of Program and Erase com­mand sequences are omitted. See “Bypass Mode” on page 17. for further details.

Common Flash Memory Interface (CFI)

The SST38VF6401/6402/6403/6404 contain Common Flash Memory Interface (CFI) information that
describes the characteristics of the device. In order to enter the CFI Query mode, the system can
either write a one-byte sequence using a standard CFI Query Entry command, or a three-bye
sequence using the SST CFI Query Entry command. A comparison of these two commands is shown
in Table 11. Once the device enters the CFI Query mode, the system can read CFI data at the
addresses given in Tables 13 through 16.

The system must write the CFI Exit command to return to Read mode. Note that the CFI Exit com­mand is ignored during an internal Program or Erase operation. See Table 11 for software command
codes, Figures 17 and 18 for timing waveform, and Figures 27 and 28 for flowcharts.

Product Identification

The Product Identification mode identifies the devices as the SST38VF6401, SST38VF6402,
SST38VF6403, or SST38VF6404, and the manufacturer as SST. See Table 6 for specific address and
data information. Product Identification mode is accessed through software operations. The software
Product Identification operations identify the part, and can be useful when using multiple manufactur­ers in the same socket. For details, see Table 11 for software operation, Figure 16 for the software ID
Entry and Read timing diagram, and Figure 27 for the software ID Entry command sequence flowchart.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

Table 6: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST38VF6401 0001H 536B

SST38VF6402 0001H 536A

SST38VF6403 0001H 536D

SST38VF6404 0001H 536C

T6.0 25015

While in Product Identification mode, the Read Block Protection Status command determines if a block
is protected. The status returned indicates if the block has been protected, but does not differentiate
between Volatile Block Protection and Non-Volatile Block Protection. See Table 11 for further details.

The Read-Irreversible Block-Lock Status command indicates if the Irreversible Block Command has
been issued. If DQ0= 0, then the Irreversible Lock command has been previously issued.

In order to return to the standard Read mode, the software Product Identification mode must be exited.
The exit is accomplished by issuing the software ID Exit command sequence, which returns the device
to the Read mode. See Table 11 for software command codes, Figure 18 for timing waveform, and Fig­ures 27 and 28 for flowcharts.

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Security ID

The SST38VF6401/6402/6403/6404 devices offer a Security ID feature. The Secure ID space is divided
into two segments — one factory programmed 128 bit segment and one user programmable 256 word
segment. See Table 7 for address information. The first segment is programmed and locked at SST
and contains a 128 bit Unique ID which uniquely identifies the device. The user segment is left un-pro­grammed for the customer to program as desired.

Table 7: Address Range for Sec ID

SST Unique ID 128 bits 000H – 007H

User 256 W 100H – 1FFH

The user segment of the Security ID can be programmed in several ways. For smaller datasets, use
the Security ID Word-Program command for word-programming. To program larger sets of data more
quickly, use the SEC ID Entry command to enter the Secure ID space. Once in the Secure ID space,
use the Write-Buffer Programming or Bypass Mode feature. Note that the Word-Programming com­mand can also be used while in this mode.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

Size Address

T7.1 25015

To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling to detect end of
Write. Once the programming is complete, lock the Sec ID by issuing the User Sec ID Program Lock­Out command or by programming bit ‘0’ in the PSR with the PSR Program command. Locking the Sec
ID disables any corruption of this space. Note that regardless of whether or not the Sec ID is locked,
the Sec ID segments can not be erased.

The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID
command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID com­mand should be executed. Refer to Table 11 for software commands and Figures 27 and 28 for flow
charts.

Bypass Mode

Bypass mode shortens the time needed to issue program and erase commands by reducing these
commands to two write cycles each. After using the Bypass Entry command to enter the Bypass
mode, only the Bypass Word-Program, Bypass Sector Erase, Bypass Block Erase, Bypass Chip
Erase, Erase-Suspend, and Erase-Resume commands are available. The Bypass Exit command exits
Bypass mode. See Table 11 for further details.

Entering Bypass Mode while already in Erase-Suspend limits the available commands. See “Erase­Suspend/Erase-Resume Commands” on page 11. for more information.

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Protection Settings Register (PSR)

The Protection Settings Register (PSR) is a user-programmable register that allows for further custom­ization of the SST38VF6401/6402/6403/6404 protection features. The 16-bit PSR provides four One
Time Programmable (OTP) bits for users, each of which can be programmed individually. However,
once an OTP bit is programmed to ‘0’, the value cannot be changed back to a ‘1’. The other 12 bits of
the PSR are reserved. See Table 8 for the definition of all 16-bits of the PSR.

Table 8: PSR Bit Definitions

Bit Default from Factory Definition

DQ

DQ

DQ

DQ

DQ

DQ

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

15

4

3

2

1

0

-DQ

5

FFFh Reserved

1 VPB power-up / hardware reset state

0 = all protected
1 = all unprotected

1 Reserved

1 Password mode

0 = Password only mode
1 = Pass-Through mode

1 Pass-Through mode

0 = Pass-Through only mode
1 = Pass-Through mode

1 SEC ID Lock Out Bit

0 = locked
1 = unlocked

T8.0 25015

Note that DQ4,DQ2,DQ1,DQ0do not have to be programmed at the same time. In addition, DQ2 and
DQ1 cannot both be programmed to ‘0’. The valid combinations of states of DQ2and DQ1are shown in
Table 9.

Table 9: Valid DQ2and DQ1Combinations

Combination Definition

,DQ1= 11 Pass-Through mode (factory default)

DQ

2

DQ

DQ

DQ

The PSR can be accessed by issuing the PSR Entry command. Users can then use the PSR Program
and PSR Read commands. The PSR Exit command must be issued to leave this mode. See Table 11
for further details.

= 10 Pass-Through only mode

2,DQ1

,DQ1= 01 Password only mode

2

,DQ1= 00 Not Allowed

2

T9.0 25015

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Individual Block Protection

The SST38VF6401/6402/6403/6404 provide two methods for Individual Block protection: Volatile Block
Protection and Non-Volatile Block Protection. Data in protected blocks cannot be altered.

Volatile Block Protection

The Volatile Block Protection feature provides a faster method than Non-Volatile Protection to protect
and unprotect 32 KWord blocks. Each block has it’s own Volatile Protection Bit (VPB). In the
SST38VF6401/2, the 32 KWord boot block also has a VPB. In the SST38VF6403/4 devices, each of
the two 4 KWord sectors in the 8 KWord boot area has it's own VPB.

After using the Volatile Block Protection Mode Entry command to enter the Volatile Block Protection
mode, individual VPBs can be set or reset with VPB Set/Clear, or be read with VPB Status Read. If the
VPB is ‘0’, then the block is protected from Program and Erase. If the VPB is ‘1’, then the block is
unprotected. The Volatile Block Protection Exit command must be issued to exit Volatile Block Protec­tion mode. See Table 11 for further details on the commands and Figure 31 for a flow chart.

If the device experiences a hardware reset or a power cycle, all the VPBs return to their default state
as determined by user-programmable bit DQ4in the PSR. If DQ4is ‘0’, then all VPBs default to ‘0’ (pro­tected). If DQ4is ‘1’, then all VPBs default to ‘1’ (unprotected).

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

Non-Volatile Block Protection

The Non-Volatile Block Protection feature provides protection to individual blocks using Non-Volatile
Protection Bits (NVPBs). Each block has it’s own Non-Volatile Protection Bit. In the SST38VF6401/2,
the 32 KWord boot block also has a it's own NVPB. In the SST38VF6403/4, each 4 KWord sector in
the 8KWord boot area has it's own NVPB. All NVPBs come from the factory set to ‘1’, the unprotected
state.

Use the Non-Volatile Block Protection Mode Entry command to enter the Non-Volatile Block Protection
mode. Once in this mode, the NVPB Program command can be used to protect individual blocks by
setting individual NVPBs to ‘0’. The time needed to program an NVPB is two times T
imum of 20µs. The NVPB Status Read command can be used to check the protection state of an indi­vidual NVPB.

To change an NVPB to ‘1’, the unprotected state, the NVPB must be erased using NVPBs Erase com­mand. This command erases all NVPBs to ‘1’. NVPB Program should be used to set the NVPBs of any
blocks that are to be protected before exiting the Non-Volatile Block Protection mode. See Table 11
and Figure 32 for further details.

Upon a power cycle or hardware reset, the NVPBs retain their states. Memory areas that are protected
using Non-Volatile Block Protection remain protected. The NVPB Program and NVPBs Erase com­mands are permanently disabled once the Irreversible Block Lock command is issued. See “Irrevers­ible Block Locking” on page 22 for further information.

which is a max-

BP,

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Advanced Protection

The SST38VF6401/6402/6403/6404 provide Advanced Protection features that allow users to imple­ment conditional access to the NVPBs. Specifically, Advanced Protection uses the Global Lock Bit to
protect the NVPBs. If the Global Lock bit is ‘0’ then all the NVPBs states are frozen and cannot be
modified in any mode. If the Global Lock bit is ‘1’, then all the NVPBs can be modified in Non-Volatile
Block Protection mode. After using the Global Lock of NVPBs Entry command to enter the Global Lock
of NVPBs mode, the Global Lock Bit can be activated by issuing a Set Global Lock Bit command,
which sets the Global Lock Bit to ‘0’. The Global Lock bit cannot be set to ‘1’ with this command. The
status of the bit can be read with the Global Lock Bit Status command. Use the Global Lock of NVPBs
Exit command to exit Global Lock of NVPBs mode. See Table 11 and Figure 33 for further details.

The steps used to change the Global Lock Bit from '0' to'1,' to allow access to the NVPBs, depend on
whether the device has been set to use Pass-Through or Password mode. When using Advanced Pro­tection, select either Pass-Through only mode or Password only mode by programming the DQ2and
DQ1bits in the PSR. Although the factory default is Pass-Through mode (DQ2=1,DQ1= 1), the user
should explicitly chose either Pass-Through only mode (DQ2=1,DQ1= 0), or Password only mode
(DQ2=0,DQ1= 1). Keeping the SST38VF6401/6402/6403/6404 in the factory default Pass-Through
mode leaves the device open to unauthorized changes of DQ2and DQ1in the PSR. See “Protection
Settings Register (PSR)” on page 18. for more information about the PSR.

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Data Sheet

Pass-Through Mode (DQ2,DQ1= 1,0)

The Pass-Through Mode allows the Global Lock Bit state to be cleared to ‘1’ by a power-down power­up sequence or a hardware reset (RST# pin = 0). No password is required in Pass-Through mode.

To set the Global Lock Bit to ‘0’, use the Set Global Lock Bit command while in the Global Lock of
NVPBs mode. Select the Pass-Through only mode by programming PSR bit DQ2= 1 and DQ1=0.

Password Mode (DQ2,DQ1= 0,1)

In the Password Mode, the Global Lock Bit is set to ‘0’ by the Set Global Lock Bit command, a power­down power-up sequence, or a hardware reset (RST# pin = 0). Select the Password only mode by pro­gramming PSR bit DQ2= 0 and DQ1= 1. Note that when the PSR Program command is issued in
Password mode, the Global Lock bit is automatically set to ‘0’.

In contrast to the Pass-Through Mode, in the Password mode, the only way to clear the Global Lock Bit
to ‘1’ is to submit the correct 64-bit password using the Submit Password command in Password Com­mands Mode. The words of the password can be submitted in any order as long as each 16 bit section
of the password is matched with its correct address. After the entire 64 bit password is submitted, the
device takes approximately 2 µs to verify the password. A subsequent Submit Password command
cannot be issued until this verification time has elapsed.

The 64-bit password must be chosen by the user before programming the DQ2and DQ1OTP bits of
the PSR to choose Password Mode. The default 64 bit password on the device from the factory is
FFFFFFFFFFFFFFFFh.

Enter the Password Commands mode by issuing the Password Commands Entry command. Then,
use the Password Program command to program the desired password. Use caution when program­ming the password because there is no method to reset the password to FFFFFFFFFFFFFFFFh.
Once a password bit has been set to ‘0’, it cannot be changed back to ‘1’. See Table 11 for further
details about Password-related commands.

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