Datasheet SST37VF512-90-3C-WH, SST37VF010-70-3C-PH, SST37VF010-70-3C-NH, SST37VF512-90-3C-PH, SST37VF512-90-3C-NH Datasheet (Silicon Storage Technology)

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories

FEATURES:

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8)

Many-Time Programmable Flash

Data Sheet

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• 2.7-3.6V Read Operation

• Superior Reliability

– Endurance: At least 1000 Cycles – Greater than 100 years Data Retention

• Low Power Consumption:

– Ac ti ve Current: 10 mA (typical) – Standby Current: 2 µA (typical)

• Fast Read Access Time:

– 70 ns – 90 ns

• Latched Address and Data

PRODUCT DESCRIPTION

The SST37VF512/010/020/040 devices are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable (MTP), low cost flash, manufactured with SST’s proprietary , high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST37VF512/010/020/040 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. The SST37VF512/010/020/040 have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide flash memories.

• Fast Byte-Program Operation:

– Byte-Program Time: 10 µs (typical) – Chip Program Time:

0.6 seconds (typical) for SST37VF512

1.2 seconds (typical) for SST37VF010

2.4 seconds (typical) for SST37VF020

4.8 seconds (typical) for SST37VF040

• Electrical Erase Using Programmer

– Does not require UV source – Chip-Erase Time: 100 ms (typical)

• CMOS I/O Compatibility

• JEDEC Standard Byte-wide Flash

EEPROM Pinouts

• Packages Available

– 32-pin PLCC – 32-pin TSOP (8mm x 14mm) – 32-pin PDIP

To meet surface mount and conventional through hole requirements, the SST37VF512/010/020/040 are offered in 32-pin PLCC, TSOP, and P DIP pa ckages. See F igures 1, 2, and 3 for pinouts.

Device Operation

The SST37VF512/010/020/040 devices are nonvolatile memory solutions that can be used instead of standard flash devices if in-system programmability is not required. It is functionally (Read) and pin compatible with industry standard flash products.The device supports electrical Erase operation via an external programmer.

Featuring high performance Byte-Program, the SST37VF512/010/020/040 provide a typical Byte-Program time of 10 µs. Designed, manufactur ed, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention i s rat ed at g reat er than 100 y ears .

The SST37VF512 /010/020/ 040 are sui ted for applica tions that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs.

1

Read

The Read operation of the SST37VF512/010/020/040 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the output s. Once the address is s table, the addres s access time is equal t o the delay from CE# to output (T output after a delay of TOE from the falling edge of OE#, assuming the CE# pin has been low and the addresses have been stable for at least T is high, the chip is deselected and a standby current of only 10 µA (typical) is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is V Refer to Fig ure 4 f or the ti ming di agr am.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MTP is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

). Data is available at the

CE

- TOE. When the CE# pin

CE

IH

.

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

Byte-Program Operation

The SST37VF512/ 010/0 20/040 are programmed by usin g an external programmer. The programming m ode is activated by asserting 12V (±5%) on OE# pin and V

on CE#

IL

pin. The device is program me d u sing a single puls e ( W E # pin low) of 10 µs per byte. Using the MTP programming algorithm, the Byte-Program process continues byte-bybyte until the entire chip ha s been programmed. Refer to Figure 10 for the flowchart and Figur e 6 for the timi ng di agram.

Chip-Erase Operation

The only way to change a data from a “0” to “1” is by electri- cal erase that changes every bit in the device to “1”. The SST37VF512/010/020/040 use an electrical Chip-Erase operation. The entire chip can be erased in 100 ms (WE# pin low). In order to activate erase mode, the 12V (±5%) is applied to OE# and A address and data pins are “don’t care”. The falling edge of WE# will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. R efer to Figure 9 for the f lowchart and Figure 5 for the timing diagr am.

pins while CE# is low. All other

9

Product Identification Mode

The Product Id entification mode ide ntifies the devices as SST37VF512, SST37VF010, SST37VF020, and SST37VF040 and manufacturer a s SST. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force V (12V±5%) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address

. For details, see T able 3 for hardware operation.

line A

0

TABLE 1: P

Manufacturer’s ID 0000H BFH Device ID SST37VF512 0001H C4H SST37VF010 0001H C5H SST37VF020 0001H C6H SST37VF040 0001H C2H

RODUCT IDENTIFICATION

Address Data

T1.2 397

Design Considerations

The SST37VF512/010/020/040 should have a 0.1µF ceramic high frequency, low inductance capacitor connected between V placed as close to the package terminals as possible.

and GND. This capacitor shou ld be

DD

H

FUNCTIONAL BLOCK DIAGRAM

Memory Address

CE# OE#

A

9

WE#

Address Buffer

Control Logic

X-Decoder

OE# and A

must remain stable at VH for the entire dura-

9

tion of an Erase operati on. OE# mus t remain stable at V for the entire duration of the Program operation.

SuperFlash

Memory

Y-Decoder

I/O Buffers

DQ7 - DQ

0

397 ILL B1.1

H

2

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

A12

A15

A16

A18

VDDWE#

A17

A12

A15

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A16NCVDDWE#

A12

A15

A16NCVDDWE#

A12

A15NCNC

SST37VF512 SST37VF010 SST37VF020 SST37VF040SST37VF040 SST37VF020 SST37VF010 SST37VF512

4 3 2 1 32 31 30

5 6 7 8

32-pin PLCC

9 10

T op Vie w

11 12 13

14 15 16 17 18 19 20

VDDWE#

A17

NC

29 28 27 26 25 24 23 22 21

SST37VF512 SST37VF010 SST37VF020 SST37VF040SST37VF040 SST37VF020 SST37VF010 SST37VF512

A14 A13 A8 A9 A11 OE# A10 CE# DQ7

DQ1

DQ2

V

SS

DQ3

DQ4

DQ5

DQ6

397 ILL F02a.2

SS

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

SST37VF040 SST37VF020 SST37VF010 SST37VF512 SST37VF512 SST37VF010 SST37VF020 SST37VF040

A11

A13 A14

A17 WE# V

DD

A18

A16

A15

A12

SS

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

A11 A9 A8

A7 A6 A5 A4

A13

A14

A17

WE# V

DD

NC A16 A15 A12

A9 A8

A7 A6 A5 A4

A11

A13 A14

NC WE# V

DD

NC

A16 A15 A12

A9 A8

A7 A6 A5 A4

A11

A13 A14

NC WE# V

DD

NC

A15 A12

A9 A8

A7 A6 A5 A4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Standard Pinout

T op Vie w

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V DQ2 DQ1 DQ0 A0 A1 A2 A3

SS

OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V

SS

DQ2 DQ1 DQ0 A0 A1 A2 A3

397 ILL F01.0

FIGURE 2: P

IN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

3

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

SST37VF040 SST37VF020 SST37VF010 SST37VF512

A18 A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

NC A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

NC A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

NC

NC A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2 V

SS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32-pin

PDIP

T op Vie w

SST37VF512 SST37VF010 SST37VF020 SST37VF040

32

V

31

WE#

30

NC

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE#

23

A10

22

CE#

21

DQ7

20

DQ6

19

DQ5

18

DQ4

17

DQ3

DD

V WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

DD

V

DD

WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

397 ILL F02b.1

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

1

A

-A

MS

-DQ

DQ

7

CE# Chip Enable To activate the device when CE# is low. WE# Write Enable To program or erase (WE# = V OE# Output Enable To gate the data output buffers during Read operation when low V

DD

V

SS

NC No Connection Unconnected pins.

1. AMS = Most significant address A

MS

Address Inputs To provide memory addresses.

0

Data Input/output To output data during Read cycles and receive input data during Program cycles.

0

The outputs are in tri-state when OE# or CE# is high.

pulse during Program or Erase)

IL

Power Supply To provide 3.0V supply (2.7-3.6V) Ground

= A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040

V

DD

WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

T2.1 397

4

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

TABLE 3: OPERATION MODES SELECTION

Mode CE# WE# A

V

Read V Output Disable V Standby V Chip-Erase V Byte-Program V

IL IL IH IL IL

Program/Erase Inhibit X V

A

IH

IN

XX VIHHigh Z A

XX X High Z X V V

V

IL IL IH

H

A

IN

XXHigh Z X

XXXV

Product Identification V

1. Device ID = C4H for SST37VF512, C5H for SST37VF020, C6H for SST37VF020, and C2H for SST37VF040

2. A

= Most significant address

MS

= A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040

A

MS

Note: X = VIL or VIH (or VH in case of OE# and A9)

= 12V±5%

V

H

V

IL

V

IH

H

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

OE# DQ Address

9

IL

V

IL

V

H

V

H

or V

V

IL

D

OUT

High Z X D

IN

High Z/ D

IH

OUT

Manufacturer’s ID (BFH) Device ID

1

A

IN IN

A

IN

X

2

A

- A1 = VIL, A0 = V

MS

2

A

- A1 = VIL, A0 = V

MS

IL IH

T3.1 397

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

+ 0.5V

DD

+ 1.0V

DD

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

1

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

AC CONDITIONS OF TEST

DD

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF

See Figures 7 and 8

5

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

TABLE 4: READ MODE DC OPERATING CHARACTERISTICS VDD=2.7-3.6V (Ta = 0°C to +70°C (Commercial))

Limits

Symbol Parameter

I

DD

VDD Read Current Address input=VIL/VIH, at f=1/TRC Min

12 mA CE#=OE#=V

I

SB

I

LI

I

LO

V

IL

V

IH

V

IHC

V

OL

V

OH

I

H

Standby VDD Current 15 µA CE#=V Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Output Leakage Current 10 µA V Input Low Voltage 0.8 V VDD=VDD Min Input High Voltage 0.7 V

DD

Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min Output High Voltage VDD-0.3 V IOH=-100 µA, VDD=VDD Min Supervoltage Current for A9 for Read-ID 200 µA CE#=OE#=VIL, A9=VH Max

TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS VDD=2.7-3.6V (Ta = 25°C±5°C)

Limits

Symbol Parameter

I

DD

I

LI

I

LO

V

H

I

H

VDD Erase or Program Current 20 mA CE#=V Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Output Leakage Current 10 µA V Supervol tage for A9 and OE# 11.4 12.6 V Supervol tage Curre nt for A9 and OE# 200 µA OE#=VH Max, A9=VH Max, VDD=VDD Max, CE# = V

Test ConditionsMin Max Units

=GND to VDD, VDD=VDD Max

OUT

Test ConditionsMin Max Units

V

DD=VDD

OUT

Max

, all I/Os open

IL

, VDD=VDD Max

IHC

=GND to VDD, VDD=VDD Max

VVDD=VDD Max

OE#=VH, VDD=VDD Max, WE#=V

IL,

Data Sheet

T4.3 397

IL

T5.1 397

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T

PU-READ

T

PU-WRITE

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs Power-up to Write Operation 100 µs

T6.1 397

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 12 pF

I/O

Input Capacitance VIN = 0V 6 pF

T7.0 397

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LTH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117 Data Retention 100 Years JEDEC Standard A103 Latch Up 100 + I

DD

mA JEDEC Standard 78

6

T8.3 397

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V (Ta = 0°C to +70°C (Commercial))

SST37VF512-70 SST37VF010-70 SST37VF020-70 SST37VF040-70

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

1

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Read Cycle Time 70 90 ns Chip Enable Access Time 70 90 ns Address Acce ss Time 70 90 ns Output Enable Access Time 35 45 ns CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns CE# High to High-Z Output 30 30 ns OE# High to High-Z Output 30 30 ns Output Hold from Address Change 0 0 ns

SST37VF512-90 SST37VF010-90 SST37VF020-90 SST37VF040-90

UnitsMinMaxMinMax

T9.2 397

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD = 2.7-3.6V (Ta = 25°C±5°C)

Symbol Parameter Min Max Units

T T T T T T T T T T T T T T T T

BP CES

CEH AS AH

DS

DH

PRT

VPS

VPH

PW

EW

VR ART A9S A9H

Byte-Program Time 12 20 µs CE# Setup Time 1 ns CE# Hold Time 1 ns Address Setup Time 1 ns Address Hold Time 1 ns Data Setup Time 1 ns Data Hold Time 1 ns OE# Rise Time for Program and Erase 1 ns OE# Setup Time for Program and Erase 1 ns OE# Hold Time for Program and Erase 1 ns WE# Program Pulse Width 10 15 ns WE# Erase Pulse Width 100 500 ns OE#/A9 Recovery Time for Erase 1 ns A9 Rise Time to 12V during Erase 1 ns A9 Setup Time during Erase 1 ms A9 Hold Time during Erase 1 ms

T10.0 397

7

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

ADDRESS

CE#

OE#

IH

WE#

DQ

7-0

HIGH-Z

T

FIGURE 4: READ CYCLE TIMING DIAGRAM

T

OLZV

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

OH

CHZ

HIGH-Z

DAT A V ALIDDAT A V ALID

397 ILL F03.0

ADDRESS

(EXCEPT A9)

CE#

DQ

7-0

V

OE#

A

WE#

H

V

DD

V

SS

V

9

V

T

H

IH IL

T

PRT

ART

T

VPS

A9S

CES

FIGURE 5: CHIP-ERASE TIMING DIAGRAM

T

CEH

T

VPH

T

VR

T

A9H

T

EW

397 ILL F04.0

8

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

T

PC

ADDRESS

ADDRESS VALID

CE#

DQ

7-0

HIGH-Z

V

OE#

H

V

DD

V

SS

T

VPS

PRT

WE#

T

CES

FIGURE 6: BYTE-PROGRAM TIMING DIAGRAM

DAT A V ALID

T

AS

T

DS

AH

T

CEH

T

DH

T

PW

T

VPH

397 ILL F05.0

9

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

V

IHT

V

ILT

AC test inputs are driven at V for inputs and outputs are V

V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 V) and VOT (0.5 VDD). Input rise and f a ll ti mes (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

FIGURE 7: AC I NPUT/OUTPUT REFERENCE WAVEFORMS

TO DUT

397 ILL F07.1

V

OT

397 ILL F06.1

(0.1 VDD) for a logic “0”. Measurement reference points

IL T

Note: V

- V

INPUT

OUTPUT

INPUT

Test

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

C

L

FIGURE 8: A TEST LOAD EXAMPLE

10

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

Start

A9 = VH, OE# = V

CE# = V

Erase 100ms pulse

(WE# = VIL)

WE# = V

OE#/A9 = VIL or V

Wait TVR Recovery Time

Read Device

Compare all

bytes to FF

H

IL

IH

No

FIGURE 9: CHIP-ERASE ALGORITHM

Yes

Device Passed

Device Failed

397 ILL F08.0

11

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

Start

Erase*

Increment Address

OE# = V

Address = First Location;

Load Data

CE# = V

Program 10µs pulse

(WE# = VIL)

Last Address?

No

H

IL

Yes

OE# = V

Read Device

Compare all bytes

to original data

Wait T

IL

VR

No

Yes

Device Passed

*See Figure 9

Device Failed

397 ILL F09.1

FIGURE 10: BYTE-PROGRAM ALGORITHM

12

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

Device Speed Suffix1 Suffix2

SST37VFxxx

-XXX -XX -XX

Package Modifi e r

H= 32 pins Numeric = Die modifier

Package Type

N = PLCC W = TSOP (die up) (8mm x 14mm) P = PDIP

Operating Temperature

C = Commercial = 0° to +70°C

Minimum Endurance

3= 1000 cycles

Read Access Speed

70 = 70 ns 90 = 90 ns

Device Density

512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit

SST37VF512 Valid combinations

SST37VF512-70-3C-NH S ST37VF512-70-3C-WH SST37VF512-90-3C-NH SST37VF512-90-3C-WH SST37VF512-90-3C-PH

SST37VF010 Valid combinations

SST37VF010-70-3C-NH SST37VF010-70-3C-WH SST37VF010-90-3C-NH SST37VF010-90-3C-WH SST37VF010-90-3C-PH

SST37VF020 Valid combinations

SST37VF020-70-3C-NH SST37VF020-70-3C-WH SST37VF020-90-3C-NH SST37VF020-90-3C-WH SST37VF020-90-3C-PH

SST37VF040 Valid combinations

SST37VF040-70-3C-NH SST37VF040-70-3C-WH SST37VF040-90-3C-NH SST37VF040-90-3C-WH SST37VF040-90-3C-PH

Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

13

PACKAGING DIAGRAMS

TOP VIEW SIDE VIEW BOTT OM VIEW

.485 .495

Optional

Pin #1 Identifier

.042 .048

.447 .453

1232

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

.106

.020 R. MAX.

.023 .029

x 30˚

.112

.030 .040

R.

.042 .048

.547

.585

.553

.595

.050 BSC.

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.026 .032

.050 BSC.

32-PIN PLASTIC LEAD CHIP CARRIER (PLCC)

ACKAGE CODE: NH

SST P

Pin # 1 Identifier

.125 .140

.075 .095

.013 .021

.400 BSC

.015 Min.

.490 .530

1.05

0.95

.50

BSC

.026 .032

32.PLCC.NH-ILL.2

12.50

12.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

32-

PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

14.20

13.80

8.10

7.90

32.TSOP-WH-ILL.4

0.15

0.05

.270 .170

SST PACKAGE CODE: WH

14

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

32

C

L

Pin #1 Identifier

.065 .075

1

1.645

1.655

7˚

4 PLCS.

.600 .625

.530 .550

Base Plane

Seating Plane

.015 .050

.070 .080

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.045 .065

.016 .022

32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)

ACKAGE CODE: PH

SST P

.100 BSC

.120 .150

.170 .200

.008 .012

.600 BSC

32.pdipPH-ILL.2

15˚

0˚

15

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408 -735 -9036

www.SuperFlash.com or www.ssti.com

16

Datasheet SST37VF512-90-3C-WH, SST37VF010-70-3C-PH, SST37VF010-70-3C-NH, SST37VF512-90-3C-PH, SST37VF512-90-3C-NH Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual