Datasheet SST36VF1601E, SST36VF1602E Datasheet (Silicon Storage Technology)

FEATURES:

16 Mbit (x8/x16) Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

SST36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlash

Data Sheet

• Organized as 1M x16 or 2M x8

• Dual Bank Architecture for Concurrent
Read/Write Operation

– 16 Mbit Bottom Sector Protection

- SST36VF1601E: 12 Mbit + 4 Mbit

– 16 Mbit Top Sector Protection

- SST36VF1602E: 4 Mbit + 12 Mbit

• Single 2.7-3.6V for Read and Write Operations

• Superior Reliability

– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical

• Hardware Sector Protection/WP# Input Pin

– Protects the 4 outermost sectors (8 KWord)

in the larger bank by driving WP# low and
unprotects by driving WP# high

• Hardware Reset Pin (RST#)

– Resets the internal state machine to reading

array data

• Byte# Pin

– Selects 8-bit or 16-bit mode

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Chip-Erase Capability

• Block-Erase Capability

– Uniform 32 KWord blocks

• Erase-Suspend / Erase-Resume Capabilities

• Security ID Feature

– SST: 128 bits
– User: 128 bits

• Fast Read Access Time

– 70 ns

• Latched Address and Data

• Fast Erase and Program (typical):

– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs

• Automatic Write Timing

– Internal V

Generation

PP

• End-of-Write Detection

– Toggle Bit
– Data# Polling
– Ready/Busy# pin

• CMOS I/O Compatibility

• Conforms to Common Flash Memory Interface (CFI)

• JEDEC Standards

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST36VF1601E and SST36VF1602E are 1M x16 or
2M x8 CMOS Concurrent Read/Write Flash Memory man­ufactured with SST’s proprietary, high performance CMOS
SuperFlash memory technology. The split-gate cell design
and thick oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The devices write (Program or Erase) with a 2.7-3.6V
power supply and conform to JEDEC standard pinouts for
x8/x16 memories.

Featuring high performance Program, these devices pro­vide a typical Program time of 7 µsec and use the Toggle
Bit, Data# Polling, or RY/BY# to detect the completion of
the Program or Erase operation. To protect against inad­vertent write, the devices have on-chip hardware and Soft­ware Data Protection schemes. Designed, manufactured,

©2005 Silicon Storage Technology, Inc.
S71274-03-000 11/05

1

and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.

These devices are suited for applications that require con­venient and economical updating of program, configura­tion, or data memory. For all system applications, the
devices significantly improve performance and reliability,
while lowering power consumption. Since for any given
voltage range, the SuperFlash technology uses less cur­rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. These devices
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

CSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.

To meet high-density, surface-mount requirements, these
devices are offered in 48-ball TFBGA and 48-lead TSOP
packages. See Figures 5 and 6 for pin assignments.

Device Operation

Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which­ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.

Auto Low Power Mode

These devices also have the Auto Lower Power mode
which puts them in a near standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the I

active Read current to 4 µA typically.

DD

While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.

Concurrent Read/Write Operation

The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank.

C

ONCURRENT READ/WRITE STATE

Bank 1 Bank 2

Read No Operation

Read Write

Write Read

Write No Operation

No Operation Read

No Operation Write

Note: For the purposes of this table, write means to perform Block-

or Sector-Erase or Program operations as applicable to the
appropriate bank.

Read Operation

The Read operation is controlled by CE# and OE#; both
have to be low for the system to obtain data from the out­puts. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is con­sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in a high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 7).

Program Operation

These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, one must ensure that the sector
which is being programmed is fully erased.

The Program operation is accomplished in three steps:

1. Software Data Protection is initiated using the
three-byte load sequence.

2. Address and data are loaded.

During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.

3. The internal Program operation is initiated after
the rising edge of the fourth WE# or CE#, which­ever occurs first. The Program operation, once ini­tiated, will be completed typically within 7 µs.

See Figures 8 and 9 for WE# and CE# controlled Program
operation timing diagrams and Figure 23 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during an internal Program operation
are ignored.

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

2

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

Sector-Erase/Block-Erase Operation

These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector­Erase command (30H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut­ing a six-byte command sequence with Block-Erase com­mand (50H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter­nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera­tion are ignored except Erase-Suspend and Erase­Resume. See Figures 13 and 14 for timing waveforms.

Chip-Erase Operation

The devices provide a Chip-Erase operation, which allows
the user to erase all sectors/blocks to the “1” state. This is
useful when a device must be quickly erased.

The Chip-Erase operation is initiated by executing a six­byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. Any com­mands issued during the Chip-Erase operation are
ignored. See Table 5 for the command sequence, Figure
12 for timing diagram, and Figure 27 for the flowchart.
When WP# is low, any attempt to Chip-Erase will be
ignored.

Erase-Suspend/Erase-Resume Operations

The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode no more than 10 µs
after the Erase-Suspend command had been issued. (T

ES

maximum latency equals 10 µs.) Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within erase­suspended sectors/blocks will output DQ
DQ

at “1”. While in Erase-Suspend mode, a Program

6

toggling and

2

operation is allowed except for the sector or block selected
for Erase-Suspend. To resume Sector-Erase or Block­Erase operation which has been suspended, the system
must issue an Erase-Resume command. The operation is
executed by issuing a one-byte command sequence with
Erase Resume command (30H) at any address in the one­byte sequence.

Write Operation Status Detection

These devices provide one hardware and two software
means to detect the completion of a Write (Program or
Erase) cycle in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta­tus bits: Data# Polling (DQ
End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.

The actual completion of the nonvolatile write is asynchro­nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ
be simultaneous with the completion of the Write cycle. If
this occurs, the system may get an erroneous result, i.e.,
valid data may appear to conflict with either DQ
order to prevent spurious rejection if an erroneous result
occurs, the software routine should include a loop to read
the accessed location an additional two (2) times. If both
Reads are valid, then the Write cycle has completed, other­wise the rejection is valid.

) and Toggle Bit (DQ6). The

7

), or Toggle Bit (DQ6) Read may

7

or DQ6. In

7

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

3

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output sig­nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to V

via an external pull-up

DD

resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.

Byte/Word (BYTE#)

The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (V
data I/0 pins DQ

) the device is in x16 data configuration: all

IH

-DQ15 are active and controlled by CE#

0

and OE#.

If the BYTE# pin is at logic “0”, the device is in x8 data con­figuration: only data I/O pins DQ

-DQ7 are active and con-

0

trolled by CE# and OE#. The remaining data pins DQ
DQ

are at Hi-Z, while pin DQ15 is used as the address

14

input A

for the Least Significant Bit of the address bus.

-1

Data# Polling (DQ7)

When the devices are in an internal Program operation, any
attempt to read DQ
true data. Once the Program operation is completed, DQ
will produce true data. During internal Erase operation, any
attempt to read DQ
Erase operation is completed, DQ
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 10 for Data# Poll­ing (DQ

) timing diagram and Figure 24 for a flowchart.

7

will produce the complement of the

7

will produce a ‘0’. Once the internal

7

will produce a ‘1’. The

7

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con­secutive attempts to read DQ
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The device is then ready for the next opera­tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ
rising edge of sixth WE# (or CE#) pulse. DQ
“1” if a Read operation is attempted on an Erase-sus­pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ
toggle.

An additional Toggle Bit is available on DQ
used in conjunction with DQ
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ
is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 11 for Toggle Bit timing
diagram and Figure 24 for a flowchart.

-

8

TABLE 1: WRITE OPERATION STATUS

Status DQ

7

Normal
Operation

Erase­Suspend
Mode

Note: DQ7, DQ

Standard
Program

Standard
Erase

Read From
Erase
Suspended
Sector/Block

Read From
Non-Erase
Suspended
Sector/Block

Program DQ7# Toggle N/A 0

and DQ2 require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta­tus. If the address is pointing to a different bank (not busy),
the device will output array data.

6,

will produce alternating “1”s

6

bit will

6

) is valid after the

6

will be set to

6

, which can be

2

to check whether a particular

6

DQ

7

DQ7# Toggle No Toggle 0

0 Toggle Toggle 0

1 1 Toggle 1

Data Data Data 1

DQ

6

RY/BY #

2

T1.1 1274

6

will

)

2

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

4

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

Data Protection

The devices provide both hardware and software features
to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.

V

Power Up/Down Detection: The Write operation is

DD

inhibited when V

Write Inhibit Mode:
high will inhibit the Write operation. This prevents inadvert­ent writes during power-up or power-down.

is less than 1.5V.

DD

Forcing OE# low, CE# high, or WE#

Hardware Block Protection

The devices provide hardware block protection which pro­tects the outermost 8 KWord in the larger bank. The block
is protected when WP# is held low. See Figures 1, 2, 3,
and 4 for Block-Protection location.

A user can disable block protection by driving WP# high.
This allows data to be erased or programmed into the pro­tected sectors. WP# must be held high prior to issuing the
Write command and remain stable until after the entire
Write operation has completed. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera­tions on that block.

Software Data Protection (SDP)

These devices provide the JEDEC standard Software Data
Protection scheme for all data alteration operations, i.e.,
Program and Erase. Any Program operation requires the
inclusion of the three-byte sequence. The three-byte load
sequence is used to initiate the Program operation, provid­ing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. Any
Erase operation requires the inclusion of the six-byte
sequence. The devices are shipped with the Software Data
Protection permanently enabled. See Table 5 for the spe­cific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within T
V

but no other value during any SDP command

IH,

sequence.

The contents of DQ15-DQ8 can be VIL or

RC.

Common Flash Memory Interface (CFI)

These devices also contain the CFI information to
describe the characteristics of the devices. In order to
enter the CFI Query mode, the system must write the
three-byte sequence, same as the Software ID Entry com­mand with 98H (CFI Query command) to address 555H in
the last byte sequence. See Figure 16 for CFI Entry and
Read timing diagram. Once the device enters the CFI
Query mode, the system can read CFI data at the
addresses given in Tables 6 through 8. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least T
return to Read mode (see Figure 20). When no internal
Program/Erase operation is in progress, a minimum period
of T

RHR

Read can take place (see Figure 19).

The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity.

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

any in-progress operation will terminate and

RP,

is required after RST# is driven high before a valid

Security ID

The SST36VF160xE devices offer a 256-bit Security ID
space. The Secure ID space is divided into two 128-bit seg­ments—one factory programmed segment and one user
programmed segment. The first segment is programmed
and locked at SST with a unique, 128-bit number. The user
segment is left un-programmed for the customer to pro­gram as desired. To program the user segment of the
Security ID, the user must use the Security ID Program
command. End-of-Write status is checked by reading the
toggle bits. Data# Polling is not used for Security ID End-of­Write detection. Once programming is complete, the Sec
ID should be locked using the User Sec ID Program Lock­Out. This disables any future corruption of this space. Note
that regardless of whether or not the Sec ID is locked, nei­ther Sec ID segment can be erased. The Secure ID space
can be queried by executing a three-byte command
sequence with Query Sec ID command (88H) at address
555H in the last byte sequence. See Figure 18 for timing
diagram. To exit this mode, the Exit Sec ID command
should be executed. Refer to Table 5 for more details.

5

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Product Identification

The Product Identification mode identifies the devices and
manufacturer. For details, see Table 2 for software opera­tion, Figure 15 for the Software ID Entry and Read timing
diagram and Figure 25 for the Software ID Entry command
sequence flowchart. The addresses A
bank address. When the addressed bank is switched to
Product Identification mode, it is possible to read another
address from the same bank without issuing a new Soft­ware ID Entry command.

TABLE 2: P

Manufacturer’s ID BK0000H 00BFH

Device ID

SST36VF1601E BK0001H 734BH

SST36VF1602E BK0001H 734AH

Note: BK = Bank Address (A19-A18)

RODUCT IDENTIFICATION

FUNCTIONAL BLOCK DIAGRAM

and A18 indicate a

19

Address Data

T2.0 1274

Product Identification Mode
Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom­plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode. This
command may also be used to reset the device to the Read
mode after any inadvertent transient condition that appar­ently causes the device to behave abnormally, e.g., not read
correctly. Please note that the Software ID Exit/CFI Exit
command is ignored during an internal Program or Erase
operation. See Table 5 for the software command code, Fig­ure 17 for timing waveform and Figure 26 for a flowchart.

Memory
Address

BYTE#

RST#

CE#

WP#

WE#

OE#

RY/BY#

Address

Buffers

Control

Logic

(8 KWord Sector Protection)

SuperFlash Memory

12 Mbit Bank

SuperFlash Memory

4 Mbit Bank

I/O Buffers

1274 B01.0

DQ15/A

-1

- DQ

0

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

6

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors

Data Sheet

8 KWord Sector Protection

(4-2 KWord Sectors)

FFFFFH

F8000H

F7FFFH

F0000H

EFFFFH

E8000H

E7FFFH

E0000H

DFFFFH

D8000H

D7FFFH

D0000H
CFFFFH
C8000H

C7FFFH

C0000H

BFFFFH

B8000H

B7FFFH

B0000H

AFFFFH

A8000H

A7FFFH

A0000H

9FFFFH

98000H
97FFFH
90000H

8FFFFH

88000H
87FFFH
80000H

7FFFFH

78000H
77FFFH
70000H

6FFFFH

68000H
67FFFH
60000H

5FFFFH

58000H
57FFFH
50000H

4FFFFH

48000H
47FFFH
40000H

3FFFFH

38000H
37FFFH
30000H

2FFFFH

28000H
27FFFH
20000H

1FFFFH

18000H
17FFFH
10000H
0FFFFH
08000H
07FFFH

02000H
01FFFH
00000H

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Bank 2

Bank 1

1274 F01.0

Note: The address input range in x16 mode (BYTE#=VIH) is A19-A

0

FIGURE 1: SST36VF1601E, 1M X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

7

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors

16 KByte Sector Protection

(4-4 KByte Sectors)

1FFFFFH

1F0000H

1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H

1BFFFFH

1B0000H

1AFFFFH

1A0000H
19FFFFH
190000H

18FFFFH

180000H
17FFFFH

170000H

16FFFFH

160000H

15FFFFH

150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH

004000H
003FFFH
000000H

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Bank 2

Bank 1

1274 F02.0

Note: The address input range in x8 mode (BYTE#=VIL) is A19-A

-1

FIGURE 2: SST36VF1601E, 2M X8 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

8

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Top Block Protection; 32 KWord Blocks; 2 KWord Sectors

8 KWord Block Protection

(4 - 2 KWord Sectors)

FFFFFH
FE000H

FDFFFH

F8000H

F7FFFH

F0000H

EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H

D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH

98000H

97FFFH

90000H

8FFFFH

88000H

87FFFH

80000H

7FFFFH

78000H

77FFFH

70000H

6FFFFH

68000H

67FFFH

60000H

5FFFFH

58000H

57FFFH

50000H

4FFFFH

48000H

47FFFH

40000H

3FFFFH

38000H

37FFFH

30000H

2FFFFH

28000H

27FFFH

20000H

1FFFFH

18000H

17FFFH

10000H

0FFFFH

08000H

07FFFH

00000H

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Data Sheet

Bank 2

Bank 1

1274 F03.0

Note: The address input range in x16 mode (BYTE#=VIH) is A19-A

0

FIGURE 3: SST36VF1602E, 1M X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

9

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Top Block Protection; 64 KByte Blocks; 4 KByte Sectors

16 KByte Block Protection

(4 - 4 KByte Sectors)

Note: The address input range in x8 mode (BYTE#=VIL) is A19-A

1FFFFFH

1FC000H

1FBFFFH

1F0000H

1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H

1BFFFFH

1B0000H

1AFFFFH

1A0000H
19FFFFH
190000H

18FFFFH
180000H
17FFFFH

170000H

16FFFFH

160000H

15FFFFH

150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H

00FFFFH
000000H

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

1274 F04.0

Bank 2

Bank 1

-1

FIGURE 4: SST36VF1602E, 2M X8 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

10

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

TOP VIEW (balls facing down)

6

A13

5

4

A9

WE#

A12

A8

RST#

A14

A10

NC

A15

A11

A19

A16

DQ7

DQ5

BYTE#

DQ14

DQ12

NOTE*

DQ13

V

DD

3

RY/BY#

WP#

DQ10

DQ11

DQ2

NC

A18

2

A7

A17

DQ8

DQ9

DQ0

A5

A6

1

A3

A4

CE#

OE#

A0

A1

A2

A B C D E F G H

Note* = DQ15/A

-1

FIGURE 5: PIN ASSIGNMENTS FOR 48-BALL TFBGA (6MM X 8MM)

A15
A14
A13
A12
A11
A10

A9
A8

A19

NC

WE#

RST#

NC

WP#

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Standard Pinout

Top View

Die Up

V

SS

DQ6

DQ4

DQ3

DQ1

V

SS

1274 48-tfbga P1.0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
V

SS

DQ15/A
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

DD

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V

SS

CE#
A0

-1

1274 48-tsop P02.0

FIGURE 6: P

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

IN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM)

11

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Data Sheet

TABLE 3: PIN DESCRIPTION

Symbol Name Functions

A

19-A0

DQ

14

DQ15/A-1Data Input/Output

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

RST# Hardware Reset To reset and return the device to Read mode

RY/BY# Ready/Busy# To output the status of a Program or Erase operation

WP# Write Protect To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or

BYTE# Word/Byte Configuration To select 8-bit or 16-bit mode.

V

DD

V

SS

NC No Connection Unconnected pins

Address Inputs To provide memory addresses. During Sector-Erase and Hardware Sector Protection,

A

address lines will select the sector. During Block-Erase A19-A15 address

19-A11

lines will select the block.

-DQ0Data Input/Output To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# or CE# is high.

DQ15 is used as data I/O pin when in x16 mode (BYTE# = “1”)

and LBS Address

A-1 is used as the LSB address pin when in x8 mode (BYTE# = “0”)

RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.

Program operation.

Power Supply To provide 2.7-3.6V power supply voltage

Ground

T3.0 1274

TABLE 4: OPERATION MODES SELECTION

1

Mode

Read V

Program V

Erase V

Standby V

Write Inhibit X V

Product
Identification

Software
Mode

1. RST# = VIH for all described operation modes

2. X can be VIL or VIH, but no other value.

3. Device ID = SST36VF1601E = 734BH,

CE# OE# WE# DQ7-DQ

V

IL

IL

IL

IHC

XXV

V

IL

V

IL

IH

V

V

V

IH

IL

V

IH

IL

X X High Z High Z High Z X

X High Z / D

IL

IH

V

V

IL

IH

D

High Z / D

Manufacturer’s ID

(BFH)

Device ID

SST36VF1602E = 734AH

OUT

D

X

DQ15-DQ

0

IN

2

IH

D

OUT

D

IN

X High Z Sector or Block

8

BYTE# = V

IL

AddressBYTE# = V

DQ14-DQ8 = High Z A

DQ15 = A

-1

IN

A

IN

address,

555H for Chip-Erase

OUT

OUT

High Z / D

High Z / D

OUT

OUT

Manufacturer’s ID

High Z X

High Z X

High Z See Table 5

(00H)

3

Device ID

3

High Z

T4.2 1274

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

12

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

TABLE 5: SOFTWARE COMMAND SEQUENCE

Command
Sequence

Program

Sector-Erase

Block-Erase

Chip-Erase

Erase-Suspend

Erase-Resume

Query Sec ID

5

User Security ID
Program

User Security ID
Program Lock-out

Software ID Entry

7

8

CFI Query Entry

Software ID Exit/
CFI Exit/
Sec ID Exit

10,11

Software ID Exit/
CFI Exit/
Sec ID Exit

1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode.

2. DQ

3. WA = Program word/byte address

4. SA

5. For SST36VF1601E,

6. SIWA = User Security ID Program word/byte address

7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=V

8. The device does not remain in Software Product Identification mode if powered down.

9. A

10. Both Software ID Exit operations are equivalent

11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the

10,11

When in x8 mode, Addresses A

-DQ8 can be VIL or VIH, but no other value, for the command sequence

15

for Sector-Erase; uses A19-A11 address lines

X

BA

for Block-Erase; uses A19-A15 address lines

X

SST ID is read with A
User ID is read with A
Lock Status is read with A
For SST36VF1602E,
SST ID is read with A
User ID is read with A
Lock Status is read with A

For SST36VF1601E, valid Word-Addresses for User Sec ID are from 00010H-00017H.
For SST36VF1602E, valid Word-Addresses for User Sec ID are from C0010H-C0017H.
All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.

and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode

19

With A

= 0;SST Manufacturer’s ID = 00BFH, is read with A0 = 0

17-A1

User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).
For SST36VF1601E, valid Word-Addresses for User Sec ID are from 00010H-00017H.
For SST36VF1602E, valid Word-Addresses for User Sec ID are from C0010H-C0017H.

1st Bus

Write Cycle

1

Addr

555H AAH 2AAH 55H 555H A0H WA

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BA

Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

3

Data

5th Bus

Write Cycle

6th Bus

Write Cycle

4

X

4

X

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

XXXXH B0H

XXXXH 30H

555H AAH 2AAH 55H 555H 88H

555H AAH 2AAH 55H 555H A5H SIWA6Data

555H AAH 2AAH 55H 555H 85H XXH 0000H

555H AAH 2AAH 55H BK

555H AAH 2AAH 55H BK

X

555H

X

555H

9

90H

9

98H

555H AAH 2AAH 55H 555H F0H

XXH F0H

Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.

19-A12,

= 0 (Address range = 00000H to 00007H),

3

= 1 (Address range = 00010H to 00017H).

3

= 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

7-A0

= 0 (Address range = C0000H to C0007H),

3

= 1 (Address range = C0010H to C0017H).

3

= C00FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

7-A0

).

IH

SST36VF1601E Device ID = 734BH, is read with A
SST36VF1602E Device ID = 734AH, is read with A

0

0

= 1
= 1

2

30H

50H

T5.1 1274

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

13

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Data Sheet

TABLE 6: CFI QUERY IDENTIFICATION STRING1

Address

x16 Mode

10H 20H 0051H Query Unique ASCII string “QRY”
11H 22H 0052H
12H 24H 0059H
13H 26H 0001H Primary OEM command set
14H 28H 0007H
15H 2AH 0000H Address for Primary Extended Table
16H 2CH 0000H
17H 2EH 0000H Alternate OEM command set (00H = none exists)
18H 30H 0000H
19H 32H 0000H Address for Alternate OEM extended Table (00H = none exits)
1AH 34H 0000H

1. Refer to CFI publication 100 for more details.

2. In x8 mode, only the lower byte of data is output.

TABLE 7: SYSTEM INTERFACE INFORMATION

Address

x16 Mode

1BH 36H 0027H V

1CH 38H 0036H V

1DH 3AH 0000H VPP min (00H = no VPP pin)

1EH 3CH 0000H V

1FH 3EH 0004H Typical time out for Program 2

20H 40H 0000H Typical time out for min size buffer program 2N µs (00H = not supported)

21H 42H 0004H Typical time out for individual Sector/Block-Erase 2

22H 44H 0006H Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H 46H 0001H Maximum time out for Program 2

24H 48H 0000H Maximum time out for buffer program 2

25H 4AH 0001H Maximum time out for individual Sector-/Block-Erase 2

26H 4CH 0001H Maximum time out for Chip-Erase 2

1. In x8 mode, only the lower byte of data is output.

Address
x8 Mode Data

Address
x8 Mode Data

2

Description

1

Description

Min (Program/Erase)

DD

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

Max (Program/Erase)

DD

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

max (00H = no VPP pin)

PP

N

µs (24 = 16 µs)

N

ms (24 = 16 ms)

N

times typical (21 x 24 = 32 µs)

N

times typical

N

times typical (21 x 26 = 128 ms)

N

times typical (21 x 24 = 32 ms)

T6.0 1274

T7.0 1274

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

14

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

TABLE 8: DEVICE GEOMETRY INFORMATION

Address

x16 Mode

27H 4EH 0015H Device size = 2
28H 50H 0002H Flash Device Interface description; 0002H = x8/x16 asynchronous interface
29H 52H 0000H
2AH 54H 0000H Maximum number of bytes in multi-byte write = 2
2BH 56H 0000H
2CH 58H 0002H Number of Erase Sector/Block sizes supported by device
2DH 5AH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 5CH 0001H y = 511 + 1 = 512 sectors (01FFH = 512)
2FH 5EH 0010H
30H 60H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H 62H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 64H 0000H y = 31 + 1 = 32 blocks (001FH = 31)
33H 66H 0000H
34H 68H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

1. In x8 mode, only the lower byte of data is output.

Address
x8 Mode Data

1

Description

N

Bytes (15H = 21; 221 = 2 MByte)

N

(00H = not supported)

Data Sheet

T8.1 1274

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

15

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Data Sheet

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V

Package Power Dissipation Capability (T

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

A

Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

O

PERATING RANGE:

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

DD

DD

DD

+0.5V
+2.0V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

See Figures 21 and 22

= 30 pF

L

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

16

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

TABLE 9: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V

Limits

Symbol Parameter

1

I

DD

I

SB

I

ALP

I

RT

I

LI

I

LIW

I

LO

V

IL

V

ILC

V

IH

V

IHC

V

OL

V

OH

1. Address input = V

Active VDD Current

Read 5 MHz 15 mA

1 MHz 4 mA

Program and Erase 30 mA CE#=WE#=V

Concurrent Read/Write 5 MHz 45 mA

1 MHz 35 mA

Standby VDD Current 20 µA CE#, RST#=VDD±0.3V

Auto Low Power VDD Current 20 µA CE#=0.1V, VDD=VDD Max

Reset VDD Current 20 µA RST#=GND

Input Leakage Current 1 µA VIN =GND to VDD, VDD=VDD Max

Input Leakage Current
on WP# pin and RST# pin

Output Leakage Current 1 µA V

Input Low Voltage 0.8 V VDD=VDD Min

Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

Input High Voltage 0.7 V

DDVDD

Input High Voltage (CMOS) VDD-0.3 VDD+0.3 V VDD=VDD Max

Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

ILT/VIHT, VDD=VDD

Max (See Figure 21)

Data Sheet

Test ConditionsFreq Min Max Units

CE#=V

CE#=V

WE#=V
Address inputs=0.1V or V

10 µA WP#=GND to VDD, VDD=VDD Max

RST#=GND to V

OUT

+0.3 V VDD=VDD Max

WE#=OE#=V

IL,

OE#=V

IL,

-0.1V

DD

, OE#=V

IL

IH

IH

IH

DD

, VDD=VDD Max

DD

-0.1V

=GND to VDD, VDD=VDD Max

T9.1 1274

TABLE 10: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T

PU-READ

T

PU-WRITE

1

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 11: CAPACITANCE (T

Power-up to Read Operation 100 µs

Power-up to Write Operation 100 µs

= 25°C, f=1 Mhz, other pins open)

A

T10.0 1274

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 10 pF

I/O

Input Capacitance VIN = 0V 10 pF

T11.0 1274

TABLE 12: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LT H

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

Endurance 10,000 Cycles JEDEC Standard A117

Data Retention 100 Years JEDEC Standard A103

Latch Up 100 + I

DD

mA JEDEC Standard 78

T12.0 1274

17

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Data Sheet

AC CHARACTERISTICS

TABLE 13: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

Symbol Parameter Min Max Units

T

RC

T

CE

T

AA

T

OE

1

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1

T

RP

1

T

RHR

1,2

T

RY

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.

Read Cycle Time 70 ns

Chip Enable Access Time 70 ns

Address Access Time 70 ns

Output Enable Access Time 30 ns

CE# Low to Active Output 0 ns

OE# Low to Active Output 0 ns

CE# High to High-Z Output 16 ns

OE# High to High-Z Output 16 ns

Output Hold from Address Change 0 ns

RST# Pulse Width 500 ns

RST# High before Read 50 ns

RST# Pin Low to Read Mode 20 µs

T13.1 1274

TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

1

T

WPH

1

T

CPH

T

DS

1

T

DH

1

T

IDA

T

SE

T

BE

T

SCE

T

ES

1,2

T

BY

1

T

BR

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.

Program Time 10 µs

Address Setup Time 0 ns

Address Hold Time 40 ns

WE# and CE# Setup Time 0 ns

WE# and CE# Hold Time 0 ns

OE# High Setup Time 0 ns

OE# High Hold Time 10 ns

CE# Pulse Width 40 ns

WE# Pulse Width 40 ns

WE# Pulse Width High 30 ns

CE# Pulse Width High 30 ns

Data Setup Time 30 ns

Data Hold Time 0 ns

Software ID Access and Exit Time 150 ns

Sector-Erase 25 ms

Block-Erase 25 ms

Chip-Erase 50 ms

Erase-Suspend Latency 10 µs

RY/BY# Delay Time 90 ns

Bus Recovery Time 0 µs

T14.1 1274

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

18

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

ADDRESSES

CE#

OE#

V

IH

WE#

DQ

15-0

HIGH-Z

FIGURE 7: READ CYCLE TIMING DIAGRAM

T

T

OLZ

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

T

OH

CHZ

HIGH-Z

DATA VALIDDATA VALID

1274 F05.0

ADDRESSES

555 2AA 555 ADDR

T

AH

T

WP

WE#

T

T

AS

WPH

OE#

T

CH

CE#

T

BY

T

DH

RY/BY#

DQ

15-0

T

CS

T

DS

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

Note: X can be VIL or V

but no other value.

IH,

FIGURE 8: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

T

BP

T

BR

VAL ID

1274 F06.0

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

19

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

T

BP

ADDRESSES

555 2AA 555 ADDR

T

AH

T

CP

CE#

T

T

AS

CPH

OE#

T

CH

WE#

T

BY

T

DH

RY/BY#

DQ

15-0

T

CS

T

DS

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

Note: X can be VIL or VIH, but no other value.

FIGURE 9: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

T

BR

1274 F07.0

VAL ID

ADDRESS A

19-0

CE#

T

OEH

OE#

WE#

T

BY

RY/BY#

DQ

7

DATA DATA# DATA# DATA

FIGURE 10: DATA# POLLING TIMING DIAGRAM

T

CE

T

OES

T

OE

1274 F08.0

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

20

16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

ADDRESSES

T

CE

CE#

T

OEH

OE#

WE#

DQ

6

Data Sheet

T

OE

T

BR

VALID DATA

FIGURE 11: TOGGLE BIT TIMING DIAGRAM

SIX-BYTE CODE FOR CHIP-ERASE

ADDRESSES

CE#

OE#

WE#

RY/BY#

555 2AA 2AA555 555

T

WP

TWO READ CYCLES

WITH SAME OUTPUTS

555

T

BY

T

SCE

T

BR

1274 F09.0

DQ

15-0

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals
are interchageable as long as minimum timings are met. (See Table 14)
X can be V

or VIH, but no other value.

IL

XX55 XX10XX55XXAA XX80 XXAA

VALID

1274 F10.0

FIGURE 12: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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Data Sheet

SIX-BYTE CODE FOR BLOCK-ERASE

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

T

BE

ADDRESSES

555 2AA 2AA555 555

CE#

OE#

T

WP

WE#

RY/BY#

DQ

15-0

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE#
signals are interchageable as long as minimum timings are met. (See Table 14)
BAX = Block Address
X can be VIL or VIH, but no other value.

XX55 XX50XX55XXAA XX80 XXAA

FIGURE 13: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

BA

X

T

T

BY

BR

VAL ID

1274 F11.0

SIX-BYTE CODE FOR SECTOR-ERASE

ADDRESSES

555 2AA 2AA555 555

CE#

OE#

T

WP

WE#

RY/BY#

DQ

15-0

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE#
signals are interchageable as long as minimum timings are met. (See Table 14)
SA
X can be V

= Sector Address

X

or V

IL

but no other value.

IH,

XX55 XX30XX55XXAA XX80 XXAA

FIGURE 14: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

SA

T

SE

X

T

T

BY

BR

VALID

1274 F12.0

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

Data Sheet

ADDRESSES

555 2AA 555 0000 0001

CE#

OE#

T

WP

WE#

T

WPH

DQ

15-0

Device ID = 734BH for SST36VF1601E and 734AH for SST36VF1602E
Note: X can be VIL or VIH, but no other value.

FIGURE 15: SOFTWARE ID ENTRY AND READ

T

IDA

T

AA

00BF Device IDXX55XXAA XX90

1274 F13.0

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESSES

555 2AA 555

CE#

OE#

T

WP

WE#

DQ

15-0

Note: X can be VIL or V

IH,

FIGURE 16: CFI ENTRY AND READ

T

WPH

XX55XXAA XX98

but no other value.

T

IDA

T

AA

1274 F14.0

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

23

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESSES

DQ

15-0

555 2AA 555

XXAA XX55 XXF0

CE#

OE#

T

WP

WE#

T

WPH

Note: X can be VIL or VIH, but no other value.

FIGURE 17: SOFTWARE ID EXIT/CFI EXIT

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

T

IDA

1274 F15.0

ADDRESS A

19-0

555 2AA 555

CE#

OE#

T

T

WP

IDA

WE#

T

DQ

WPH

15-0

XX55XXAA XX88

SW0 SW1 SW2

Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

but no other value.

X can be V

IL

or V

IH,

T

AA

1274 F16.0

FIGURE 18: SEC ID ENTRY

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

RY/BY#

0V

T

RST#

CE#/OE#

FIGURE 19: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

RY/BY#

RP

T

RHR

T

RY

Data Sheet

1274 F17.0

RST#

T

RP

CE#

OE#

T

BR

FIGURE 20: RST# TIMING DIAGRAM (DURING SECTOR- OR BLOCK-ERASE OPERATION)

1274 F18.0

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

V

IHT

V

V

ILT

AC test inputs are driven at V
for inputs and outputs are V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

FIGURE 21: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO DUT

V

OT

1274 F19.0

(0.1 VDD) for a logic “0”. Measurement reference points

ILT

Note: V

- V

- V

- V

- V

INPUT

OUTPUT

INPUT

INPUT

Tes t

Tes t

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

1274 F20.0

FIGURE 22: A TEST LOAD EXAMPLE

C

L

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

FIGURE 23: PROGRAM ALGORITHM

Load

Address/Data

Wait for end of

Program (T

BP

,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

1274 F21.0

Note: X can be VIL or VIH, but no other value.

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Internal Timer

Program/Erase

Initiated

Wait TBP,

T

T

SCE

SE

,

or T

BE

Program/Erase

Completed

No

Toggle Bit

Program/Erase

Initiated

Read

byte/word

Read same

byte/word

Does DQ

6

match?

Ye s

No

Data# Polling

Program/Erase

Initiated

Read DQ

Is DQ

7

=

7

true data?

Ye s

Program/Erase

Completed

FIGURE 24: WAIT OPTIONS

Program/Erase

Completed

1274 F22.0

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

Software Product ID Entry

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait T

IDA

CFI Query Entry

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 555H

Wait T

IDA

Sec ID Query Entry

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX88H

Address: 555H

Wait T

IDA

Read Software ID

X can be VIL or VIH, but no other value

Read CFI data

Read Sec ID

FIGURE 25: SOFTWARE PRODUCT ID/CFI/SEC ID ENTRY COMMAND FLOWCHARTS

1274 F23.0

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

29

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Wait T

IDA

Return to normal

operation

X can be VIL or V

Load data: XXF0H

Address: XXH

Wait T

Return to normal

operation

but no other value

IH,

IDA

1274 F24.0

FIGURE 26: SOFTWARE PRODUCT ID/CFI/SEC ID EXIT COMMAND FLOWCHARTS

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

Chip-Erase

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Sector-Erase

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Block-Erase

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Wait T

SCE

Chip erased

to FFFFH

Note: X can be VIL or V

Load data: XX30H

Address: SA

Wait T

X

SE

Sector erased

to FFFFH

but no other value.

IH,

Load data: XX50H

Address: BA

Wait T

X

BE

Block erased

to FFFFH

1274 F25.0

FIGURE 27: ERASE COMMAND SEQUENCE

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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Data Sheet

PRODUCT ORDERING INFORMATION

SST 36 VF 1601E - 70 - 4C - B3K E

XX

XX XXX XX - XXX -XX-XXX X

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

Environmental Attribute

1

E

= non-Pb

Package Modifier

K = 48 balls or leads

Package Type

B3 = TFBGA (6mm x 8mm)
E =TSOP (type 1, die up, 12mm x 20mm)

Temperature Range

C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Bank Split

1 = 12 Mbit + 4 Mbit
2 = 4 Mbit + 12 Mbit

Device Density

160 = 1 Mbit x16 or

2 Mbit x8

Volta g e

V = 2.7-3.6V

Product Series

36 = Concurrent SuperFlash

1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.

Valid combinations for SST36VF1601E

SST36VF1601E-70-4C-B3KE SST36VF1601E-70-4C-EKE
SST36VF1601E-70-4I-B3KE SST36VF1601E-70-4I-EKE

Valid combinations for SST36VF1602E

SST36VF1602E-70-4C-B3KE SST36VF1602E-70-4C-EKE
SST36VF1602E-70-4I-B3KE SST36VF1602E-70-4I-EKE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

PACKAGING DIAGRAMS

8.00 ± 0.20

6

5

4

3

2

1

A B C D E F G H

6.00 ± 0.20

4.00

0.80

BOTTOM VIEWTOP VIEW

5.60

0.80

H G F E D C B A

Data Sheet

0.45 ± 0.05
(48X)

6

5

4

3

2

1

A1 CORNER

SIDE VIEW

SEATING PLANE

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1.10 ± 0.10

0.12

0.35 ± 0.05

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K

A1 CORNER

1mm

48-tfbga-B3K-6x8-450mic-4

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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Data Sheet

Pin # 1 Identifier

16 Mbit Concurrent SuperFlash

SST36VF1601E / SST36VF1602E

1.05

0.95

0.50

BSC

0.27

12.20

11.80

0.17

18.50

18.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

20.20

19.80

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM
SST PACKAGE CODE: EK

0.15

0.05

DETAIL

1.20
max.

0˚- 5˚

0.70

0.50

1mm

48-tsop-EK-8

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E

Data Sheet

TABLE 15: REVISION HISTORY

Number Description Date

00

• Initial release of data sheet

01

• Updates to data sheet Tables 1, 4, 5, 8, 9, and 13. Added RoHS compliance information
on page 1 and in the “Product Ordering Information” on page 33

• Updated sector information in Table 8, “Device Geometry Information” on page 16

• Updated Active Current values and test conditions in Table 9 on page 18

• Updated OE timings in Table 13 on page 19

• Added a Reset footnote to Table 4 on page 13

• Updated the footnote for Table 1 on page 4

• Corrected the Address Format in footnote 1 in Table 5 on page 14

• Clarified the solder temperature profile under “Absolute Maximum Stress Ratings” on

page 17

02

• Updated “Erase-Suspend/Erase-Resume Operations” on page 3

• Updated T

03

• Made changes to support Pb-free packages only

parameter from 20 µs to 10 µs in Table 14 on page 19

ES

Oct 2004

Mar 2005

Jul 2005

Nov 2005

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone [phone] • Fax [phone]

www.SuperFlash.com or www.sst.com

©2005 Silicon Storage Technology, Inc. S71274-03-000 11/05

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