Datasheet SST36VF1601-70-4E-EK, SST36VF1601-70-4E-BK, SST36VF1601-70-4C-EK, SST36VF1601-70-4C-BK Datasheet (Silicon Storage Technology)

FEATURES:

16 Mbit Concurrent SuperFlash

SST36VF1601

SST36V160116Mb (x16) Concurrent SuperFlash

Data Sheet

• Organized as 1M x16

• Dual Bank Architecture for Concurrent Read/Write Operation

– 16 Mbit Bottom Sector Protection

- SST36VF1601: 12 Mbit + 4 Mbit

• Single 2.7-3.6V for Read and Write Operations

• Superior Reliability

– Endurance: 100,000 cycles (typical) – Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 25 mA – Standby Current: 4 µA

• Hardware Sector Protection/WP# Input Pin

– Protects 4 outermost sectors (4 KWord) in the

larger bank by driving WP# low and unprotects by driving WP# high

• Hardware Reset Pin (RST#)

– Resets the internal state machine to reading

array data

• Sector-Erase Capability

– Uniform 1 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Fast Read Access Time

– 70 ns

• Latched Address and Data

• Fast Erase and Word-Program (typical):

– Sector-Erase Time: 18 ms – Block-Erase Time: 18 ms – Chip-Erase Time: 70 ms – Word-Program Time: 14 µs – Chip Rewrite Time: 8 seconds

• Automatic Write Timing

– Internal V

Generation

PP

• End-of-Write Detection

– Toggle Bit – Data# Polling – Ready/Busy# pin

• CMOS I/O Compatibility

• Conforms to Common Flash Memory Interface (CFI)

• JEDEC Standards

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm) – 48-ball TFBGA (8mm x 10mm)

PRODUCT DESCRIPTION

The SST36VF1601 is 1M x16 CMOS Concurrent Read/ Write Flash Memory manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.The SST36VF1601 writes (Program or Erase) with a 2.7-3.6V power supply. The SST36VF1601 device conforms to JEDEC standard pinouts for x16 memories.

Featuring high performance Word-Program, the SST36VF1601 device provides a typical Word-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the SST36VF1601 device has on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the

1

SST36VF1601 device is offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST36VF1601 is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST36VF1601 significantly improves performance and reliability, while lowering power consumption. The SST36VF1601 inherently uses less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST36VF1601 also improves flexibility while lowering the cost for program, data, and configuration storage applications.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Concurrent SuperFlash and CSF are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST36VF1601 is offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 2 and 3 for pinouts.

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Concurrent Read/Write Operation

Dual bank architecture of SST36VF1601 device allows the Concurrent Read/Write operation whereby the user can read from one bank while program or erase in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank.

ONCURRENT READ/WRITE STATE

C

Bank 1 Bank 2

Read No Operation

Read Write

Write Read

Write No Operation

No Operation Read

No Operation Write

Note: For the purposes of this table, write means to perform Block-,

Sector-, or Chip-Erase or Word-Program operations as applicable to the appropriate bank.

Read Operation

The Read operation of the SST36VF1601 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data on the output pins.

The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4).

Word-Program Operation

The SST36VF1601 is programmed on a word-by-word basis. Before programming, one must ensure that the sector, in which the word which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed typically within 10 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.

Sector- (Block-) Erase Operation

The Sector- (Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST36VF1601 offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 1 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. See Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored.

Chip-Erase Operation

The SST36VF1601 provides a Chip-Erase operation, which allows the user to erase all unprotected sectors/ blocks to the “1” state. This is useful when the device must be quickly erased.

2

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid Read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 22 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST36VF1601 provides one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/ BY#) output pin. The software detection includes two status bits: Data# Polling (DQ Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), a Data# Polling (DQ be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

) and Toggle Bit (DQ6). The End-of-

7

) or Toggle Bit (DQ6) read may

7

‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling (DQ

) timing diagram and Figure 20 for a

7

flowchart. There is a 1 µs bus recovery time (T before valid data can be read on the data bus. New commands can be entered immediately after DQ true data.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ

will produce alternating 1s

6

and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ stop toggling. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 20 for a flowchart. There is a 1 µs bus recovery time (T

) required before

BR

valid data can be read on the data bus. New commands can be entered immediately after DQ

no longer toggles.

6

Data Protection

7

The SST36VF1601 provides both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

) required

BR

becomes

7

bit will

6

Ready/Busy# (RY/BY#)

The SST36VF1601 includes a Ready/Busy# (RY/BY#) output signal. RY/BY# is actively pulled low while during an internal Erase or Program operation is in progress. RY/BY# is an open drain output that allows several devices to be tied in parallel to V BY# is high impedance whenever CE# is high or RST# is low. There is a 1 µs bus recovery time (T valid data can be read on the data bus. New commands can be entered immediately after RY/BY# goes high.

via an external pull up resistor. RY/

DD

) required before

BR

Power Up/Down Detection: The Write operation is

V

DD

inhibited when V

Write Inhibit Mode:

is less than 1.5V.

DD

Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Hardware Block Protection

The SST36VF1601 provides a hardware block protection which protects the outermost 4 KWord in the larger bank. The block is protected when WP# is held low. See Figure 1

Data# Polling (DQ7)

When the SST36VF1601 is in the internal Program operation, any attempt to read DQ of the true data. Once the Program operation is completed,

will produce true data. During internal Erase opera-

DQ

7

tion, any attempt to read DQ internal Erase operation is completed, DQ

will produce the complement

7

will produce a ‘0’. Once the

7

will produce a

7

for Block-Protection location.

A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed.

3

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least T

any in-progress operation will terminate and

RP,

return to Read mode (see Figure 16). When no internal Program/Erase operation is in progress, a minimum period of T

is required after RST# is driven high before a valid

RHR

Read can take place (see Figure 15).

The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST36VF1601 provides the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST36VF1601 is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within T

can be VIL or VIH, but no other value during any SDP

DQ

8

The contents of DQ15-

RC.

command sequence.

Common Flash Memory Interface (CFI)

The SST36VF1601 also contains the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 5555H in the last byte

sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

Product Identification

The Product Identification mode identifies the device and manufacturer. For details, see Table 4 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 21 for the Software ID Entry command sequence flowchart.

TABLE 1: P

Manufacturer’s ID 0000H 00BFH

Device ID

SST36VF1601 0001H 2761H

RODUCT IDENTIFICATION

Word Da ta

T1.1 373

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for the software command code, Figure 14 for timing waveform and Figure 21 for a flowchart.

4

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

Memory Address

RST#

CE#

WP#

WE#

OE#

RY/BY#

Address

Buffers

Control

Logic

(4 KWord Sector Protection)

SuperFlash Memory

12 Mbit Bank

SuperFlash Memory

4 Mbit Bank

I/O Buffers

DQ15 - DQ

373 ILL B37.5

0

5

16 Mbit Concurrent SuperFlash

Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors

SST36VF1601

Data Sheet

4 KWord Sector Protection

(4- 1 KWord Sectors)

FFFFFH

F8000H

F7FFFH

F0000H

EFFFFH

E8000H

E7FFFH

E0000H

DFFFFH

D8000H

D7FFFH

D0000H CFFFFH C8000H

C7FFFH

C0000H

BFFFFH

B8000H

B7FFFH

B0000H

AFFFFH

A8000H

A7FFFH

A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH

10000H 00FFFFH 008000H 007FFFH

001000H 000FFFH 000000H

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Bank 2

Bank 1

373 ILL F38.2

FIGURE 1: SST36VF1601, 1 MBIT X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

6

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

A15 A14 A13 A12 A11 A10

A9 A8

A19

NC

WE#

RST#

NC

WP#

RY/BY#

A18 A17

A7 A6 A5 A4 A3 A2 A1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Standard Pinout

Top View

Die Up

FIGURE 2: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

373 ILL F01b.3

A16 NC V

SS

DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

DD

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# V

SS

CE# A0

FIGURE 3: P

TOP VIEW (balls facing down)

SST36VF1601

6

5

4

3

2

A13

A9

WE#

RY/BY#

A7

A12

A8

RST#

WP#

A17

A14

A10

NC

A18

A6

A15

A11

A19

NC

A5

A16

DQ7

DQ5

DQ2

DQ0

NC

DQ14

DQ12

DQ10

DQ8

DQ15

DQ13

V

DD

DQ11

DQ9

1

A3

A4

A2

A1

A0

CE#

OE#

A B C D E F G H

IN ASSIGNMENTS FOR 48-BALL TFBGA (8MM X 10MM)

V

SS

DQ6

DQ4

DQ3

DQ1

V

SS

373 ILL F01a.7

7

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

TABLE 2: PIN DESCRIPTION

Symbol Name Functions

A

19-A0

-DQ

DQ

15

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

RST# Hardware Reset To reset and return the device to Read mode

RY/BY# Ready/Busy# To output the status of a Program or Erase Operation

WP# Write Protect To protect and unprotect the bottom 4 sectors from Erase or Program operation.

V

DD

V

SS

NC No Connection Unconnected pins

Address Inputs To provide memory addresses. During Sector-Erase and Hardware Sector Protection,

address lines will select the sector. During Block-Erase A19-A15 address lines

A

19-A10

will select the block.

Data Input/output To output data during Read cycles and receive input data during Write cycles

0

Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.

RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read.

Power Supply To provide 2.7-3.6V power supply voltage

Ground

T2.6 373

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V

Program V

Erase V

Standby V

IL

IH

Write Inhibit X V

XXV

Product Identification

Software Mode V

1. X can be VIL or VIH, but no other value.

2. Device ID = 2761H

IL

V

X X High Z X

V

IL

IH

V

IL

V

IL

D

OUT

D

IN

1

X

Sector or block address,

A

IN

A

IN

XXH for Chip-Erase

IL

XHigh Z / D

IH

V

IH

High Z / D

Manufacturer’s ID (00BFH) See Table 4

Device ID

OUT

2

X

T3.6 373

8

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command Sequence

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry

5,6

CFI Query Entry 5555H AAH 2AAAH 55H 5555H 98H

Software ID Exit/ CFI Exit

1. Address format A14-A0 (Hex), Addresses A19- A15 can be VIL or VIH, but no other value, for the Command sequence.

-DQ8 can be VIL or VIH, but no other value, for the Command sequence

2. DQ

15

3. WA = Program word address for Sector-Erase; uses A19-A10 address lines

4. SA

X

for Block-Erase; uses A19-A15 address lines

BA

X

5. The device does not remain in Software Product Identification mode if powered down.

6. With A

= 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0

19-A1

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data

4

30H

X

4

50H

X

5555H AAH 2AAAH 55H 5555H 90H

5555H AAH 2AAAH 55H 5555H F0H

T4.4 373

SST36VF1601 Device ID = 2761H, is read with A

0

= 1

2

TABLE 5: CFI QUERY IDENTIFICATION STRING1

Address Data Data

10H 0051H Query Unique ASCII string “QRY” 11H 0052H 12H 0059H 13H 0001H Primary OEM command set 14H 0007H 15H 0000H Address for Primary Extended Table 16H 0000H 17H 0000H Alternate OEM command set (00H = none exists) 18H 0000H 19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

1. Refer to CFI publication 100 for more details.

T5.0 373

9

TABLE 6: SYSTEM INTERFACE INFORMATION

Address Data Data

1BH 0027H V

1CH 0036H V

1DH 0000H V

1EH 0000H V

1FH 0004H Typical time out for Word-Program 2

20H 0000H Typical time out for min size buffer program 2

21H 0004H Typical time out for individual Sector/Block-Erase 2

22H 0006H Typical time out for Chip-Erase 2

23H 0001H Maximum time out for Word-Program 2

24H 0000H Maximum time out for buffer program 2

25H 0001H Maximum time out for individual Sector/Block-Erase 2

26H 0001H Maximum time out for Chip-Erase 2

Min (Program/Erase)

DD

-DQ4: Volts, DQ3-DQ0: 100 millivolts

DQ

7

Max (Program/Erase)

DD

DQ

-DQ4: Volts, DQ3-DQ0: 100 millivolts

7

min (00H = no VPP pin)

PP

max (00H = no VPP pin)

PP

N

µs (24 = 16 µs)

N

ms (26 = 64 ms)

N

times typical (21 x 24 = 32 µs)

N

times typical

N

times typical (21 x 26 = 128 ms)

16 Mbit Concurrent SuperFlash

SST36VF1601

N

µs (00H = not supported)

N

ms (24 = 16 ms)

N

times typical (21 x 24 = 32 ms)

Data Sheet

T6.0 373

TABLE 7: DEVICE GEOMETRY INFORMATION

Address Data Data

27H 0015H Device size = 2 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H 2AH 0000H Maximum number of bytes in multi-byte write = 2 2BH 0000H 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0003H y = 1023 + 1 = 1024 sectors (03FFH = 1023) 2FH 0008H

30H 0000H z = 8 x 256 Bytes = 4 KByte/sector (0008H = 8)

31H 003FH Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 0000H y = 31 + 1 = 32 blocks (001FH = 31)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

N

Bytes (15H = 21; 221 = 2 MByte)

N

(00H = not supported)

T7.3 373

10

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

PERATING RANGE:

O

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V

Extended -20°C to +85°C 2.7-3.6V

DD

+0.5V +2.0V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

See Figures 17 and 18

= 30 pF

L

11

TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V

Limits

Symbol Parameter

I

DD

I

SB

I

RT

I

LI

I

LO

V

IL

V

ILC

V

IH

V

IHC

V

OL

V

OH

Active VDD Current Address input=VIL/VIH, at f=1/TRC Min,

Read 35 mA CE#=OE#=V

Program and Erase 40 mA CE#=V

Concurrent Read/Write 75 mA

Standby VDD Current 20 µA CE#=V

Reset VDD Current 20 µA RST# = VSS ± 0.3V

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

Output Leakage Current 1 µA V

Input Low Voltage 0.8 V VDD=VDD Min

Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

Input High Voltage 0.7 V

DD

Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

Test ConditionsMin Max Units

V

DD=VDD

OUT

VVDD=VDD Max

Max

, WE#=VIH, all I/Os open

IL

, OE#=V

IL

IHC

IH

, VDD=VDD Max

=GND to VDD, VDD=VDD Max

T8.6 373

TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

T

1

PU-READ

PU-WRITE

1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

Power-up to Write Operation 100 µs

TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

1

C

I/O

1

C

IN

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance V

= 0V 10 pF

I/O

Input Capacitance VIN = 0V 10 pF

TABLE 11: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

1

N

END

1

T

DR

1

I

LT H

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

Data Retention 100 Years JEDEC Standard A103

Latch Up 100 + I

DD

mA JEDEC Standard 78

T9.2 373

T10.0 373

T11.1 373

12

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

AC CHARACTERISTICS

TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

SST36VF1601-70

Symbol Parameter

T

RC

T

CE

T

AA

T

OE

1

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1

T

RP

1

T

RHR

1,2

T

RY

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase operations.

Read Cycle Time 70 ns

Chip Enable Access Time 70 ns

Address Access Time 70 ns

Output Enable Access Time 35 ns

CE# Low to Active Output 0 ns

OE# Low to Active Output 0 ns

CE# High to High-Z Output 20 ns

OE# High to High-Z Output 20 ns

Output Hold from Address Change 0 ns

RST# Pulse Width 500 ns

RST# High before Read 50 ns

RST# Pin Low to Read Mode 150 µs

UnitsMin Max

T12.9 373

TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

1

T

WPH

1

T

CPH

T

DS

1

T

DH

1

T

IDA

T

SE

T

BE

T

SCE

1

T

BY

T

BR

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Word-Program Time 20 µs

Address Setup Time 0 ns

Address Hold Time 40 ns

WE# and CE# Setup Time 0 ns

WE# and CE# Hold Time 0 ns

OE# High Setup Time 0 ns

OE# High Hold Time 10 ns

CE# Pulse Width 40 ns

WE# Pulse Width 40 ns

WE# Pulse Width High 30 ns

CE# Pulse Width High 30 ns

Data Setup Time 30 ns

Data Hold Time 0 ns

Software ID Access and Exit Time 150 ns

Sector-Erase 25 ms

Block-Erase 25 ms

Chip-Erase 100 ms

RY/BY# Delay Time 90 ns

Bus Recovery Time 1 µs

T13.6 373

13

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

ADDRESSES

CE#

OE#

IH

HIGH-Z

DQ

WE#

15-0

FIGURE 4: READ CYCLE TIMING DIAGRAM

T

OLZV

CLZ

T

RC

T

CE

T

OE

T

AA

T

OHZ

T

OH

DATA VALIDDATA VALID

CHZ

HIGH-Z

373 ILL F22.1

ADDRESSES

WE#

OE#

CE#

RY/BY#

DQ

15-0

T

AS

Note: X can be VIL or VIH, but no other value.

5555 2AAA 5555 ADDR

T

AH

T

CP

T

CPH

T

CH

T

CS

T

DS

XXAA XX55 XXA0 DATA

SW0 SW1 SW2

WORD

(ADDR/DATA)

T

BY

T

DH

FIGURE 5: WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM

T

BP

T

BR

VALID

373 ILL F23.11

14

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

ADDRESSES

CE#

OE#

WE#

T

AS

5555 2AAA 5555 ADDR

T

AH

T

CP

T

CPH

T

BP

T

CH

RY/BY#

DQ

15-0

T

CS

XXAA XX55 XXA0 DATA

SW0 SW1 SW2

Note: X can be VIL or VIH, but no other value.

T

(ADDR/DATA)

DS

WORD

T

BY

T

DH

FIGURE 6: CE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM

ADDRESSES

T

CE

CE#

T

OEH

OE#

T

OES

T

BR

373 ILL F24.10

VALID

T

OE

WE#

T

BR

DQ

7

DATA # DATA #

DATA #

VALID DATA

373 ILL F41.0

FIGURE 7: DATA# POLLING TIMING DIAGRAM

15

ADDRESSES

CE#

OE#

WE#

DQ

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

T

CE

T

OEH

6

OET

T

BR

VALID DATA

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

SIX-BYTE CODE FOR CHIP-ERASE

ADDRESSES

CE#

OE#

WE#

RY/BY#

5555 2AAA 2AAA5555 5555

T

WP

TWO READ CYCLES

WITH SAME OUTPUTS

5555

373 ILL F42.1

T

SCE

T

BY

T

BR

DQ

15-0

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals

are interchageable as long as minimum timings are met. (See Table 13) X can be VIL or VIH, but no other value.

XX55 XX10XX55XXAA XX80 XXAA

VALID

373 ILL F27.6

FIGURE 9: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

16

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

SIX-BYTE CODE FOR BLOCK-ERASE

T

BE

ADDRESSES

CE#

OE#

WE#

RY/BY#

DQ

15-0

5555 2AAA 2AAA5555 5555

T

WP

XX55 XX50XX55XXAA XX80 XXAA

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE#

signals are interchageable as long as minimum timings are met. (See Table 13) BAX = Block Address X can be VIL or VIH, but no other value.

FIGURE 10: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

BA

X

T

BY

BR

VALID

373 ILL F28.8

SIX-BYTE CODE FOR SECTOR-ERASE

ADDRESSES

CE#

OE#

WE#

RY/BY#

DQ

15-0

5555 2AAA 2AAA5555 5555

T

WP

SW0 SW1 SW2 SW3 SW4 SW5

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE#

signals are interchageable as long as minimum timings are met. (See Table 13) SAX = Sector Address X can be VIL or VIH, but no other value.

SA

XX55 XX30XX55XXAA XX80 XXAA

FIGURE 11: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

T

SE

X

T

BY

BR

VALID

373 ILL F29.8

17

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

ADDRESSES

CE#

OE#

WE#

DQ

15-0

5555 2AAA 5555 0000 0001

T

WP

T

WPH

SW0 SW1

Device ID = 2761H for SST36VF1601 Note: X can be VIL or VIH, but no other value.

SW2

FIGURE 12: SOFTWARE ID ENTRY AND READ

T

IDA

T

AA

00BF

Device IDXX55XXAA XX90

373 ILL F30.6

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESSES

CE#

OE#

WE#

DQ

15-0

5555 2AAA 5555

T

WP

SW0 SW1 SW2

Note: X can be VIL or VIH, but no other value.

FIGURE 13: CFI ENTRY AND READ

T

WPH

XX55XXAA XX98

T

IDA

T

AA

373 ILL F31.2

18

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESSES

DQ

15-0

CE#

OE#

WE#

5555 2AAA 5555

XXAA XX55 XXF0

T

WP

T

WPH

SW0 SW1 SW2

Note: X can be VIL or VIH, but no other value.

FIGURE 14: SOFTWARE ID EXIT/CFI EXIT

RY/BY#

0V

T

RST#

RP

T

IDA

373 ILL F32.4

CE#/OE#

T

RHR

373 ILL F43.1

FIGURE 15: RST# TIMING (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

T

RY

RY/BY#

RST#

T

RP

CE#

OE#

FIGURE 16: RST# T

IMING (DURING SECTOR- OR BLOCK-ERASE OPERATION)

19

T

BR

373 ILL F44.3

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

V

IHT

V

ILT

AC test inputs are driven at V for inputs and outputs are V

V

IT

(0.9 VDD) for a logic “1” and V

IHT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

IT

REFERENCE POINTS OUTPUTINPUT

FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO DUT

V

OT

373 ILL F14.3

(0.1 VDD) for a logic “0”. Measurement reference points

ILT

Note: V

- V

INPUT

OUTPUT

INPUT

Tes t

Te s t

HIGH Test

LOW Test

IT

V

OT

V

IHT

V

ILT

TO TESTER

373 ILL F15.1

FIGURE 18: A TEST LOAD EXAMPLE

C

L

20

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Note: X can be VIL or VIH, but no other value.

FIGURE 19: WORD-PROGRAM ALGORITHM

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

373 ILL F33.3

21

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

Internal Timer

Program/Erase

Initiated

Wait TBP,

T

SCE, TSE

or T

BE

Program/Erase

Completed

No

Toggle Bit

Program/Erase

Initiated

Read word

Read same

word

Does DQ

6

match?

Ye s

No

Data# Polling

Program/Erase

Initiated

Read DQ

7

Is DQ7 =

true data?

Ye s

Program/Erase

Completed

FIGURE 20: WAIT OPTIONS

Program/Erase

Completed

373 ILL F34.0

22

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

CFI Query Entry

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX98H

Address: 5555H

Wait T

IDA

Read CFI data

Software Product ID Entry

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

Wait T

IDA

Read Software ID

Software ID Exit/CFI Exit

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Wait T

IDA

Return to normal

operation

Note: X can be VIL or VIH, but no other value.

373 ILL F35.2

FIGURE 21: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS

23

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

Chip-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Sector-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Block-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Wait T

SCE

Chip erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

Load data: XX30H

Address: SA

Wait T

X

SE

Sector erased

to FFFFH

Load data: XX50H

Address: BA

Wait T

X

BE

Block erased

to FFFFH

373 ILL F36.2

FIGURE 22: ERASE COMMAND SEQUENCE

24

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

SST36V

F1601 -XXX -XX -XX

Package Modifier

K = 48 balls

Package Type

B = TFBGA (8mm x 10mm) E = TSOP (type 1, die up, 12mm x 20mm)

Temperature Range

C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Bank Split

1 = 12 Mbit + 4 Mbit

Device Density

160 = 1M x16

Volt ag e

V = 2.7-3.6V

Valid combinations for SST36VF1601

SST36VF1601-70-4C-EK SST36VF1601-70-4C-BK SST36VF1601-70-4E-EK SST36VF1601-70-4E-BK

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

25

PACKAGING DIAGRAMS

Pin # 1 Identifier

16 Mbit Concurrent SuperFlash

SST36VF1601

1.05

0.95

0.50

BSC

0.27

12.20

11.80

0.17

Data Sheet

18.50

18.30

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

20.20

19.80

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK

TOP VIEW

8

7

6

5

4

3

2

1

A1 CORNER

A B C D E F G H

4.00

8.00 ± 0.20

0.80

1.20 max.

H G F E D C B A

DETAIL

48-tsop-EK-ILL.7

1mm

BOTTOM VIEW

10.00 ± 0.20

5.60

0.15

0.05

0.70

0.50

0˚- 5˚

0.80

A1 CORNER

8

7

6

5

4

3

2

1

0.30 ± 0.05 (48X)

SIDE VIEW

SEATING PLANE

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.1 (±.05) mm.

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

48-

BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM

1.10 ± 0.10

0.21 ± 0.05

48ba-tfbga-BK-8x10-300mic-ILL.10

0.15

1mm

SST PACKAGE CODE: BK

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com

26

Datasheet SST36VF1601-70-4E-EK, SST36VF1601-70-4E-BK, SST36VF1601-70-4C-EK, SST36VF1601-70-4C-BK Datasheet (Silicon Storage Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual