Datasheet SSD1730QL3 Datasheet (Solomon Systech)

TABLE OF CONTENTS

1. GENERAL DESCRIPTION .......................................................................................................................1

2. FEATURES ...............................................................................................................................................1

3. ORDERING INFORMATION.....................................................................................................................1

5. FUNCTIONAL BLOCK DESCRIPTIONS................................................................................................3

LCD Polarity Reverse Signal Generator...............................................................................................3

Clock Signal Generator .........................................................................................................................3

-V1 Discharge Circuit.............................................................................................................................3

Column Driver Voltage Generator ........................................................................................................3

Row Driver Voltage Generator ..............................................................................................................3

Row Driver Voltage Conversion Circuit...............................................................................................3

VDD_ROW Voltage Generator...............................................................................................................3

+V1 Voltage Generator...........................................................................................................................3

6. PINS ASSIGNMENT .................................................................................................................................4

7. PIN DESCRIPTION...................................................................................................................................5

8. DC CHARACTERISTICS..........................................................................................................................8

Maximum Ratings...................................................................................................................................8

9. Electrical Characteristics ..................................................................................................................9

10. AC CHARACTERISTICS......................................................................................................................10

Input Timing Characteristics...............................................................................................................10

Output Timing Characteristics............................................................................................................11

11. EXPLANATION OF FUNCTIONS.........................................................................................................12

LCD Polarity Reverse Signal Generator.............................................................................................13

Clock Signal Generator .......................................................................................................................14

Driver Voltage Generator.....................................................................................................................14

i

Contrast Control Circuit ......................................................................................................................15

+V1 Voltage Generator.........................................................................................................................15

-V1 and +V1 Discharge Circuit............................................................................................................16

Power Up and Power Down Sequence...............................................................................................16

12. APPLICATION CIRCUIT (SSD1730 5X STEP-UP MODE).................................................................17

13. PACKAGE DIMENSIONS.....................................................................................................................18

ii

SOLOMON SYSTECH LIMITED

SOLOMON SYSTECH LIMITED

SOLOMON SYSTECH LIMITEDSOLOMON SYSTECH LIMITED

SEMICONDUCTOR TECHNICAL DATA

SSD1730

Advanced Infomation

SSD1730 MLA Power Chip
CMOS

1. GENERAL DESCRIPTION

The SSD1730 is a power chip for operating four-line MLA (Multi Line Addressing) LCD drivers. It consists of a
CMOS charge pump-type voltage converter that can generate all the bias voltages required for the four-line MLA
drive based on a single power supply input.

This can be used for the system that is formed by a column (segment) driver such as SSD1870 and a row
(common) driver such as SSD1881. Such type of display system is able to produce a module with lower power
consumption when comparing with the conventional driving method.

2. FEATURES

! Single Power Supply Operation, +2.4V to +3.6V

! Low current consumption
! Two step-up modes, 5X or 6X step-up by internal charge pump DC/DC converter
! Internal LCD voltage generator to generate all LCD voltages required for 4-line MLA driving
! External contrast control
! Internal –V1 discharge circuit to discharge the residual charge at the row driver negative

voltage-side power supply voltage terminal –V1

! Internal “power off” function using an external signal
! Equipped internally with a LCD polarity reverse signal generator
! Polarity reversed period in the range of 2P to 17P

! Available in 48 pin QFP package (0.5 mm terminal pitch)

3. ORDERING INFORMATION

Ordering Part Number Package Dimension Package Form

SSD1730QL3 7 mm x 7mm 48 LQFP

Table 1 - Ordering Information

This document contai ns information on a new product. Specifications and information herein are subject to c hange without notice.
IC manufactured under Motif l i cense including U.S. Patent No. 5,420,604

Copyright  2001 SOLOMON Systech Limited

Rev 2.0
04/2002

4. BLOCK DIAGRAM

VDD_PWR

VSS

L0
L1
L2
L3

FR

XFR

LP

XSLP

C1P

LCD Polarity
Reverse Signal
Generator

Column (S e g ment)
Driver Voltage Gener-

ator

C1N
C2P
C2N

-V3
C3P

C3N
V2

C4P
C4N

-V2

Clock Signal
Generator

Row (Common) Driver
Voltage Generator

Row Driver Voltage

Conversion Circuit

C1PB
C1NB

-V3B
HC

C5P
C5N
VEM
C6N
VEE

SOLOMON

-V1 Discharge Circuit

VDD_ROW Voltage Generator

+V1 Voltage Generator

Figure 1 - Block Diagram

Rev 2.0
04/2002

SSD1730

C8N
VDD_ROW

C7N

-V1
AB

XBB

2

5. FUNCTIONAL BLOCK DESCRIPTIONS

LCD Polarity Reverse Signal Generator

This circuit generates the polarity reverse signals FR and XFR from the pulse signal LP. The polarity reversal interval is
controlled by four pins L0, L1, L2 & L3 and the range is from 2P to 17P (1P is equal to one LP period), Table 15 shows
their relationship. The polarity of the FR signal and the XFR signal are mutually opposite, so that the upper and lower
screens can be driven mutually in opposite phases when a two-screen drive panel is used.

Clock Signal Generator

This circuit generates the clock for the charge pump from the pulse signal LP. W hen the display control signal XSLP is

set to VSS, the clock will stop and the voltage converter will halt. For normal display mode, XSLP must be tied to
VDD_PWR. Besides, this circuit also generates the signals AB & XBB which are the clocks for the column driver voltage
generator and the row driver voltage generator. Figure 7 shows their timing characteristics.

-V1 Discharge Circuit

When the display is off or the power is off, this circuit will discharge the residual charges at the negative voltage lev el-side

power supply voltage terminal –V1 of the row driver.

Column Driver Voltage Generator

This circuit accompanying with external components generates voltages for column driver. In SSD1730, three voltage
outputs including V2, -V2 and -V3 will be generated and their voltage levels are based on the supply voltage VDD_PWR.
Their relationship is V2 = VDD_PWR/2, -V2 = -(VDD_PWR/2) and –V3 = -VDD_PWR.

Row Driver Voltage Generator

This voltage generator consists of three circuits (1) Row driver voltage conversion circuit, (2) VDD_ROW voltage
generator and (3) +V1 voltage generator.

Row Driver Voltage Conversion Circuit

This circuit generates VEE voltage which is used to generate +V1 & -V1 power supply voltages for row
driver. There ar e two s tep-up modes 5X and 6X which are s et by the HC pin. When HC pin is tied to VSS, 5X
step-up mode is chosen. When HC pin is tied to -V3B, 6X step-up mode is chosen.
In SSD1730, VDD_PWR is taken as the reference, VEE is equal to -4 x VDD_PW R at 5X step-up mode
while VEE is equal to -5 x VDD_PWR at 6X step-up mode.
For the contrast adjustm ent, it is performed through the use of an exter nal emitter follower circuit to adjust
VEE to generate –V1, this contrast control circuit is shown in Figure 9.

VDD_ROW Voltage Generator

VDD_ROW voltage generator is us ed to generate VDD_ROW , which is the power supply to the logic circuit
of a row driver.

+V1 Voltage Generator

+V1 voltage generator accompanies with an external MOS transistor to generate +V1 voltage, which is
required for the row driver. Figure 10 shows the accompanying external circuit for generating +V1 voltage.

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SSD1730

Rev 2.0
04/2002

SOLOMON

6. PINS ASSIGNMENT

The package of SSD1730 is 48 LQFP and Table 2 shows its pin assignment.

Pin 1

Figure 2 - Pinout Diagram

Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal

Name

1 -V1 13 -V3B 25 NC2 37 L0
2 C8N 14 C1NB 26 NC 3 38 L1
3 VDD_ROW 15 VSS 27 -V3 39 L2
4 C7N 16 C1PB 28 C2P 40 L3
5 VSS 17 VDD_PWR 29 VDD_PWR 41 VSS
6 VEE 18 C4N 30 C1P 42 LP
7 C6N 19 -V2 31 VSS 43 FR
8 VEM 20 C4P 32 C3N 44 XFR

9 C5N 21 -V3 33 V2 45 XSLP
10 HC 22 VSS 34 NC4 46 XTST
11 NC1 23 C1N 35 C3P 47 AB
12 C5P 24 C2N 36 VDD_PWR 48 XBB

Table 2 - Pin Assignment Table

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04/2002

SSD1730

4

7. PIN DESCRIPTION

Key:

I =Input
O =Output
I/O = Bi-Directional (Input/Output)
P = Power pin
NC = Dummy pin

Pin Name Type Pin# Description

VDD_PWR P 17, 29 &36 Power supply pin
VSS P 5, 15, 22, 31 & 41 Ground pin

Table 3 - Power Supply Pins

Pin Name Type Pin# Description

L0 to L3 I 37 to 40 These input pins are used to set the polarity

reversal interval ranging from 2P to 17P.

FR O 43 This is an output pin and the FR signal is

generated from the LCD polarity reverse signal
generator.

XFR O 44 This is an output pin and the XFR signal is also

generated from the LCD polarity reverse signal
generator. This signal is a rever se phase from FR
signal.

Table 4 - Pins for frame signal generator

Pin Name Type Pin# Description

LP I 42 This input pin is us ed to generate the charge pum p

clock and the polarity reverse signal FR and X FR.
A pulse signal with a period of 1P should be fed
into this pin.

XSLP I 45 This input pin is used to switch on or off the

display. When it is set to VSS level, the clock and
the operations of the voltage converter will be stop.
The display will be off. W hen it is set to VDD_PWR
level, the display will be on.

Table 5 - Pins for clock signal generator

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Pin Name Type Pin# Description

-V1 I/O 1 This is the row driver negative voltage level power
supply voltage terminal. The –V1 is an input signal
to the contrast adjustment circuit this is used to
adjust the display contrast. Besides, this is the
power supply to the +V1 voltage generator control
circuit.

Table 6 - Pins for –V1 discharge circuit

Pin Name Type Pin# Description

C1P

I/O 30 The positive-side connection terminal for a

capacitor C1 to generate -V3 output voltage. (Refer
to the application circuit)

C1N

I/O 23 The negative-side connection terminal for a

capacitor C1 to generate -V3 output voltage. (Refer
to the application circuit)

C2P I/O 28 The positive-side connection terminal for a

capacitor C2 to generate -V3 output voltage. (Refer
to the application circuit)

C2N I/O 24 The negative-side connection terminal for a

capacitor C2 to generate -V3 output voltage. (Refer
to the application circuit)

-V3 O 21, 27 This is -V3 output voltage, which is for the power
supply of segment driver.

C3P I/O 35 The positive-side connection terminal for a

capacitor C3 to generate V2 output voltage. (Refer
to the application circuit)

C3N I/O 32 The negative-side connection terminal for a

capacitor C3 to generate V2 output voltage. (Refer
to the application circuit)

V2 I/O 33 This is V2 output voltage which is for the power

supply of segment driver.

C4P I/O 20 The positive-side connection terminal for a

capacitor C4 to generate -V2 output voltage. (Refer
to the application circuit)

C4N I/O 18 The negative-side connection terminal for a

capacitor C4 to generate -V2 output voltage. (Refer
to the application circuit)

-V2 O 19 This is -V2 output voltage which is for the power
supply of segment driver.

Table 7 - Pins for column (segment) driver voltage generator

SOLOMON

Rev 2.0
04/2002

SSD1730

6

Pin Name Type Pin# Description

Pins for VDD_ROW voltage generator

C8N

I/O 2 The negative-side connection terminal for a

capacitor C11 to generate VDD_ROW output
voltage. (Refer to the application circuit)

VDD_ROW O 3 This is VDD_ROW output voltage which is the

power supply to the logic circuit part of row driver.

Pins for +V1 voltage generator

AB O 47 This is the clock output for the external n-channel

MOS transistor control in the +V1 voltage
generator circuit.

XBB O 48 This is the clock output for the external p-channel

MOS transistor control in the +V1 voltage
generator circuit.

C7N I/O 4 The negative-side connection terminal for a

capacitor C18 to generate +V1 output voltage.
(Refer to the application circuit)

Pins for row driver voltage conversion circuit

C1PB

I/O

16 The positive-side connection terminal for a

capacitor C10 and C11 to generate -V3B output
voltage. (Refer to the application circuit)

C1NB

I/O

14 The negative-side connection terminal for a

capacitor C10 to generate -V3B output voltage.
(Refer to the application circuit)

-V3B

HC

O
I

13 This is -V3B output voltage equipped as the middle

voltage level for generating VEE output voltage.

10 This pin is used to select 5X or 6X step-up mode.

When it is tied to VSS, 5X step-up mode will be
set. When it is tied to -V3B, 6X step-up mode will
be set.

C5P

I/O

12 The positive-side connection terminal for a

capacitor C8 and C9 to generate VEM output
voltage. (Refer to the application circuit)

C5N

I/O

9 The negative-side connection terminal for a

capacitor C8 to generate VEM output voltage.
(Refer to the application circuit)

VEM
C6N

O
I/O

8 This is VEM output voltage equipped as the middle

voltage level for generating VEE output voltage.

7 The negative-side connection terminal for a

capacitor C9 to generate VEE output voltage.
(Refer to the application circuit)

VEE O 6 This is VEE output voltage.

Table 8 - Pins for row (common) driver voltage generator

Pin Name Type Pin# Description

XTST I 46 This is a test pin. This pin must be tied to the

VDD_PWR level in normal application.

NC,1 NC2,
NC3, NC4

NC 11, 25, 26, 34 Dummy Pins. These pins must be left open &

unconnected in normal application.

Table 9 - Test circuit pins and Dummy pins

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SSD1730

Rev 2.0
04/2002

SOLOMON

8. DC CHARACTERISTICS

Maximum Ratings

Symbol

VDD_PWR

-V1
Vin
IDD
IV2
I

-V2

I

-V3

I

VEE

I

VDD_ROW

TA
T

STG

Table 10 - Maximum Ratings for DC characteristics (Voltage Referenced to VSS, TA=25°C)

Maximum ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to
the limits shown in the Electrical characteristics table.

This device contain circuitry to protect the inputs against damage due to high static voltages of electric fields;
however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum
rated voltages to this high impedanc e circuit. All dummy pins and NC pins m ust be left open & unconnected. Do
not connect or group dummy pins or NC pins together.

Parameter Value Unit

Supply voltage 3.7 V
Row driver negative supply voltage VEE–0.3 to 0.3 V
Input voltage -0.3 to VDD_PWR+3.0 V
Input current 10 mA
Output current at V2 6 mA
Output current at -V2 6 mA
Output current at -V3 5 mA
Output current at VEE 1 mA
Output current at VDD_ROW 0.1 mA
Operating Temperature -20 to +85
Storage Temperature Range -65 to +150

°C
°C

SOLOMON

Rev 2.0
04/2002

SSD1730

8

9. Electrical Characteristics

Symbol Parameter Test Condition Min Typ Max Unit

VDD_PWR

-V1

Istd

I

DP1

I

DP2

VEE

VDD_ROW

V2 Output voltage at V2 pin

-V2 Output voltage at -V2 pin

-V3 Output voltage at -V3 pin

VIH

V

IL

VOH

V

OL

Supply voltage range
Row driver negative

supply voltage Range
Standby Mode Supply
Current Drain at
VDD_PWR
Display Mode Supply
Current Drain at
VDD_PWR in 5X step-up
mode
Display Mode Supply
Current Drain at
VDD_PWR in 6X step-up
mode

Output voltage at VEE
pin

Output voltage at
VDD_ROW pin

Input High voltage at
pins: LP, XSLP, L0, L1,
L2, L3 and XTST

Input Low voltage at pins
: LP, XSLP, L0, L1, L2,
L3 and XTST
Output High Voltage at
pins : XBB, AB, FR and
XFR

Output Low Voltage at
pins : XBB, AB, FR and
XFR

(Absolute value referenced to VSS)

2.4

3.3

3.6

V

(Absolute value referenced to VSS) VEE+0.6 -- -V3 V
VDD_PWR=2.4V to 3.6V, Display off

(XSLP=VIL).

-- 2 5

µA

VDD_PWR=2.7V, 5X step-up, LP
period=69µs, LP width=1µs, Display on
(XSLP=V

), No loading

IH

-- 270 380

µA

VDD_PWR=2.7V, 6X step-up, LP

period=69µs, LP width=1µs, Display on
(XSLP=V

6X step-up, LP period=69µs, LP

width=1µs, Display on
(XSLP=V
VSS)

6X step-up, LP period=69µs, LP

width=1µs, Display on
(XSLP=V
V1)

6X step-up, LP period=69µs, LP

width=1µs, Display on
(XSLP=V

6X step-up, LP period=69µs, LP

width=1µs, Display on
(XSLP=V
VSS)

6X step-up, LP period=69µs, LP

width=1µs, Display on
(XSLP=V
VSS)

), No loading

IH

), Io=0.4mA (from

IH

), Io=0.02mA (to –

IH

), Io=2mA (to VSS)

IH

), Io=2mA (from

IH

), Io=1mA (from

IH

VDD_PWR

=2.7V

VDD_PWR

=2.4V

VDD_PWR

=2.7V

VDD_PWR

=2.4V

VDD_PWR

=2.7V

VDD_PWR

=2.4V

VDD_PWR

=2.7V

VDD_PWR

=2.4V

VDD_PWR

=2.7V

VDD_PWR

=2.4V

-- 350 480

-- -12.25 -- V

-- -10.85 -- V

-- -V1+2.7 -- V

-- -V1+2.4 -- V

-- 1.313 -- V

-- 1.16 -- V

-- -1.276 -- V

-- -1.134 -- V

-- -2.646 -- V

-- -2.352 -- V

µA

VDD_PWR = 2.4V - 3.6V

0.8*VDD_PWR

0

--

--

VDD_PWR

0.2*VDD_PWR

V

VDD_PWR = 2.4V - 3.6V, Iout=-20µA

VDD_PWR = 2.4V - 3.6V, Iout=-20µA

VDD_PWR-0.1

0

--

--

VDD_PWR

0.1

V

Table 11 - Electrical characteristics (Voltage Referenced to VSS, TA=25°C)

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04/2002

SOLOMON

10. AC CHARACTERISTICS

Input Timing Characteristics

Symbol Parameter Min Typ Max Unit

t

LP Period 50 70 125

LPC

t

LP Width 70 1000 *2000 ns

LPW

t

LP Rise Time -- -- 10 ns

LPr

t

LP Fall Time -- -- 10 ns

LPf

Table 12 - Input Timing Characteristics (Voltage Referenced to VSS, VDD_PWR = 2.4 to 3.6V, TA = 25°C)

Remark *: It is noted that the wider the positive LP pulse with, the higher the output impedance of the output

voltage. The chip can function with positive LP pulse width in excess of 2000ns, but high output
impedance will be found.

t

LPW

µs

LP

t

LPC

t

t

LP r

LPf

Figure 3 - Timing Characteristics for input pin LP

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SSD1730

10

Output Timing Characteristics

V

LP pulse width = 1000ns, -V1 = VEE + 0.6V, 6X step-up mode application

Symbol Parameter Min Typ Max Unit

t
t

t
t

t

XBBr

t

XBBf

t

OFFr

t

OFFf

t

C7Nr

t

C7Nf

FRr

FRf

ABr

Abf

FR/XFR Signal Rise Delay Time (with loading =
50pF)
FR/XFR Signal Fall Delay Time (with loading =
50pF)

AB Signal Rise Delay Time 230 -- 2000 ns
AB Signal Fall Delay Time 180 -- 1900 ns

XBB Signal Rise Delay Time 130 -- 1100 ns
XBB Signal Fall Delay Time 280 -- 3200 ns
Rising Edge Output Phase Differential Time 1000 -- 2400 ns
Falling Edge Output Phase Differential Time 1000 -- 2200 ns
C7N Signal Rising Edge Delay Time 270 -- 2400 ns
C7N Signal Falling Edge Delay Time 490 -- 3800 ns

Table 13 - Output Timing Characteristics

t

FRr

FR
XFR

330 -- 3300 ns
330 -- 3300 ns

t

FRf

LP

AB

XBB

C7N

11

SSD1730

VSS

t

XBB r

t

C7Nf

Rev 2.0
04/2002

t

OFFr

VL+1.0V

-V1+1.0

t

t

t

ABr

C7Nf

-V1 -V1

VL

VL

ABf

t

C7Nr

t

XBBf

t

OFFf

t

C7Nr

VSS-1.0V

Figure 4 - Output Timing Characteristics

VSS

SOLOMON

V

R

V

V

V

V

V

V

V

V

11. EXPLANATION OF FUNCTIONS

This SSD1730 is a power chip for oper ating four-line MLA LCD drivers. It consists of a CMOS charge pump-type
voltage generator which can produce all of the bias voltages for a four-line MLA driven. SSD1730 power chip can
be used as a voltage generator to a display system for m ed by column driver such as SSD1870 and row driver s uch
as SSD1881. In SSD1730, all output voltages are generated or referenc e from supply power VDD_PWR. The volt­age levels at 5X or 6X step-up mode can be calculated by the logical formulas that are summarized in Table 14.

VDD_PWR

VSS

External
components

+V1

DD_PW

-

-

DD_ROW

-

SSD1730
Power Chip

SS

EE

+V1

3

2
2

3

V2
VSS

-V2

-V3

SSD1870
Column Driver

1

VC

VDD_ROW

-V1

SSD1881
Row Driver

Figure 5 - Voltage levels relationship between power chip, column driver and row driver

5X Step-up Mode 6X Step-up Mode

Logical Formula

+V1=-(-V1)
=4 x (VDD_PWR-VSS) - γ

Voltage Level

(VDD_PWR=3.3V)

13.2 - γ

Logical Formula

+V1=-(-V1)
=5 x (VDD_PWR-VSS) - γ

Voltage Level

(VDD_PWR=3.3V)

16.5 - γ

V3=VDD_PWR-VSS 3.3 V3=VDD_PWR-VSS 3.3
V2=0.5 x (VDD_PWR-VSS) 1.65 V2=0.5 x (VDD_PWR-VSS) 1.65
VC=VSS 0.0 VC=VSS 0.0

-V2=-0.5 x (VDD_PWR-VSS) -1.65 -V2=-0.5 x (VDD_PWR-VSS) -1.65

-V3=-V3B=-(VDD_PWR-VSS) -3.3 -V3=-V3B=-(VDD_PWR-VSS) -3.3
VEM=-2 x (VDD_PWR-VSS) -6.6 VEM=-3 x (VDD_PWR-VSS) -9.9
VDD_ROW=-3 x (VDD_PWR­VSS) + γ

-9.9 + γ

VDD_ROW=-4 x (VDD_PWR­VSS) + γ

-13.2 + γ

-V1=-4 x (VDD_PWR-VSS) + γ -13.2 + γ -V1=-5 x (VDD_PWR-VSS) + γ -16.5 + γ
VEE=-4 x (VDD_PWR-VSS) -13.2 VEE=-5 x (VDD_PWR-VSS) -16.5

Table 14 - Logical formula for SSD1730 (VSS = 0.0V)

Where γ is a vari abl e and i t must greater than or equal to 0 (γ ≥ 0). I n practice, it represents contrast adjustment value.

SOLOMON

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SSD1730

12

LCD Polarity Reverse Signal Generator

This circuit generates the polarity reverse signals FR and XFR from the 1P period pulse signal LP. The polarity
reversal period ranging from 2P to 17P is c ontrolled by four pins L0, L1, L2 & L3. In suc h cas e, the upper and lower
screens can be driven in mutually opposite phases when a two-screen drive panel is used, the polarity of the FR
signal and the XFR signal are mutually opposite. The tim ing of the output trans itions is synchronized with the falling
edge of the LP signal. Figure 6 shows the timing diagram of LP, FR and XFR signals. Table 15 shows the
relationship between the number of LP (NumLP) during the frame interval and the settings of L0 to L3.

XSLP

LP

FR

XFR

1P P e riod

Num LP

NumL P

Figure 6 - Timing Characteristics of LP, FR and XFR

L0 L1 L2 L3 Time Number Of LP (NumLP)

0 0 0 0 17P LP Signal 17th pulse
1 0 0 0 2P LP Signal 2

nd

pulse
0 1 0 0 3P LP Signal 3rd pulse
1 1 0 0 4P LP Signal 4th pulse
0 0 1 0 5P LP Signal 5th pulse
1 0 1 0 6P LP Signal 6th pulse
0 1 1 0 7P LP Signal 7th pulse
1 1 1 0 8P LP Signal 8th pulse
0 0 0 1 9P LP Signal 9th pulse
1 0 0 1 10P LP Signal 10th pulse
0 1 0 1 11P LP Signal 11th pulse
1 1 0 1 12P LP Signal 12th pulse
0 0 1 1 13P LP Signal 13th pulse
1 0 1 1 14P LP Signal 14th pulse
0 1 1 1 15P LP Signal 15th pulse
1 1 1 1 16P LP Signal 16th pulse

Table 15 - Relationship between NLP an L0 to L3

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p

V

V

V

R

Clock Signal Generator

This circuit generates the c loc k for charge pump circ uit f r om the pulse signal LP. When the display off control signal
XSLP is set to VSS, the clock will stop and the voltage c onverter will halt. The signal clocks AB and XBB f or the
column driver voltage generator and the row driver voltage generator are also generated by this circuit.

Input Signal XSLP

Input Signal LP

Output Signal AB

ut Signal XBB

Out

Figure 7 - Timing diagram for LP, AB and XBB

Driver Voltage Generator

This circuit generates all voltage levels which are required to drive both the row driver and the column driver. The
voltage converter circuit compr ises a CMO S charge pum p-type DC/DC converter which is form ed by five individual
voltage generator circuits including 1) Colum n driver voltage generator, 2) Row driver voltage conversion circuit, 3)
VDD_ROW voltage gener ator circ uit, 4) +V1 voltage generator circuit and 5) External c ontrast c ontrol circuit. Figure
8 shows the relationship between these voltage generator c ircuits and Table 14 summarized all logical form ulas
which can be used to calculated these voltage levels. Besides, in order to generate these voltages, external
capacitors for the charge pump are necessary. Application circuit shows their connections

DD_PW

VSS

Row driver
voltage
conversion
circuit

Column driver

Row driver voltage generator

-V3B

VEM

DD_ROW voltage

generator circuit

Ext. contrast
control circuit

voltage

generator

+V1 voltage generator

circuit

3

V2
VC

-V2

-V3

VDD_ROW

+V1

VEE

-V1

Figure 8 - Voltage generator control circuit

SOLOMON

Rev 2.0
04/2002

SSD1730

14

Contrast Control Circuit

The display contrast level –V1 is controlled by an external contrast adjustment circuit. Figure 9 shows the typical
connection of contrast control circuit.

-V3B

510k

VL

-V1

VL

-V1

SSD1730A

2SA500k

VEE

Figure 9 - Typical connection of contrast control circuit

+V1 Voltage Generator

This circuit generates voltage level +V1 which is the positive power supply to row driver. Signal AB and XBB are the clock for
this generator circuit. Figure 10 shows the typical connection of the +V1 voltage generator.

3.3M

470pF

+V1

XBB

C7N

2SJ

1.0pF

1.0uF

VH

SSD1730A

AB

Figure 10 - Typical connection of +V1 voltage generator

15

SSD1730

Rev 2.0
04/2002

2SJ

SOLOMON

-V1 and +V1 Discharge Circuit

When XSLP is set to VSS level, the internal –V1 discharge circuit will be triggered and the residual charge at the
row driver negative voltage-side power supply voltage terminal –V1 will be discharged to the VSS level. However,
the residual charge at the row driver positive voltage-side power supply terminal +V1 can be discharged to the VSS
level through an external MOS transistor. Figure 11 shows the typical connection of the +V1 discharge circuit.

VH

+V1

XSLP

3.3M
2SK

2SK

SSD1730A

VSS

Figure 11 - Typical connection of +V1 discharge circuit

Power Up and Power Down Sequence

Proper power up sequence and power down sequence are recommended to protect the display system and to have
better performance.

Power Up Sequence:
Start – Turn on the logic system in the application and power up the SSD1730
Display off – Set Column and Row Driver DOFF# to “L”
Initialization – Send LP, YD, XSCL and Data
Stable – Wait for the power levels getting stable (around 80ms)
Display on – Set Column and Row Driver DOFF# to “H”

Power Down Sequence:
Display off – Set Column and Row Driver DOFF# to “L”
Sleep mode – Set power chip to sleep mode by setting XSLP to “L”
Discharge – Wait for the discharge of the display system (around 50ms)
Power down – Cut the power of the SSD1730
End – Turn off the logic system of the application

#

Depends on the system loading.

#

#

SOLOMON

Rev 2.0
04/2002

SSD1730

16

12. APPLICATION CIRCUIT (SSD1730 5X Step-Up Mode)

VDD=VDD_PWR

FR
XFR

C1P
C1N
C2P
C2N
C3P
C3N
C4P
C4N

C1=4.7uF

C2=4.7uF

C3=4.7uF

C4=4.7uF

VSS

VDD

VSS

L3
L2
L1
L0

XTST

FR

XFR

V3

LP

XSLP

LP

XSLP

V2

VSS

-V2

-V3

C5N
C5P

C6N
C1NB
C1PB

C8N

HC

-V3B
VEM

VDD_ROW

-V1

VEE

XBB

C7N

AB

C14=0.1uF

C15=1.0uF

C17=470pF

C18=1.0uF

C5=4.7uF
C6=4.7uF

C8=1.0uF
C9=1.0uF

C10=4.7uF
C11=0.1uF

C13=1.0uF

3.3M

C7=4.7uF

C12=4.7uF

510k

500k

2SJ

C19=1.0uF

2SK

2SK

2SA

C16=1.0uF

3.3M

V2
VC

-V2

-V3

VDD_ROW

-V1

+V1

2SK

Figure 12 - Application Circuit for SSD1730 5X step-up mode

Remark: HC is tied to –V3B for 6X Step-up Mode.
17

SSD1730

Rev 2.0
04/2002

SOLOMON

13. PACKAGE DIMENSIONS

9.00

7.00

Pin 1
Identifier

48

1.6max

12

1

13 24

0.50

0.22±0.05

36

25

7.00

9.00

0.05

±

1.4
min0.05

max0.15

0.25

3.5o

±

3.5

SOLOMON

48 LQFP

(Dimensi on in mm, do not scale this drawing)

Figure 13 - Package Dimensions

Rev 2.0
04/2002

1.00

±

0.6

0.15

SSD1730

18

Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability a rising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and
do vary in different applications. A ll operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
Solomon Systech does not convey any license under i ts patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon
Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design
or manufacture of the part.

19

SSD1730

Rev 2.0
04/2002

SOLOMON