Datasheet SP791CN, SP791CP, SP791EN, SP791EP Datasheet (Sipex Corporation)

Download

Page 1

SP791

Low P o wer Micropr ocessor Supervisory

with Battery Switch-Over

■ Precision 4.65V Voltage Monitoring

■ 200ms Power-OK/Reset Time Delay

■ Independent Watchdog Time-Preset or Adjustable

■ 75µA Maximum Operating Supply Current

■ 1.0µA Maximum Battery Backup Current

■ 0.1µA Maximum Battery Standby Current

■ Power Switching

250mA Output in Vcc Mode (0.6Ω) 25mA Output in Battery Mode (5Ω)

■ On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 6ns CE Gate Propagation Delay

■ Voltage Monitor for Power-Fail or Low Battery

■ Backup-Battery Monitor

■ RESET Valid to Vcc=1V

■ Pin Compatible Upgrade to MAX791

DESCRIPTION

The SP791 is a microprocessor (µP) supervisory circuit that integrates a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in µP and digital systems. The SP791 offers complete µP monitoring and watchdog functions. The SP791 is ideal for a low-cost battery management solution and is well suited for portable, battery-powered applications with its supply current of 40µA. The 6ns chip-enable propagation delay, the 25mA current output in battery-backup mode, and the 250mA current output in standard operation also makes the SP791 suitable for larger scale, high-performance equipment.

SWT

WDI

PFI

SP791

OUT

+ _

1.25V

RESET

GENERATION

TIMEBASE FOR

RESET AND WATCHDOG

WATCHDOG

TRANSITION

DETECTOR

PFO

RESET

WATCHDOG TIMER

WDO

WDPO

Vcc

BATT

4.65V

GND

+ _

CHIP-ENABLE

OUTPUT

CONTROL

150mV

LOWLINE

BATT ON

OUT

CE OUT

Figure 1. Block Diagram

Page 2

ABSOLUTE MAXIMUM RATINGS

Input Voltage (with respect to GND)

VCC..................................................-0.3V to +6V

VBATT.................................. ............-0.3V to +6V

All Other Inputs ................-0.3V to (VOUT + 0.3V)

Input Current

VCC Peak..................................................... 1.0A

VCC Continuous .......................................250mA

VBATT Peak ..............................................250mA

VBATT Continuous.......................................25mA

GND, BATT ON .........................................100mA

All Other Outputs ........................................25mA

Continuous Power Dissipation (TA = + 70oC)

Plastic DIP (derate 10.53mW/oC above +70oC) 842mW Narrow SO (derate 8.70mW/oC above+70oC) 696mW

ESD Rating........................................................4KV

Stresses beyond these listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Operating Temperature Ranges

SP791C ..............................0oC to +70oC

SP791E ...........................-40oC to +85oC

Storage T emperature Range...........-65oC to +160oC

Lead Temperature (soldering,10sec)..........+300oC

ELECTRICAL CHARACTERISTICS

(Vcc = 4.75V to 5.5V, VBATT = 2.8V, TA = T

PARAMETER MIN TYP MAX UNITS CONDITIONS

Operating Voltage Range 0 5.5 V VCC, V

(Note 1)

BATT

in Normal VCC- 0.3 VCC - 0.15 V VCC = 4.5V, I

OUT

Operating Mode VCC- 0.2 VCC - 0.09 V

to T

MIN

unless otherwise noted, typicals specified at 25oC)

MAX

VCC - 0.05 VCC - 0.015 VCC = 4.5V, I

=3.0V; V

OUT

BATT

= 25mA

= 250mA

= 2.8V, I

OUT

= 100mA

VCC-to-V

OUT

BATT

On Resistance Ω

OUT

in Battery Backup Mode V

-to-V

On Resistance 7 25 Ω V

OUT

0.6 1.2 V

0.9 2.0 V

- 0.3 V

BATT

- 0.25 V V

BATT

- 0.15 V

BATT

515 V

10 30 V

BATT BATT BATT

=4.5V;

=3.0V;

=4.5V, I =2.8V, I =2.0V, I

=4.5V =2.8V =2.0V

OUT OUT OUT

=20mA =10mA =5mA

Supply Current in Normal Operating Mode (Excludes IOUT)4075µAV

Supply Current in Battery Backup 0.001 1 µA V

> V

– 1V

BATT

< V

– 1.2V ; V

BATT

= 2.8V

Mode (Excludes IOUT) (Note 2) VBATT Standby Current -0.1 0.02 µA V

(Note 3) Battery-Switchover Threshold V

+0.03 Power up

BATT

-0.03 V Power down

BATT

+ 0.2V < V

Battery-Switch over Hysteresis 60 mV Peak to Peak Low-Battery Detector Threshold 2 V

Page 3

ELECTRICAL CHARACTERISTICS (continued)

(Vcc = 4.75V to 5.5V, VBATT = 2.8V, TA = T

PARAMETER MIN TYP MAX UNITS CONDITIONS

MIN

to T

unless otherwise noted, typicals specified at 25oC)

MAX

BATT ON Output 0.1 0.4 V I Low Voltage 0.7 1.5 I

SINK SINK

= 3.2mA = 25mA

BATT ON Output 60 mA Sink Current Short Circuit Current 1 15 100 µA Source Current

RESET, LOW-LINE AND WATCHDOG TIMER

RESET Threshold Voltage 4.50 4.65 4.75 V RESET Threshold Hysteresis 15 mV LOWLINE-to-RESET 150 mV

Threshold Voltage VCC-to-RESET Delay 100 µs Power down VCC-to-LOWLINE Delay 80 µs Power down RESET Active Timeout Period 140 200 280 ms Power up Watchdog Timeout Period 1.0 1.6 2.25 sec SWT connected to V

OUT

Minimum Watchdog 10 ms 4.7nF capacitor connected from Timeout Period SWT to GND

Minimum Watchdog Input 100 ns V Pulse Width

= 0.8V, VIH = 0.75 X V

WDPO Pulse Width 1 ms WDPO-to-WDO Delay 70 ns RESET Output Voltage 0.004 0.3 V I

0.1 0.4 I

3.5 I

=50µA,VCC=1.0V,VCC ➘

SINK

= 3.2 mA, VCC = 4.25V

SINK

= 1.6mA, VCC = 5V

SOURCE

RESET Output Short-Circuit Current 7 20 mA Output source current

LOWLINE Output Voltage 0.4 V I

3.5 I

= 3.2mA, VCC = 4.25V

SINK

= 1µA, VCC = 5V

SOURCE

LOWLINE Output 15 100 µA Output source current Short-Circuit Current

WDO Output Voltage 0.4 V I

3.5 I

= 3.2mA

SINK

= 500µA, VCC = 5V

SOURCE

WDO Output Short-Circuit 3 10 mA Output source currrent Current

WDPO Output Voltage 0.4 V I

3.5 I

SINK

SOURCE

= 3.2mA

= 1mA

WDPO Output Short-Circuit 7 20 mA Output source current Current

Page 4

ELECTRICAL CHARACTERISTICS (continued)

(Vcc = 4.75V to 5.5V, VBATT = 2.8V, TA = T

PARAMETER MIN TYP MAX UNITS CONDITIONS

MIN

to T

unless otherwise noted, typicals specified at 25oC)

MAX

WDI Threshold Voltage 0.75 X V

(Note 4) 0.8 V

WDI Input Current -50 -10 µA WDI = 0V

20 50 WDI = V

OUT

POWER FAIL COMPARATOR

PFI Input Threshold 1.20 1.25 1.30 V V

= 5V

PFI Leakage Current +0.01 +25 nA PFO Output Voltage 0.4 V I

3.5 I

= 3.2mA

SINK SOURCE

= 1µA, VCC = 5V

PFO Short-Circuit Current 60 mA Output sink current

1 15 100 µA Output source current

PFI-to-PFO Delay 15 µs V

55 V

= 15mV

CHIP-ENABLE GATING

CE IN Leakage Current +0.005 +1 µA Disabled mode CE IN-to-CE OUT Resistance 65 150 Ω Enabled mode

(Note 5) CE OUT Short-Circuit Current 0.1 0.75 2.0 mA Disabled mode, CE OUT = 0V

(Reset Active) CE IN-to-CE OUT Propagation 6 10 ns 50Ω source impedance driver,

Delay (Note 6) C CE OUT Output Voltage High 3.5 V V

(Reset Active) 2.7 V

LOAD

= 5V, I

= 0V, V

= 50pF

OUT

BATT

= 100µA

= 2.8V, I

OUT

RESET-to-CE OUT Delay 15 µs Power down

MANUAL RESET INPUT

MR Minimum Pulse Width 25 15 µs MR-to-RESET 7 µs

Propagation Delay MR Threshold 1.25 V V

= 5V

MR Pull-Up Current 23 250 µA MR = 0V

= 1µA

Note 1: Either VCC or V greater than 2.0V.

Note 2: The supply current drawn by the SP791 from the battery (excluding I

- 1V) < VCC < V period as VCC falls through this region.

OUT

BATT

can go to 0V, if the other is

BATT

) typically goes to 10µA when (V

. In most applications, this is a brief

BATT

Note 5: The chip-enable resistance is tested with VCC =

4.75V :: V

CE IN

= V

CE OUT

=VCC/2.

Note 6: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE

OUT

Note 3: "+" = battery-discharging current, "-" = battery-charging current.

Note 4: WDI is internally connected to a voltage divider between V

1.6V (typ), disabling the watchdog function.

and GND. If unconnected, WDI is driven to

OUT

Page 5

PINOUT

TOP VIEW

to select another watchdog-timeout period. W atchdog-timeout period = 2.1 x (capacitor value in nF) ms.

BATT

OUT

Vcc

GND

BATT ON

PFO

PFI

SWT

1 2 3 4

Corporation

5 6 7 8

DIP/SO

16 15 14 13 12

WDPO RESET WDO

OUT

WDI LOWLINE

PIN ASSIGNMENTS

Pin 1 — V

— Backup-Battery Input. Connect

BATT

to external battery or capacitor and charging circuit.

Pin 2 —V

— Output Supply Voltage. V

OUT

con-

nects to VCC when VCC is greater than V

BATT

and VCC is above the reset threshold. When VCC falls below V reset threshold, V nect a 0.1µF capacitor from V

and VCC is below the

BATT

connects to V

OUT

to GND.

OUT

BATT

. Con-

Pin 3 — VCC — Input Supply Voltage —

+5V input Pin 4 — GND — Ground reference for all signals Pin 5 — BATT ON — Battery On Output. Goes

high when V

when V

switches to V

OUT

switches to VCC. Connect the base

OUT

. Goes low

BATT

of a PNP through a current-limiting resistor

to BATT ON for V

current requirements

OUT

greater than 250mA. Pin 6 — PFO — Power-Fail Output. This is the

output of the power-fail comparator. PFO

goes low when PFI is less than1.25V . This is

an uncommitted comparator, and has no ef-

fect on any other internal circuitry. Pin 7 — PFI — Power-Fail Input. This is the

noninverting input to the power-fail compara-

tor. When PFI is less than 1.25V, PFO goes

low. Connect PFI to GND or V

when not

OUT

used. Pin 8 — SWT — Set Watchdog-Timeout Input.

Connect this input to V

to select the de-

OUT

fault 1.6 sec watchdog timeout period. Con-

nect a capacitor between this input and GND

Pin 9 — MR — Manual-Reset Input. This input

can be tied to an external momentary pushbutton switch, or to a logic gate output. RESET remains low as long as MR is held low and for 200ms after MR returns high.

Pin 10 — LOWLINE — LOWLINE Output goes

low when VCC falls to 150mV above the reset threshold. The output can be used to generate an NMI (nonmaskable interrupt) if the unregulated supply is inaccessible.

Pin 11 — WDI — W atchdog Input. WDI is a three-

level input. If WDI remains either high or low for longer than the watchdog timeout period, WDO goes low. WDO remains low until the next transition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between V

and GND, which

OUT

sets it to mid-supply when left unconnected.

Pin 12 — CE OUT — Chip-Enable Output.

CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE

IN is low when reset is asserted, CE OUT will

stay low for 15us or until CE IN goes high, whichever occurs first.

Pin 13 — CE IN — Chip-Enable Input. The Input

to chip-enable gating circuit. Connect to GND or V

if not used.

OUT

Pin 14 — WDO — W atchdog Output. WDO goes

low if WDI remains either high or low longer than the watchdog timeout period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. WDO is also high when RESET is asserted.

Pin 15 — RESET — RESET Output goes low

whenever VCC falls below the reset threshold. RESET will remain low for 200ms after VCC crosses the reset threshold on power-up.

Pin 16 — WDPO — Watchdog-Pulse Output.

Upon the absence of a transition at WDI, WDPO will pulse low for a minimum of 1ms. WDPO precedes WDO by 70ns.

Page 6

TYPICAL CHARACTERISTICS (25

C, unless otherwise noted)

VCC Supply Current vs.

Temperature (Normal Mode)

57 53 49 45 41

Current (µA)

33 29 25

-60 -30 0 30 60 90 120 150

Temperature Deg. C

to V

BATT

Resistance vs. Temperature

VCC=0V V

Resistance (ohms)

-60 -30 0 30 60 90 120 150

Temperature Deg. C

OUT

BATT

VCC=5V

BATT

=2V

BATT

=2.8V

=4.5V

Battery Supply Current vs.

Temperature (Backup Mode)

2.9

VCC=0V

2.4

=2.8V

BATT

1.9

1.4

Current (µA)

0.9

BATT

0.4

-0.1

-60

-40 -20 0

Resistance vs. Temperature

0.9

0.8

0.7

0.6

0.5

Resistance (ohms)

0.4

0.3

-60 -30 0 30 6 0 90 120 150

20 406080

Temperature Deg. C

VCC to V

OUT

VCC=5V

Temperature Deg. C

BATT

100120

=0V

140

PFI Threshold (V)

Chip Enable On

Resistance vs. Temperature

120 110 100

90 80 70 60

Resistance (ohms)

50 40

-60 -30 0 30 60 90 120 150 180

VCC=4.75V V

BATT

CE IN=V

Temperature Deg. C

PFI Threshold

1.256

1.254

1.252

1.250

1.248

1.246

vs. Temperature

VCC=5V V

BATT

NO LOAD ON PFO

-60 -30 0 30 6 0 90 120 150

Temperature Deg. C

=2.8V

Reset Threshold

4.70

4.69

4.68

4.67

4.66

4.65

4.64

4.63

Reset Threshold (V)

4.62

4.61

4.60

vs. Temperature

=0V

BATT

Power Down

-60 -30 0 30 60 90 120 150

Temperature Deg. C

Reset Output Resistance

vs. Temperature

600 500 400 300 200

Resistance (ohms)

100

-60 -30 0 30 60 90 120 150

VCC=5V,V

Soucing Current

VCC=0V,V

Sink Current

Temperature Deg. C

BATT

=2.8V

212 210 208 206 204

Reset Delay (mS)

202 200

-60 -30 0 30 60 90 120 150

Reset Delay

vs. Temperature

VCC=0V to 5V Step,

=2.8V

BATT

Temperature Deg. C

Page 7

TYPICAL CHARACTERISTICS (25

C, unless otherwise noted)

Maximum Reset Comparator Overdrive

100

Maximum Transient Duration (uS)

Without Causing a Reset

0.1µF Capacitor V

OUT

Above Line

Reset Generated

Below Line

No Reset Generated

10 100 1000 10000

Reset Threshold Voltage - VCC (mV)

Chip-Enable Propagation Delay

vs. CE OUT Load Capacitance

VCC=5V

50Ω Driver

Propagation Delay (NS)

0 50 100 150 200 250 300

Cload (pF)

VBATT to VOUT vs.

=4.5V =0V

Output Current

IOUT (mA)

1000

BATT

Slope=5Ω

100

Voltage Drop(mV)

1 10 100

to GND

Watchdog Timeout

vs. Timing Capacitor

250

VCC=5V

200

150

100

Watchdog Tiimeout (mS)

1000

100

Voltage Drop(mV)

IE+2 IE+1 IE+0

IE-1 IE-2 IE-3 IE-4 IE-5

Current(µA) Log Scale

IE-6

BATT

IE-7

IE-8

=2.8V

BATT

0 10 20 30 40 50 60 70 80 90 100

Timing Capacitor (nF)

VCC to V

Output Current

OUT

vs.

VCC=4.5V

=0V

BATT

Slope=0.6Ω

1 10 100 1000

IOUT (mA)

Battery Current vs. VCC Voltage

.0000 5.000

VCC (0.5V/div)

=2.8V

BATT

Page 8

OTHER SYSTEM RESET SOURCES

UNREGULATED SUPPLY

Typical Operating Circuit

+5V

UNREGULATED

SUPPLY FAILURE

0.1µF

0.47F

BATT

PFI

PFO

BATT ON

Corporation

LOWLINE

GND

SWT

OUT

WDI

RESET

WDO

ADDRESS DECODE

0.1µF

AO-A15 µP

I/O NMI RESET

INT

CMOS RAM

MANUAL RESET

OTHER RESET SOURCES

Corporation

RESET

25µs MIN

µs

TYP

OUT

Figure 2. Manual-Reset Timing Diagram

FEA TURES

The SP791 is a microprocessor (µP) supervisory circuit that monitors the power supplied to digital circuits such as microprocessors, microcontrollers, or memory. The SP791 is an ideal solution for portable, battery-powered equipment that require power supply monitoring. The SP791 watchdog functions will continuously oversee the operational status of a system. Implementing the SP791 will reduce the number of components and overall complexity in a design that requires power supply monitoring circuitry. The operational features and benefits of the SP791 are described in more detail below.

µs

TYP

DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS

Figure 3. Diode "OR" connections allow multiple reset sources to connect to MR.

2) Manual-Reset input ➡ Manually resets

RESET output

3) Power Fail Comparator ➡ Provides for power-

fail warning and low-battery detection, or monitors another power supply .

4) Watchdog function ➡ Monitors µP activity

where the watchdog output goes to a logic LOW state if the watchdog input is not toggled for a period greater than the timeout period.

5) Internal switch ➡ Switches over from VCC to

if the VCC falls below the reset thresh-

BATT

old and below V

BATT

MANUAL RESET INPUT

THEORY OF OPERATION

The SP791 is a complete µP supervisor IC and provides the following main functions:

1) µP reset ➡ RESET output is asserted during

power fluctuations such as power-up, powerdown, and brown out conditions, and is guaranteed to be in the correct state for VCC down to 1V.

Many microprocessor or microcontroller products include manual-reset capability, allowing the operator or test technician to initiate a reset. The Manual Reset Input (MR) can be connected directly to a switch, without an external pull-up resistor. It connects to a 1.25V comparator, and has an internal pull-up to VOUT as shown in Fig- ure 1. The propagation delay from asserting MR to RESET being asserted is 7us typical. Pulsing

Page 9

RESET

TO µP RESET

WDI

1.6sec

100ns MIN

Corporation

Figure 4. Adding an external pull-down resistor ensures RESET is valid with VCC down to GND.

+5V

Vcc

BATT

3.6V

LOWLINE

GND

10k

4.7k

Ω

REACTIVATE

+5V

1µF

Corporation

RESET

WDPO

OUT

WDI

WDO

15 11

WDPO

WDO

70ns

Figure 5. WDI, WDO and WDPO Timing Diagram (VCC mode).

0.1µF

1/6 74HC04

Vcc

CLOCK

CD4013

SET

RESET Vss

654

∗

SETS Q HIGH ON POWER-UP

P POWER

RESET

I/O

NMI INTERRUPT

TWO CONSECUTIVE WATCHDOG FAULT INDICATIONS

Figure 6. Two consecutive watchdog faults latch the system in reset.

MR low for a minimum of 25µs resets all the internal counters, sets the Watchdog Output (WDO) and Watchdog-Pulse Output (WDPO) high, and sets the Set W atchdog-Timeout (SWT) input to VOUT if it is not already connected to VOUT (for Internal timeouts). It also, disables the Chip-Enable Output (CE OUT) forcing it to a high state. The RESET output remains at a logic low as long as MR is held low, and the reset-timeout period begins after MR returns high, Figure 2.

Use this input as either a digital-logic input or a second low-line comparator. Normal TTL/ CMOS levels can be wire-OR connected via pull-down diodes, Figur e 3, and open-drain/collector outputs can be wire-ORed directly.

1.6mA at VOUT – 0.5V. When no backup battery is used, RESET output is valid down to VCC = 1V, and an external 10kΩ pull-down resistor on RESET ensures that RESET will be valid with VCC down to GND as shown on Figure 4. As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the rDS(ON) and the saturation voltage. The 10kΩ pull-down resistor ensures the parallel combination of switch and external resistor is 10kΩ and the output saturation voltage is below 0.4V, while sinking 40µA. When using a 10kΩ external pull-down resistor, the high state for the RESET output with Vcc =

4.75V is 4.5V typical. For battery voltages greater than or equal to 2V, RESET remains valid for VCC between 0V and 5.5V. RESET will

RESET OUTPUT

The SP791's RESET output ensures that the µP powers up in a known state, and prevents codeexecution errors during power-down or brownout conditions.

The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, RESET sources

be asserted during the following conditions:

1) VCC < 4.65V (typ)

2) MR < 1.25V (typ)

3) RESET = logic "0" ; for 200 ms (typ) after Vcc rises above 4.65V or after MR has exceeded

1.25V. The SP791 battery-switchover comparator does

not affect RESET assertion.

Page 10

WATCHDOG FUNCTION

The watchdog monitors µP activity via the Watchdog Input (WDI). If the µP becomes inactive over a period of time, WDO and WDPO are asserted.

To use the watchdog functon, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6sec nominal), WDPO and WDO are asserted, indicating a software fault or idle condition.

WATCHDOG INPUT

A change of logic state (minimum 100ns duration) at WDI during the watchdog period will reset the watchdog timer. The watchdog default timeout is 1.6sec. To select an alternative timeout period, connect an external capacitor from SWT to GND.

To disable the watchdog function, leave WDI floating. An internal impedance network (100kΩ equivalent at WDI) biases WDI to approximately

1.6V. Internal comparators detect this level and disable the watchdog timer. When Vcc is below the reset threshold, the watchdog function is disabled and WDI is disconnected from its internal network, thus becoming high impedance.

WATCHDOG OUTPUT

WDO remains high if there is activity (transition or pulse) at WDI during the watchdogtimeout period. The watchdog function is disabled and WDO is a logic high when VCC is less than the reset threshold, or when WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog-timeout period, WDO goes low 70ns after the falling edge of WDPO and remains low until the next transition at WDI as shown on Figure 5. A flip- flop can force the system into a hardware shutdown if there are two successive watchdog faults, shown on Figure 6. WDO has a 2 x TTL output characteristic.

WATCHDOG-PULSE OUTPUT

As described in the preceding section, WDPO can be used as the clock input to an external D flip-flop. Upon the absence of a watchdog edge or pulse at WDI at the end of a watchdog-timeout period, WDPO will pulse low for 1ms. The fall-

ing edge of WDPO precedes WDO by 70ns. Since WDO is high when WDPO goes low, the Q output of the flip-flop remains high as WDO goes low (Figure 6). If the watchdog timer is not reset by a transition at WDI, WDO remains low and WDPO clocks a logic low to the Q output, causing the SP791 to latch in reset. If the watchdog timer is reset by a transition at WDI, WDO goes high and the flip-flop's Q output remains high. Thus, a system shutdown is only caused by two successive watchdog faults.

The internal pull-up resistors associated with WDO and WDPO connect to VOUT. Therefore, do not connect these outputs directly to CMOS logic that is powered from VCC since, in the absence of VCC (i.e., battery mode), excessive current will flow from WDO or WDPO through the protection diode(s) of the CMOS-logic inputs to ground.

SELECTING AN ALTERNATIVE WA TCHDOG TIMEOUT PERIOD

SWT input controls the watchdog-timeout period. Connecting SWT to VOUT selects the internal 1.6sec watchdog-timeout period. Select an alternative timeout period by connecting a capacitor between SWT and GND. Do not leave SWT floating, and do not connect it to ground. The following formula determines the watchdog-timeout period:

Watchdog Timeout Period = 2.1 x

(capacitor value in nF) ms

This formula is valid for capacitance values between 4.7 nF and 100nF (see the Watchdog Timeout vs. T iming Capacitor graph in the T ypi-

cal Operating Characteristics).

CHIP-ENABLE SIGNAL GATING

The SP791 provides internal gating of chip-enable (CE) signals to prevent erroneous data from corrupting the CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The SP791 uses a series transmission gate from CE IN to CE OUT.

Page 11

Vcc

RESET

THRESHOLD

OUT

15µs

100

RESET

Figure 7. Reset and Chip-Enable Timing

The 10ns maximum CE propagation from CE

IN to CE OUT enables the SP791 to be used with

most µPs.

CHIP-ENABLE INPUT

CE IN is high impedance (disabled mode) while RESET is asserted.

During a power-down sequence where VCC falls below 4.65V, CE IN assumes a high impedance state when the voltage at CE IN goes high or 15µs after RESET is asserted, whichever occurs first, (Figure 7).

During a power-up sequence, CE IN remains high impedance until RESET is deasserted.

In the high-impedance mode, the leakage currents into this input are less than 1µA over temperature. In the low-impedance mode, the impedance of CE IN appears as a 65Ω resistor in series with the load at CE OUT.

The propagation delay through the CE transmission gate depends on both the source impedance of the drive to CE IN and the capacitive loading on CE OUT (see the ChipEnable Propagation Delay vs. CE OUT Load

100

Capacitance graph in the Typical Operating Characteristics). The CE propagation delay is

defined from the 50% point on CE IN to the 50% point on CE OUT using a 50Ω driver with 50pF load capacitance as in Figure 8. For minimum propagation delay, minimize the capacitive load at CE OUT and use a low output-impedance driver.

CHIP-ENABLE OUTPUT

In the enabled mode, the impedance of CE OUT is equivalent to 65Ω in series with the source driving CE IN. In the disabled mode, the 65Ω transmission gate is off and CE OUT is actively pulled to VOUT. This source turns off when the transmission gate is enabled.

+5V

Vcc

Corporation

OUT

Ω

Driver

GND

50pF C

LOAD

Figure 8. CE Propagation Delay Test Circuit

Page 12

FROM REGULATED SUPPLY

0.1

Corporation

OUT

BATT

Vcc

0.1

3.0V

P POWER

POWER TO CMOS RAM

UNREGULATED SUPPLY

b.)

a.)

VOLTAGE REGULATOR

0.1

RESET

10 11

WDI

GND

Corporation

OUT

BATT

RESET

WDI

6 11

Vcc

PFI

GND

0.1

3.0V

RESET NMILOWLINE I/O LINE

P POWER

POWER TO CMOS RAM

RESET NMIPFO I/O LINE

Figure 9. a) If the unregulated supply is inaccessible, LOWLINE generates the NMI for the µP. b) Use PFO to generate the µP NMI if the unregulated supply is accessible.

LOWLINE OUTPUT

The low-line comparator monitors VCC with a typical threshold voltage 150mV above the reset threshold and has 15mV of hysteresis. LOWLINE typically sinks 3.2mA at 0.1V. For normal operation (Vcc above the LOWLINE threshold), LOWLINE is pulled to VOUT. If ac-

POWER-FAIL INPUT

The Power-Fail Input (PFI) has a guaranteed input leakage of +/-25nA max over temperature. The typical comparator delay is 15µs from VIL to VOL (power failing), and 55µs from VIH to VOH (power being restored). Connect PFI to ground if not used.

cess to the unregulated supply is unavailable, use LOWLINE to provide a nonmaskable interrupt (NMI) to the µP as shown in Figure 9a.

POWER-FAIL OUTPUT

The Power-Fail Output (PFO) goes low when PFI falls below 1.25V. It sinks 3.2mA with a

POWER-FAIL COMPARATOR

The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the SP791. Common uses include monitoring supplies other than 5V (see the Typical Operating Circuit and the Monitoring a Nega-

saturation voltage of 0.1V. With PFI above

1.25V, PFO is actively pulled to VOUT. Connecting PFI through a voltage divider to an unregulated supply allows PFO to generate an NMI as the unregulated power begins to fall (see

Figure 9b).

tive Voltage section) and early power-fail de-

tection when the unregulated power is easily accessible as shown in Figure 9b.

Page 13

INPUT/OUTPUT STATES IN BATTERY-BACKUP MODE

PIN NAME STATUS

1VBATT Supply current is 1µA maximum

2VOUT VOUT is connected to VBATT

3VCC Battery-switchover comparator

4 GND GND-0V reference for all signals. 5 BATT ON Logic high. The open-circuit output is

6 PFO The power-fail comparator is disabled

7 PFI The power-fail comparator is disabled 8 SWT SWT is Ignored.

9 MR MR is ignored. 10 LOWLINE Logic low. 11 WDI WDI is ignored, and goes high

12 CE OUT Logic high. The open-circuit output

13 CE IN High Impedance. 14 WDO Logic high. The open-circuit output

15 RESET Logic low. 16 WDPO Logic high. The open-circuit output

Table 1. Input/Output states in Battery-Backup mode

To enter the Battery-Backup mode, VCC must be less than the Reset threshold and less than V

When VCC < V

through an Internal PMOS switch.

monitors VCC for active switchover. VCC is disconnected from V

equal to VOUT.

PFO is forced low.

impedance.

voltage is equal to VOUT.

BATT

-1.2V

OUT

BATTERY-BACKUP MODE

The SP791 requires two conditions to switch to battery-backup mode: 1) VCC must be below the reset threshold; 2) VCC must be below VBATT. T able 1 lists the status of the inputs and outputs in battery-backup mode.

BATTERY ON OUTPUT

The Battery On Output (BATT ON) indicates the status of the internal VCC/battery-switchover comparator, which controls the internal VCC and VBA TT switches. For VCC greater than VBATT (ignoring the small hysteresis effect), BATT ON is a logic low. For VCC less than VBATT, BA TT ON is a logic high. Use BATT ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications (see Typical Operating Circuit).

BATT

Vcc

Corporation

Figure 10. VCC and VBATT-to-VOUT Switch

0.1µF

OUT

INPUT SUPPLY VOLTAGE

The Input Supply Voltage (VCC) should be a regulated +5V source. VCC connects to VOUT via a parallel diode and a large PMOS switch (Figure 10). The switch carries the entire current load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. The maximum continuous current is 250mA, but power-on transients may reach a maximum of 1A.

BACKUP-BATTERY INPUT

The Backup-Battery Input (VBATT) is similar to VCC, except the PMOS switch and parallel diode are much smaller. Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than 1µA over temperature and supply voltage.

OUTPUT SUPPLY VOLTAGE

The Output Supply Voltage (VOUT) supplies all the current to the external system and internal circuitry. All open-circuit outputs will, for example, assume the VOUT voltage in their high states rather than the VCC voltage. At the maximum source current of 250mA, VOUT will typically be 200mV below VCC. VOUT should be decoupled with 0.1µF capacitor.

Page 14

RESET THRESHOLD

Vcc

RESET

OUT

200ms TYP

SECOND CE PULSE ABSENT WHEN V

BATT

< 2V

+5V

1N4148

0.47F

Vcc

BATT

OUT

(

Corporation

GND

Figure 11. Backup-Battery Monitor Timing Diagram

LOW-BATTERY MONITOR

The SP791 low-battery voltage function moni- tors VBATT. Low-battery detection of 2.0V ±0.15V is monitored only during the resettimeout period (200ms) that occurs either after a normal power-up sequence or after the MR reset input has been returned to its high state. If the battery voltage is below 2.0V, the second CE pulse is inhibited after reset timeout. If the battery voltage is above 2.0V, all CE pulses are allowed through the CE gate after the reset timeout period. To use this function, after the 200ms reset delay, write 00 (HEX) to a location using the first CE pulse, and write FF (HEX) to the same location using the second CE pulse following RESET going inactive on power-up. The contents of the memory then indicates a good battery (FF) or a low battery (00), Figure 11.

TYPICAL APPLICA TIONS

The SP791 is not short-circuit protected. Shorting VOUT to ground, other than power-up transients such as charging a decoupling capacitor, may destroy the device. All open-circuit outputs swing between VOUT and GND rather than VCC and GND. If long leads connect to the chip inputs, ensure that these lines are free from ringing and other conditions that would forward bias the chip's protection diodes.

Figure 12. High Capacity Capacitor on VBATT

There are three distinct modes of operation:

1) Normal operating mode with all circuitry powered up from VCC. Typical supply current from VCC is 40µA, while only leakage currents flow from the battery.

2) Battery-backup mode where VCC is typically within 0.7V below VBATT. All circuitry is powered up from VBATT, and the supply current is typically less than 40µA.

3) Battery-backup mode where VCC is less than VBATT by at least 0.7V. VBATT supply current is less than 1µA.

USING HIGH CAPACITY CAPACITOR WITH THE SP791

VBATT has the same operating voltage range as VCC, and the battery-switchover threshold voltages are typically +30mV centered at VBATT, allowing use of a capacitor and a simple charging circuit as a backup source (see Figure 12) .

If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC.

™ - REGISTERED TRADEMARK OF BAKNOR INDUSTRIES

Page 15

OUT

MAXIMUM Rp VALUE DEPENDS ON THE NUMBER OF RAM DEVICES. MINIMUM Rp VALUE IS 1KΩ

OUT

Corporation

GND

Figure 13. Alternate CE Gating

ACTIVE-HIGH CE LINES FROM LOGIC

VIN

RAM 1

RAM 2

RAM 3

RAM 4

PFO

+5V

TRIP

= 1.25

VH = 1.25

C1*

R2 II R3

(

R1 + R2 II R3

R1 + R2

(

+5V

Vcc

PFI

Corporation

PFO

GND

* OPTIONAL FOR ADDITIONAL

NOISE REJECTION

TRIP

)

VL - 1.25 5 - 1.25 1.25

)

R1 R3 R2

Figure 14. Adding Hysteresis to the Power-Fail Comparator

Leakage current through the capacitor charging diode and the SP791 internal power diode eventually discharges the capacitor to VCC. Also, if VCC and VBATT start from 0.5V above the reset threshold and power is lost at VCC, the capacitor on VBATT discharges through VCC until VBATT reaches the reset threshold; the SP791 then switches to battery-backup mode.

USING SEPARATE POWER SUPPLIES FOR VBATT AND VCC

If using separate power supplies for VCC and VBATT, VBATT must be less than 0.3V above VCC when VCC is above the reset threshold. As described in the previous section, if VBATT ex- ceeds this limit and power is lost at VCC, current flows continuously from VBATT to VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC switch until the circuit is broken.

ALTERNATIVE CHIP-ENABLE GATING

Using memory devices with CE and CE inputs allows the SP791 CE loop to be bypassed. T o do this, connect CE IN to ground, pull up CE OUT to VOUT, and connect CE OUT to the CE input of each memory device as shown in Figure 13. The CE input of each part then connects directly to the chip-select logic, which does not have to be gated by the SP791.

ADDING HYSTERESIS TO THE POWER-FAIL COMPARATOR

Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is near the trip point. Figure 14 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 to R2 such that PFI sees 1.25V when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1µA to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10kΩ to prevent it from loading down the PFO pin. Capacitor C1 adds additional noise rejection.

MONITORING A NEGATIVE VOLTAGE

The power-fail comparator can be used to monitor a negative supply voltage using the circuit shown in Figure 15. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit's accuracy is affected by the PFI threshold tolerance, the VCC voltage, and resistors R1 and R2.

BACKUP-BATTERY REPLACEMENT

The backup battery may be disconnected while VCC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses.

Page 16

+5V

PFO

+5V

V–

5 - 1.25 1.25 - V

R1 R2

NOTE: V

TRIP

IS NEGATIVE.

START

Vcc

Corporation

GND

PFO

V–

SET WDI LOW

SUBROUTINE OR PROGRAM LOOP SET WDI HIGH

RETURN

PFI

TRIP

END

Figure 16. Watchdog Flow DiagramFigure 15. Monitoring a Negative Voltage

NEGATIVE-GOING VCC TRANSIENTS

The SP791 is relatively immune to short-duration negative-going VCC transients resulting from power up, power down, and brownout conditions. It is usually undesirable to reset the µP when VCC experiences only small glitches.

Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 40µs or less will not cause a reset pulse to be issued.

A 100nF bypass capacitor mounted close to the VCC pin provides additional transient immunity .

CONNECTING A TIMING CAPACITOR TO THE SWT PIN

To prevent timing errors minimize external cur rent leakage sources at this pin, and locate the capacitor as close to SWT as possible. The sum of PC board leakage + SWT capacitor leakage must be small compared to ±100 nA.

WATCHDOG SOFTWARE CONSIDERATIONS

A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than "pulsing" the watchdog input high-low-high or low-high-low.

This technique avoids a "stuck" loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out.

Figure 16 shows an example flow diagram where the I/O driving the watchdog input is set low at the beginning of the program, set high at the beginning of every subroutine or loop, then set low again when the program returns to the beginning. If the program should "hang" in any subroutine, the I/O is continually set high and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued.

MAXIMUM VCC FALL TIME

The VCC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/µs. A standard rule of thumb for filter capacitance on most regulators is on the order of 100µF per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial VCC fall rate is just the inverse of 1A/100µF =

0.01V/µs. The VCC fall rate decreases with time as VCC falls exponentially , which more than satisfies the maximum fall-time requirement.

Page 17

D1 = 0.005" min.

(0.127 min.)

e = 0.100 BSC

(2.540 BSC)

ALTERNATE

(BOTH ENDS)

END PINS

PACKAGE: PLASTIC

DUAL–IN–LINE (NARROW)

A1 = 0.015" min.

(0.381min.)

A = 0.210" max.

(5.334 max).

eA = 0.300 BSC

(7.620 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.355/0.400

(9.017/10.160)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.735/0.775

(18.669/19.685)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.780/0.800

(19.812/20.320)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

18–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.880/0.920

(22.352/23.368)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

20–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.980/1.060

(24.892/26.924)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

22–PIN8–PIN 14–PIN 16–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

1.145/1.155

(29.083/29.337)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

Page 18

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

8–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249

0.014/0.019 (0.35/0.49)

0.189/0.197 (4.80/5.00)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

PACKAGE: PLASTIC

h x 45°

14–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249)

0.013/0.020

(0.330/0.508)

0.337/0.344

(8.552/8.748)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

16–PIN

0.053/0.069

(1.346/1.748)

0.004/0.010

(0.102/0.249)

0.013/0.020

(0.330/0.508)

0.386/0.394

(9.802/10.000)

0.150/0.157

(3.802/3.988)

0.050 BSC

(1.270 BSC)

0.228/0.244

(5.801/6.198)

0.010/0.020

(0.254/0.498)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

SMALL OUTLINE (SOIC) (NARROW)

Page 19

ORDERING INFORMATION

Model Temperature Range Package

SP791CP ...................................................................................0˚C to +70˚C .............................................................................. 16-pin, Plastic DIP

SP791CN ................................................................................... 0˚C to +70˚C .......................................................................... 16-pin, Narrow SOIC

SP791EP .................................................................................... -40˚C to +85˚C .......................................................................... 16–pin, Plastic Dip

SP791EN ...................................................................................-40˚C to +85˚C ..................................................................... 16–pin, Narrow SOIC

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP791CN, SP791CP, SP791EN, SP791EP Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual