Datasheet SP693ACN, SP693ACP, SP693ACT, SP693AEN, SP693AEP Datasheet (Sipex Corporation)

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SP691A/693A/800L/800M

Low Power Microprocessor Supervisory

with Battery Switch-Over

■ Precision 4.65V/4.40V Voltage Monitoring

■ 200ms Or Adjustable Reset Time

■ 100ms, 1.6s Or Adjustable Watchdog Time

■ 60µA Maximum Operating Supply Current

■ 1.0µA Maximum Battery Backup Current

■ 0.1µA Maximum Battery Standby Current

■ Power Switching

250mA Output in Vcc Mode (0.6Ω) 25mA Output in Battery Mode (5Ω)

■ On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 6ns CE Gate Propagation Delay

■ Voltage Monitor for Power-Fail or Low Battery

■ Backup-Battery Monitor

■ RESET Valid to Vcc=1V

■ 1% Accuracy Guaranteed (SP800L/800M)

■ Pin Compatible Upgrade to MAX691A/693A/

800L/800M

DESCRIPTION

The SP691A/693A/800L/800M is a microprocessor (µP) supervisory circuit that integrates a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in µP and digital systems. The SP691A/693A/800L/800M offers complete µP monitoring and watchdog functions. The SP691A/693A/800L/800M is ideal for a low-cost battery management solution and is well suited for portable, battery-powered applications with its supply current of 35µA. The 6ns chip-enable propagation delay, the 25mA current output in battery-backup mode, and the 250mA current output in standard operation also makes the SP691A/693A/800L/800M suitable for larger scale, high-performance equipment.

rebmuNtraPdlohserhTTESERycaruccATESERycaruccAIFPhctiwSyrettaB-pukcaB

A196PSV56.4+Vm521+%4SEY A396PSV04.4+Vm521+%4SEY L008PSV56.4+Vm05+%1SEY M008PSV04.4+Vm05+%1SEY

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

Terminal Voltages (with respect to GND)

VCC.......................................................................................-0.3V to +6V

.....................................................................................-0.3V to +6V

BATT

All Other Inputs........................................................-0.3V to (V

Input Currents

VCC Peak...........................................................................................1.0A

VCC Continuous.............................................................................250mA

Peak....................................................................................250mA

BATT

Continuous............................................................................25mA

BATT

GND, BATT ON............................................................................100mA

All Other Inputs..............................................................................25mA

Enhanced ESD Specifications........................+4kV Human Body Model

Power Dissipation Per Package

16-pin PDIP (derate 14.3mW/OC above +70OC).......................1150mW

16-pin Narrow SOIC (derate 13.6mW/OC above 70OC)............1090mW

16-pin Wide SOIC (derate 11.2mW/OC above 70OC).................900mW

Storage Temperature....................................................-65OC to +150OC

Lead Temperature (soldering,10 sec).........................................+300OC

+0.3V)

SPECIFICATIONS

VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, V noted. Typical values apply at T

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50.0-

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TTAB

52.0-

TTAB

51.0-

TTAB

510.0-

VCC51.0-

VCC90.0-

2.1

9.0

1.0-

TTAB

70.0-

TTAB

50.0-

TTAB

Ω

0.2

5306

100.00.1

1.0-20.0

30.0+

TTAB

30.0-

TTAB

Ω

52 03

µA

siseretsyHrevohctiwSyrettaB06

= +2.8V, and T

BATT

VCCI,V5.4= VCCI,V5.4= VCCV,V0.3=

TTAB

>V(

= T

to T

MIN

Am52=

Am052=

unless otherwise

MAX

I,V8.2=

TUO

Am001=

AMB

TUO

TTAB

V5.4= V0.3=

I,V5.4=

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TUO

I,V8.2=

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Ignidulcxe,V8.2=

pu-rewop

nwod-rewop

kaePotkaeP

TUO

SPECIFICATIONS (continued)

VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, V noted. Typical values apply at T

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woLtuptuONOTTAB

trohStuptuONOTTAB

1.0

4.0

7.0

06 51001

5.1 Am

µA

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06.4

53.4

56.4

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56.4

04.4

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1.04.0

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1.04.0

µA

301Amtnerrucecruostuptuo

= +2.8V, and T

BATT

I I

Am2.3=

KNIS

Am52=

KNIS

A196PS A396PS L008PS M008PS

nwodrewop

kcolc

selcyc

pu-rewop

doirepgnol

doireptrohs

kcolc

selcyc

I I I

I I

doirepgnol

doireptrohs

V,V8.0=

05=µV,ACCV,V1=CCgnillaf

KNIS

ECRUOS

Am2.3=

KNIS

1=µV,ACCV5=

ECRUOS

Am2.3=

KNIS

005=µV,ACCV5=

ECRUOS

= T

to T

AMB

MIN

tnerrucknis

tnerrucecruos

V,Am2.3=

V,Am6.1=CCV5=

V,Am2.3=

unless otherwise

MAX

Vx57.0=

V52.4=

tnerrucecruostuptuo

SPECIFICATIONS (continued)

VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, V noted. Typical values apply at T

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56.30.2

2zHkCSO

= +2.8V, and T

BATT

= T

to T

MIN

unless otherwise

MAX

AMB

V0=IDW

V=IDW

TUO

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A396/A196PSV,

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V0=

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SPECIFICATIONS (continued)

VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, V noted. Typical values apply at T

NOTE 1: Either VCC or V NOTE 2: The supply current drawn by the SP691A/693A/800L/800M from the battery (excluding I goes to 5µA when (V

=+25OC.

AMB

can go to 0V, if the other is greater than 2.0V.

BATT

- 1V) < VCC < V

BATT

. In most applications, this is a brief period as VCC falls through this region.

BATT

NOTE 3: "+" = battery-discharging current, "-" = battery-charging current. NOTE 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. NOTE 5: RESET is an open-drain output and sinks current only. NOTE 6: WDI is internally connected to a voltage divider between V to 1.6V (typ), disabling the watchdog function. NOTE 7: The chip-enable resistance is tested with VCC = +4.75V for the SP691A/800L and VCC = +4.5V for the SP693A/800M. CEIN = CE

= VCC/2.

OUT

NOTE 8: The chip-enable propagation delay is measured from the 50% point at CEIN to the 50% point at CE

= +2.8V, and T

BATT

and GND. If unconnected, WDI is driven

OUT

= T

to T

MIN

unless otherwise

MAX

OUT

) typically

AMB

OUT

TYPICAL PERFORMANCE CHARACTERISTICS (T

Current (µA)

-60 -30 0 30 60 90 120

Figure 1. VCC Supply Current vs. Temperature (Normal Operating Mode)

75.0 VCC = 4.75V

70.0 V

= 2.8V

BATT

CE IN = VCC/2

65.0

60.0

55.0

50.0

CE-IN Resistance (Ω)

45.0

40.0

-80 -60 -40 -20 0 20 40 60 80 100 120 140

Figure 3. Chip-Enable On-Resistance vs. Temperature

VCC = 5V

= 2.8V

BATT

Temperature (oC)

Temperature (

Current (µA)

BATT

-0.5

Figure 2. Battery Supply Current vs. Temperature (Battery-Backup Mode)

Resistance (Ω)

Figure 4. V

= 25oC, unless otherwise noted)

AMB

2.5

2.0

VCC = 1.6V

= 2.8V

BATT

1.5

1.0

0.5

0.0

-60 -30 0 30 60 90 120 150

Temperature (

VCC = 0V

12 10

8 6 4

= 2V

2 0

BATT

= 2.8V

BATT

= 4.5V

BATT

-60 -30 0 30 60 90 120 150

Temperature (oC)

to V

BATT

On-Resistance vs. Temperature

OUT

TYPICAL PERFORMANCE CHARACTERISTICS (T

1.256

VCC = 4.5V

0.9 V

= 2.8V

BATT

1.252

= 25oC, unless otherwise noted)

AMB

VCC = 5V

= 0V

BATT

0.7

0.5

Resistance (Ω)

0.3

-60 -30 0 30 60 90 120 150

Temperature (oC)

Figure 5. VCC to V

4.69

4.68

On-Resistance vs. Temperature

OUT

= 0V

BATT

4.67

4.66

4.65

4.64

4.63

4.62

Reset Threshold (V)

4.61

4.60

-60 -30 0 30 60 90 120 150

Temperature (

V VCC Falling

Rising

1.248

1.244

PFI Threshold (V)

1.240

1.236

-60 -30 0 30 60 90 120 150

Temperature (oC)

Figure 6. PFI Threshold vs. Temperature

400 350 300 250 200 150

Resistance (Ω)

100

Sourcing VCC = 5V Sinking VCC = 4.25V

-60 -30 0 30 60 90 120 150

Temperature (oC)

Figure 7. Reset Threshold vs. Temperature

0.240

0.230

0.220

VCC = 5V

BATT

= 2.8V

Figure 8. RESET Output Resistance vs. Temperature

1.E-04

1.E-05

1.E-06

1.E-07

= 2.8V

BATT

1.E-08

0.210

0.200

0.190

Reset Timeout Period (s)

0.180

-60 -30 0 30 60 90 120 150

Temperature (oC)

Figure 9. Reset Delay vs. Temperature

1.E-09

1.E-10

1.E-11

Current (A), Log Scale

1.E-12

BATT

1.E-13

1.E-14 0 1 2 3 4 5

(V)

Figure 10. Battery Current vs. Input Supply Voltage

TYPICAL PERFORMANCE CHARACTERISTICS (T

= 25oC, unless otherwise noted)

AMB

1000

100

Timeout Period (s)

Watchdog and Reset

Long Watchdog Timeout Period Reset Active Timeout Period Short Watchdog Timeout Period

0.1 10 100 1000 10000

OSCIN Capacitor (pF)

VCC = 5V

= 2.8V

BATT

Figure 11. Watchdog and Reset Timeout Period vs. OSCIN Timing Capacitor (C

1000

100

Voltage Drop (mV)

OSC

)

VCC = 4.5V V

= 0V

BATT

Slope = 0.6Ω

Propagation Delay (µs)

VCC = 5V

= 2.8V

BATT

50Ω driver

0 50 100 150 200 250 300 350

Cload (pF)

Figure 12. Chip-Enable Propagation Delay vs. CE Load Capacitance

1000

100

Voltage Drop (mV)

VCC = 4.5V V

= 0V

BATT

Slope = 5Ω

OUT

1 10 100 1000

Figure 13. VCC to V Operating Mode)

(mA)

OUT

vs. Output Current (Normal

OUT

Reset

Threshold

+5V

1 10 100 1000

Figure 14. V Backup Mode)

BATT

to V

(mA)

OUT

vs. Output Current (Battery-

OUT

80µs

RESET

LOW

1.1µs

LOWLINE

LOW

16µs

OUT

Figure 15. VCC to LOWLINE and CE

LOW

OUT

Delay

PINOUT

LOWLINE

VBATT

VOUT

Vcc

GND

BATT ON

OSC

SEL

Pin 7 — OSCIN — External Oscillator Input.

TOP VIEW

Corporation

14 13 12

RESET RESET WDO

CE CEOUT WDI

PFO

PFI

1 2 3 4 5 6 7

DIP/SO

When OSC HIGH, a 10µA pull-up connects from V to this input pin, the internal oscillator sets the reset and watchdog timeout periods, and this input pin selects between fast and slow watchdog timeout periods. When OSC driven LOW, the reset and watchdog timeout periods may be set either by a capacitor from this input pin to ground or by an external clock at this pin (refer to Figure 21).

is unconnected or driven

SEL

OUT

PIN ASSIGNMENTS

Pin 1 — V

to the external battery supply or super-

— Battery-Backup Input. Connect

BATT

charging capacitor and charging circuit. If a backup battery is not provided, connect this pin to ground.

Pin 2 —V

— Output Supply Voltage. V

OUT

connects to VCC when VCC is greater than V

and VCC is above the reset threshold.

BATT

When VCC falls below V below the reset threshold, V V

. Connect a 0.1µF capacitor from V

BATT

and VCC is

BATT

connects to

OUT

to GND.

Pin 3 — V

— +5V Input Supply Voltage.

Pin 4 — GND — Ground reference for all

signals.

Pin 5 — BATT ON — Battery On Output. Goes

high when V when V

switches to V

OUT

switches to VCC. Connect the base

OUT

. Goes low

BATT

of a PNP through a current-limiting resistor to BATT ON for V

current requirements

OUT

greater than 250mA.

Pin 6 — LOWLINE — Low Line Output. This

output pin goes LOW when VCC falls below the reset threshold voltage. This output pin returns to it's HIGH output as soon as V rises above the reset threshold voltage.

Pin 8 — OSC

OSC

SEL

— Oscillator Select. When

SEL

is unconnected or driven HIGH, the internal oscillator sets the reset delay and watchdog timeout period. When OSC

SEL

is driven LOW, the external oscillator input pin, OSCIN, is enabled (refer to Table 1). This input pin has a 10µA internal pull-up.

Pin 9 — PFI — Power-Fail Input. This is the

noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or V

when not used.

OUT

Pin 10 — PFO — Power-Fail Output. This is

the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V . This is an uncommitted comparator, and has no effect on any other internal circuitry .

Pin 11 — WDI — Watchdog Input. This is a

three-level input pin. If WDI remains either HIGH or LOW for longer than the watchdog timeout period, WDO goes LOW and RESET is asserted for the reset timeout period. WDO remains LOW until the next transition at this input pin. Leaving this input pin unconnected disables the watchdog function. This input pin connects to an internal voltage divider between V

and ground, which sets it to

OUT

mid-supply when left unconnected.

Pin 12 — CE

— Chip-Enable Output. This

OUT

output pin goes LOW only when CEIN is LOW and VCC is above the reset threshold voltage. If CEIN is LOW when RESET is asserted, this output pin will stay low for 16µs or until CEIN goes HIGH, whichever occurs first.

Pin 13 — CEIN — Chip-Enable Input. This is the

input pin to the chip-enable gating circuit. If this input pin is not used, connect it to ground or V

OUT

Pin 14 — WDO — Watchdog Output. If WDI

remains HIGH or LOW longer than the watchdog timeout period, this output pin goes LOW and RESET is asserted for the reset timeout period. This output pin returns HIGH on the next transition at WDI. This output pin remains HIGH if WDI is unconnected.

Pin 15 — RESET — Active LOW Reset Output.

This output pin goes LOW whenever V falls below the reset threshold. This output pin will remain low typically for 200ms after VCC crosses the reset threshold voltage on power-up.

Pin 16 — RESET — Active HIGH Reset

Output. This output pin is open drain and the inverse of RESET.

PFI

Watchdog

Timer

1.25V

Reset

Generator

OUT

Control

OSC

WDI

SEL

BATT

Watchdog

Transition

Detector

Reset /

Watchdog

Timebase

4.65V or

4.40V*

4.65V for the SP691A/800L

4.40V for the SP693A/800M

Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M

PFO

WDO

RESET

LOWLINE

OUT

BATT ON

GND

OUT

µP

A0-A15

BUS

CMOS

RAM

Regulated +5V

RESET

NMI I/O LINE

Address

Decode

Unregulated DC

PFI

RESET

PFO

WDI

Backup

BATT

Supply

BATT ON

OUT

WDO

LOWLINE

alarm

system status indicator

0.1µF

Figure 17. Typical Application Circuit of the SP691A/693A/800L/800M

FEATURES

The SP691A/693A/800L/800M devices are microprocessor (µP) supervisory circuits that monitor the power supplied to digital circuits such as microprocessors, microcontrollers, or memory. The SP691A/693A/800L/800M series is an ideal solution for portable, batterypowered equipment that require power supply monitoring. The SP691A/693A/800L/800M watchdog functions will continuously oversee the operational status of a system. Implementing the SP691A/693A/800L/800M series will reduce the number of components and overall complexity in a design that requires power supply monitoring circuitry. The operational features and benefits of this series are described in more detail below.

GND

THEORY OF OPERATION

The SP691A/693A/800L/800M series is a complete µP supervisor IC and provides the following main functions:

1) µP reset ➡ Reset output is asserted during

power fluxiations such as power-up, power-down, and brown out conditions, and is guaranteed to be in the correct state for VCC down to 1V, even with no battery in the circuit.

2) µP reset ➡ Reset output is pulsed if the

optional watchdog timer has not been toggled within a specified time.

3) Power Fail Comparator ➡ Provides for

power-fail warning and low-battery detection, or monitors another power supply.

4) Watchdog function ➡ Monitors µP activity

where the watchdog output goes to a logic LOW state if the watchdog input is not toggled for greater than the timeout period.

5) Internal switch ➡ Switches over from V

to V threshold.

if the VCC falls below the reset

BATT

RESET and RESET Outputs

The SP691A/693A/800L/800M devices' RESET and RESET outputs ensure that the µP powers up in a known state, and prevents code-execution errors during power-down or brownout conditions.

The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, RESET sources

1.6mA at typically VOUT – 0.5V. RESET output is open drain, active high, and typically sinks

3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is guaranteed to be valid down to VCC = 1V, and an external 10kΩ pull-down resistor on RESET ensures that RESET will be valid with VCC down to GND as shown on Figure 18. As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the RDS(ON) and the saturation voltage. The 10kΩ pull-down resistor ensures the parallel combination of switch plus resistor is around

RESET

Corporation

Figure 18. External Pull-down Resistor Ensures RESET is Valid with VCC Down to Ground.

TO µP RESET

10kΩ

10kΩ and the output saturation voltage is below

0.4V while sinking 40µA. When using a 10kΩ external pull-down resistor, the high state for the RESET output with Vcc = 4.75V is 4.5V typical. For battery voltages less than or equal to 2V connected to VBATT, RESET and RESET remains valid for VCC from 0V to 5.5V.

RESET and RESET are asserted when VCC falls below the reset threshold and remain asserted for the Reset Timeout Period (200ms nominal) after VCC rises above the reset threshold voltage on power-up. Refer to F igur e 19. The devices' battery-switchover comparator does not affect reset assertion. However, both reset outputs are asserted in battery-backup mode since VCC must be below the reset threshold to enter this mode.

Vcc

RESET

THRESHOLD

OUT

12µ

100µs

RESET RESET

Figure 19. Reset and Chip-Enable Timing

WDI

WDO

RESET

t1 = RESET Timeout Period t2 = Normal Watchdog Timeout Period t3 = Watchdog Timeout Period Immediately After RESET

Figure 20. Watchdog Timeout Period and Reset Active Time

Watchdog Function

The watchdog monitors µP activity via the Watchdog Input (WDI). If the µP becomes inactive, RESET and RESET are asserted. To use the watchdog function, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6s nominal). WDO, RESET , and RESET are asserted, indicating a software fault or idle conditions. Refer to RESET and RESET

Outputs and Watchdog Output sections.

Watchdog Input

A change of logic state (minimum 100ns duration) at WDI during the watchdog period will reset the watchdog timer. The watchdog default timout is 1.6sec.

To disable the watchdog function, leave WDI floating. An internal resistor network (100kΩ equivalent impedance at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When Vcc is below the reset threshold, the watchdog function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance.

OSC

No Connect

SEL

No Connect

600 x C

47pF

OSC

1.6sec Normal Watchdog Timeout

Internal Oscillator

OSC

100ms Normal Watchdog Timeout

Internal Oscillator

OSC

Normal Watchdog Timeout = [ms]

External Oscillator

Watchdog Output

WDO remains high if there is activity (transition or pulse) at WDI during the watchdog-timeout period. The watchdog function is disabled and

OSC

SEL

WDO is a logic high when VCC is less than the reset threshold or when WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog-timeout period,

Normal Watchdog Timeout = 1024 Clock Periods

External Clock

Figure 21. Selecting Timeout Periods

CSO

LES

WOLtupnIkcolClanretxEskcolc4201skcolc6904skcolc8402 WOLroticapaClanretxEsm)CxFp74/006(ces)Cxfp7.4/4.2(sm)CxFp74/0021(

gnitaolFWOLsm001s6.1sm002 gnitaolFgnitaolFs6.1s6.1sm002

Table 1. Reset Pulse Width and Watchdog Timeout Selections

CSO

lamroNteseRretfAyletaidemmI

doirePtuoemiTgodhctaW

doirePtuoemiTteseR

RESET and RESET are asserted for the reset timeout period (200ms nominal). WDO goes to logic low and remains low until the next transition at WDI. Refer to Figure 20. If WDI is held high or low indefinitely, RESET and RESET will generate 200ms pulses every 1.6s. WDO has a 2 x TTL output characteristic.

Selecting an Alternative Watchdog Timeout Period

The OSC watchdog are reset timeout periods. Floating OSC

SEL

selects the nominal 1.6s watchdog timeout

and OSCIN inputs control the

SEL

and OSCIN or tying them both to V

OUT

period and 200ms reset timout period. Connecting OSCIN to ground and floating or connecting OSC mal watchdog timeout period and a 1.6s timeout

SEL

to V

selects a 100ms nor-

OUT

period immediately after reset. The reset timeout period remains 200ms. Refer to Figure 20. Select alternative timeout periods by connecting OSC

to ground and connecting a capacitor

SEL

between OSCIN and ground, or by externally driving OSCIN . A synopsis of this control can be found in Figure 21 and Table 1.

Chip-Enable Signal Gating

The SP691A/693A/800L/800M devices provide internal gating of chip-enable (CE) signals, to prevent erroneous data from corrupting the CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The SP691A/ 693A/800L/800M devices use a series transmission gate from CEIN to CE

. Refer to Figure 16.

OUT

The 10ns maximum CE propagation from CE to CE 800M devices to be used with most µPs.

enables the SP691A/693A/800L/

OUT

Chip-Enable Input

CEIN is in high impedance (disabled mode) while RESET and/or RESET are asserted.

During a power-down sequence where VCC falls below the reset threshold, CEIN assumes a high impedance state when the voltage at CEIN goes high or 12µs after RESET is asserted, whichever occurs first. Refer to Figure 19. During a power-up sequence, CEIN remains high impedance until RESET is deasserted.

In the high-impedance mode, the leakage currents into CEIN are <1µA over temperature. In the low-impedance mode, the impedance of CEIN appears as a 65Ω resistor in series with the load at CE

OUT

The propagation delay through the CE transmission gate depends on both the source impedance of the drive to CEIN and the capacitive loading on CE Chip-Enable Propagation Delay vs. CE Load Capacitance graph in the Typical

(see the

OUT

Performance Characteristics section). The CE propagation delay is defined from the 50% point on CEIN to the 50% point on CE a 50Ω driver and 50pF of load capacitance as in

OUT

using

Figure 22. For minimum propagation delay, minimize the capacitive load at CE a low output-impedance driver.

and use

OUT

+5V

BATT

2.8V

Figure 22. Chip Enable Propagation Delay Test Circuit Figure 23. Low-Battery Indicator Circuit

GND

OUT

LOAD

+2.0V

+5.5V

BATT

PFI

PFO

GND

LOW BATT

Chip-Enable Output

In the enabled mode, the impedance of CE is equivalent to 65Ω in series with the source

OUT

driving CEIN. In the disabled mode, the 65Ω transmission gate is off and CE pulled to VOUT. This source turns off when the

is actively

OUT

transmission gate is enabled.

LOWLINE Output

LOWLINE is the buffered output pin of the reset threshold comparator. Refer to F igur e 16. LOWLINE typically sinks 3.2mA at 0.1V. For normal operation where VCC is above the reset threshold, LOWLINE is pulled to V

OUT

Power-Fail Comparator

The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the SP691A/693A/800L/800M devices. Common uses include low battery detection, as found in Figure 23, and early power-fail detection when the unregulated power is easily accessible as shown in Figur e 17.

Power-Fail Input

The Power-Fail Input (PFI) has a guaranteed input leakage of +25nA max over temperature. The typical comparator delay is 25µs from VIL to VOL (power failing), and 60µs from VIH to VOH (power being restored). Connect this input to ground if PFI is not used.

Power-Fail Output

The Power-Fail Output (PFO) goes low when PFI goes below 1.25V. It sinks 3.2mA with a saturation voltage of 0.1V. With PFI above

1.25V, PFO is actively pulled to VOUT. PFO can be used to generate an NMI for the µP, as shown in Figure 17.

Battery-Backup Mode

The SP691A/693A/800L/800M requires two conditions to switch to battery-backup mode:

1) VCC must be below the reset threshold; 2) VCC must be below VBATT. Table 2 lists the status of the inputs and outputs in batterybackup mode.

Battery-On Output

The Battery On Output (BATT ON) indicates the status of the internal VCC/battery-switchover comparator, which controls the internal VCC and VBA TT switches. For VCC greater that VBATT (ignoring the small hysteresis effect), BA TT ON is a logic low. For VCC less than V ON is a logic high. Use BATT ON to indicate

BATT

, BATT

battery-switchover status or to supply base drive to an external pass transistor for higher-current applications. Refer to Figure 17.

EMANSUTATSREBMUNNIP

TTAB

TUO

1sitnerrucylppuSµVnehwmumixamA

Votdetcennoc

TTAB

Vmorfdetcennocsid

TUO

V(<

.)V2.1-1

TTAB

.hctiwsSOMPlanretninahguorht2

VsrotinomrotarapmocrevohctiwsyrettaB

V.revohctiwsevitcarof

DNG.slangisllarofecnereferV0 4

NOTTABVotlauqesiegatlovtuptuotiucric-nepoehT.HGIHcigoL

TUO

ENILWOL.WOLcigoL 6

CSO

CSO CSO

LES

.Z-hgihtasidnaderongisi 7

.Z-hgihtasidnaderongisi 8

IFP.delbasidsirotarapmocliaf-rewopehT 9

OFP .WOLcigolotdecrofsiOFP.delbasidsirotarapmocliaf-rewopehT 01

IDW.Z-hgihtasidnaderongisiIDW 11

Votlauqesiegatlovtuptuotiucric-nepoehT.HGIHcigoL

TUO

.Z-hgiH 31

ODWVotlauqesiegatlovtuptuotiucric-nepoehT.HGIHcigoL

.21

TUO

.41

TUO

TESER.WOLcigoL 51 TESER.Z-hgiH 61

Table 2. Input and Output Status in Battery-Backup Mode; to enter the Battery-Backup Mode, VCC must be less than the reset threshold and less than V

BATT

Input Supply Voltage

The Input Supply Voltage (VCC) should be a regulated +5V source. VCC connects to VOUT

BATT

via a parallel diode and a large PMOS switch. The switch carries the entire current load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances

SW1

SW2

less than 1Ω each. Refer to Figure 24. The maximum continuous current is 250mA, but

OUT

0.1µF

power-on transients may reach a maximum of 1A.

Backup-Battery Input

The Backup-Battery Input (VBATT) is similar

Figure 24. VCC and V

BATT

to V

OUT

Switch

to VCC, except the PMOS switch and parallel diode are much smaller. Refer to Figure 24. Accordingly, the on-resistances of the diode and the switch are each approximately 10Ω.

+5V

BATT

Vcc

Corporation

GND

VOUT

BATT

1N4148

(

0.47F

Figure 25. High Capacity Capacitor on V

Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than 1µA over temperature and supply voltage.

Output Supply Voltage

The Output Supply Voltage (VOUT) supplies all the current to the external system and internal circuitry. All open-circuit outputs will assume the VOUT voltage in their high states rather than the VCC voltage. At the maximum source current of 250mA, VOUT will typically be 150mV below VCC. VOUT should be decoupled with 0.1µF capacitor.

2) Battery-backup mode where VCC is typically within 0.7V below V powered from V current from the battery is typically less

. All circuitry is

BATT

and the supply

BATT

than 5µA.

3) Battery-backup mode where VCC is less than V

by at least 0.7V. V

BATT

current is less than 1µA max.

BATT

supply

Using High Capacity Capacitor with the SP691A/693A/800L/800M Series

VBATT has the same operating voltage range as VCC, and the battery-switchover threshold voltages are typically +30mV centered at VBATT, allowing use of a capacitor and a simple charging circuit as a backup source. Refer to Figure 25.

If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC.

Leakage current through the capacitor charging diode and SP691A/693A/800L/800M internal power diode eventually discharges the capacitor to VCC. Also, if VCC and VBA TT start from 0.5V above the reset threshold and power is lost at VCC, the capacitor on VBA TT dischar ges through VCC until VBA TT reaches the reset threshold; the SP691A/693A/800L/800M devices then switch to battery-backup mode.

TYPICAL APPLICATIONS

The SP691A/693A/800L/800M devices are not short-circuit protected. Shorting VOUT to ground, other than power-up transients such as charging a decoupling capacitor, may destroy the device. All open-circuit outputs swing between VOUT and GND rather than VCC and GND. If long leads connect to the chip inputs, ensure that these lines are free from ringing and other conditions that would forward bias the

Using Separate Power Supplies f or V and V

If using separate power supplies for VCC and

BATT

VBATT, VBATT must be less than 0.3V above VCC when VCC is above the reset threshold. As described in the previous section, if VBATT exceeds this limit and power is lost at VCC, current flows continuously from VBATT to VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC switch until the circuit is broken. Refer to Figure 24.

chip's protection diodes.

Alternative Chip-Enable Gating

There are three distinct modes of operation:

1) Normal operating mode with all circuitry powered from VCC. T ypical supply current from VCC is 35µA, while only leakage currents flow from the battery.

Using memory devices with CE and CE inputs allows the CE loop of the SP691A/693A/800L/ 800M series to be bypassed. To do this, connect CEIN to ground, pull up CE

to VOUT,

OUT

GND

Active-HIGH

CE Logic Lines

for Memory Devices

Minimum value of RP is 1kΩ.

Maximum value of RP is dependent on the connected number of RAMs, n.

OUT

RP*

OUT

CE CE

RAM

+5V

PFI

PFO

GND

TRIP

1.25

R1 + R

1.25

PFO

+5V

VH =

TRIP

- 1.25 R

1.25

R1 + R2 || R

*optional

connect to µP

5.0 - 1.25

|| R

Figure 26. Alternate Chip Enable Gating

and connect CE memory device as shown in Figur e 26. The CE

to the CE input of each

OUT

input of each part then connects directly to the chip-select logic, which does not have to gated by the SP691A/693A/800L/800M devices.

Adding Hysteresis to the Power-Fail Comparator

Hysteresis adds noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is near the power-fail comparator trip point. Figur e 27 shows how to add hysteresis to the power-fail comparator . Select the ratio of R1 and R2 such that PFI sees 1.25V when V falls to the desired trip point (V R3 adds hysteresis. It will typically be an order

). Resistor

TRIP

of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1µA to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should

Figure 27. Adding Hysteresis to the Power-Fail Comparator

be larger than 10kΩ to prevent it from loading down the PFO pin. Capacitor C1 adds additional noise rejection.

Monitoring a Negative Voltage

The power-fail comparator can be used to monitor a negative supply voltage using the circuit shown in Figur e 28. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit's accuracy is affected by the PFI threshold tolerance, the VCC voltage, and resistors R1 and R2.

Backup-Battery Replacement

The backup battery may be disconnected while VCC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses.

+5V

PFI

PFO

GND

5.0 - 1.25

1.25 - V

PFO

+5V

TRIP

is a negative voltage

Figure 28. Monitoring a Negative Voltage

V-

160

0.1µF Capacitor V

to GND

120

Duration (µs)

Maximum Transient

OUT

Above Line

Reset Generated

V-

1 10 1000 10000

Reset Comparator Overdrive

TRIP

Figure 29. Maximum Transient Duration Without Causing a Reset Pulse vs. Reset Comparator Overdrive

(Reset Threshold Voltage - V

), (mV)

As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 40µs or less will not cause a reset pulse to be issued. A 100nF bypass capacitor mounted close to the VCC pin provides additional transient immunity .

Connecting a Timing Capacitor to OSC

Negative-Going VCC T ransients

While asserting resets to the µP during power-up, power-down, and brownout conditions, these supervisors are relatively immune to shortduration negative-going VCC transients. It is usually undesirable to reset the µP when VCC experiences only small glitches.

When OSC disconnects from its internal 10µA pull-up and is internally connected to a +100nA current source. When a capacitor is connected from OSCIN to ground (to select an alternative watchdog timeout period), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and

is connected to ground, OSC

SEL

watchdog timeout period. To prevent timing Refer to Figur e 29 for a graph of the maximum transient duration vs. the reset-comparator overdrive for which reset pulses are not generated. The graph was produced using negative-going pulses, starting at 5V and ending below the

errors, minimize external current leakage

sources at this pin, and locate the capacitor as

close to OSCIN as possible. The sum of any PC

board leakage plus the OSC capacitor leakage

must be small compared to +100nA. reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse width a negative-going VCC transient may typically have without causing a reset pulse to be issued.

Watchdog Software Considerations

A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than "pulsing" the watchdog input high-low-high or low-high-low. This technique avoids a "stuck" loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out.

Figure 30 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subrouting or loop, then set high again when the program returns to the beginning. If the program should "hang" in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued.

Maximum VCC Fall Time

The VCC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/µs. A standard rule of thumb for filter capacitance on most regulators is on the order of 100µF per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial VCC fall rate is just the inverse of 1A/100µF =

0.01V/µs. The VCC fall rate decreases with time as VCC falls exponentially, which more than satisfies the maximum fall-time requirement.

START

SET WDI LOW

SUBROUTINE OR PROGRAM LOOP SET WDI HIGH

RETURN

END

Figure 30. Watchdog Flow Diagram

D1 = 0.005" min.

(0.127 min.)

e = 0.100 BSC

(2.540 BSC)

ALTERNATE

END PINS

(BOTH ENDS)

PACKAGE: PLASTIC

DUAL–IN–LINE (NARROW)

A1 = 0.015" min.

(0.381min.)

A = 0.210" max.

(5.334 max).

eA = 0.300 BSC

(7.620 BSC)

DIMENSIONS (Inches)

Minimum/Maximum

(mm) A2

16–PIN

0.115/0.195

(2.921/4.953)

0.014/0.022

(0.356/0.559)

0.045/0.070

(1.143/1.778)

0.008/0.014

(0.203/0.356)

0.780/0.800

(19.812/20.320)

0.300/0.325

(7.620/8.255)

0.240/0.280

(6.096/7.112)

0.115/0.150

(2.921/3.810)

0°/ 15°

(0°/15°)

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC) (NARROW)

h x 45°

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

(1.346/1.748)

(0.102/0.249)

(0.330/0.508)

(9.802/10.000)

(3.802/3.988)

(1.270 BSC)

(5.801/6.198)

(0.254/0.498)

(0.406/1.270)

16–PIN

0.053/0.069

0.004/0.010

0.013/0.020

0.386/0.394

0.150/0.157

0.050 BSC

0.228/0.244

0.010/0.020

0.016/0.050

0°/8°

(0°/8°)

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC) (WIDE)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

16–PIN

0.093/0.104

(2.352/2.649)

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.398/0.413

(10.10/10.49)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

ORDERING INFORMATION

Model Temperature Range Package Type

SP691ACP ............................................... 0OC to +70OC...................................16-Pin Plastic DIP

SP691ACN............................................... 0OC to +70OC...............................16-Pin Narrow SOIC

SP691ACT ............................................... 0OC to +70OC........................................... 16-Pin SOIC

SP691AEP ............................................. -40OC to +85OC .................................16-Pin Plastic DIP

SP691AEN ............................................. -40OC to +85OC ............................. 16-Pin Narrow SOIC

SP691AET ............................................. -40OC to +85OC ......................................... 16-Pin SOIC

SP693ACP ............................................... 0OC to +70OC...................................16-Pin Plastic DIP

SP693ACN............................................... 0OC to +70OC...............................16-Pin Narrow SOIC

SP693ACT ............................................... 0OC to +70OC........................................... 16-Pin SOIC

SP693AEP ............................................. -40OC to +85OC .................................16-Pin Plastic DIP

SP693AEN ............................................. -40OC to +85OC ............................. 16-Pin Narrow SOIC

SP693AET ............................................. -40OC to +85OC ......................................... 16-Pin SOIC

SP800LCP ............................................... 0OC to +70OC...................................16-Pin Plastic DIP

SP800LCN ............................................... 0OC to +70OC...............................16-Pin Narrow SOIC

SP800LCT................................................ 0OC to +70OC........................................... 16-Pin SOIC

SP800LEP ............................................. -40OC to +85OC .................................16-Pin Plastic DIP

SP800LEN ............................................. -40OC to +85OC ............................. 16-Pin Narrow SOIC

SP800LET.............................................. -40OC to +85OC ......................................... 16-Pin SOIC

SP800MCP .............................................. 0OC to +70OC...................................16-Pin Plastic DIP

SP800MCN .............................................. 0OC to +70OC...............................16-Pin Narrow SOIC

SP800MCT............................................... 0OC to +70OC........................................... 16-Pin SOIC

SP800MEP............................................. -40OC to +85OC .................................16-Pin Plastic DIP

SP800MEN ............................................ -40OC to +85OC ............................. 16-Pin Narrow SOIC

SP800MET............................................. -40OC to +85OC ......................................... 16-Pin SOIC

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP693ACN, SP693ACP, SP693ACT, SP693AEN, SP693AEP Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual