Datasheet SP526CF Datasheet (Sipex Corporation)

Download

Page 1

WAN Multi-Mode Serial Transceiver

■ Low-Cost Programmable Serial Transceiver

■ Four (4) Drivers and Four (4)) Receivers

■ Driver and Receiver Tri-state Control

■ Software Selectable Protocol Selection

■ Interface Modes: ✓ RS-232 (V.28) ✓ RS-422 (V.11, X.21) ✓ EIA-530 or RS-449 (V.10, V.11)

■ Designed to Meet All NET1/2 Compliancy

Requirements

■ High ESD Tolerance

✓ ±15kV per Human Body Model ✓ ±15kV per IEC1000-4-2 Air Discharge ✓ ±8kV per IEC1000-4-2 Contact Discharge

1.0µF

T1IN

ENT1

T2IN

ENT2

T3IN

ENT3

T4IN

ENT4

R1OUT

ENR1

R2OUT

ENR2

R3OUT

ENR3

R4OUT

ENR4

+5V

1.0µF

SP526

GND

1.0µF

T1OUTA

T1OUTB

T2OUTA

T2OUTB

T3OUTA

T3OUTB

T4OUT

R1INA

R1INB

R2INA

R2INB

R3INA

R3INB

R4INA

R4INB

GND

C1+

C1–

C2+

C2–

SP526

DESCRIPTION

The SP526 is a monolithic device that supports three (3) physical layer serial interface standards. The SP526 is fabricated using a low power BiCMOS process technology, and incorporates four (4) drivers and four (4) receivers can be configured via software for the selected interface modes at any time. The SP526 includes tri-state ability for the driver and receiver outputs through separate enable lines. A shutdown mode is also included through the mode select pins for power savings. When mated with the SP322 V.11/V.35 Programmable Transceiver, the SP526 provides the four (4) channels needed for handshaking/control lines such as CTS, RTS, etc. The two transceiver ICs are an ideal solution for WAN serial ports in networking equipment such as routers, DSU/CSU's, and other access devices.

Page 2

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VCC............................................................................+7V

Input Voltages:

Logic...............................-0.3V to (VCC+0.5V)

Drivers............................-0.3V to (VCC+0.5V)

Receivers........................................±15.5V

Output Voltages:

Logic................................-0.3V to (VCC+0.5V)

Drivers................................................±15V

STORAGE CONSIDERATIONS

Due to the relatively large package size of the 44-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order remove moisture prior to soldering. Sipex ships the 44-pin QFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.

Receivers........................-0.3V to (VCC+0.5V)

Storage Temperature..........................-65˚C to +150˚C

Power Dissipation

(derate 14.3mW/˚C above 70˚C)................1144mW

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

LOGIC INPUTS

2.0 Volts

LOGIC OUTPUTS

2.4 Volts I

V.28 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±15 Volts per Figure 1 Loaded Voltage ±5.0 ±15 Volts per Figure 2 Short-Circuit Current ±100 mA per Figure 4 Power-Off Impedance 300 Ω per Figure 5

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 1.5 µs per Figure 6; +3V to -3V Instantaneous Slew Rate 30 V/µs per Figure 3 Propagation Delay

PHL

PLH

Max.Transmission Rate 120 230 kbps

0.5 1 5 µs

0.8 Volts

0.4 Volts I

= – 3.2mA

OUT

= 1.0mA

OUT

V.28 RECEIVER

DC Parameters

Inputs

Input Impedance 3 7 kΩ per Figure 7 Open-Circuit Bias +2.0 Volts per Figure 8 HIGH Threshold 1.7 3.0 Volts LOW Threshold 0.8 1.2 Volts

AC Parameters VCC = +5V for AC parameters

Propagation Delay

PHL

PLH

50 100 500 ns 50 100 500 ns

Page 3

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

V.28 RECEIVER (continued)

AC Parameters (cont.)

Max.Transmission Rate 120 230 kbps

V.10 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±4.0 ±6.0 Volts per Figure 9 Test-Terminated Voltage 0.9V Short-Circuit Current ±150 mA per Figure 11

Power-Off Current ±100 µA per Figure 12

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 200 ns per Figure 10; 10% to 90% Propagation Delay

PHL

PLH

Max.Transmission Rate 120 kbps

50 100 500 ns 50 100 500 ns

V.11 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±5.0 Volts per Figure 14 Test Terminated Voltage ±2.0 Volts per Figure 15

Balance ±0.4 Volts per Figure 15 Offset +3.0 Volts per Figure 15 Short-Circuit Current ±150 mA per Figure 16 Power-Off Current ±100 µA per Figure 17

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 25 ns per Figures 19 and 24; 10% to 90% Propagation Delay Using RL = 100Ω and CL = 50pF;

PHL

PLH

Differential Skew 20 40 ns per Figures 21 and 24, Max.Transmission Rate 10 Mbps

0.5V

0.67V

50 80 115 ns per Figures 21 and 24 50 80 115 ns per Figures 21 and 24

Volts per Figure 10

Volts

SKEW

= | t

DPLH

- t

DPHL

V.11 RECEIVER

DC Parameters

Inputs

Common Mode Range –7 +7 Volts Sensitivity ±0.3 Volts

Page 4

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

V.11 RECEIVER (continued)

DC Parameters (cont.)

Input Current –3.25 +3.25 mA per Figure 18 and 20 Input Impedance 4 kΩ

AC Parameters VCC = +5V for AC parameters

Propagation Delay Using RL = 100Ω and CL = 50pF; t

PHL

PLH

Differential Skew 20 ns per Figure 21, t Max. Transmission Rate 10 Mbps

POWER REQUIREMENTS

(V.28/RS-232) 35 45 mA fIN = 120kbps; Drivers active & loaded.

(V.11/RS-422) 130 150 mA fIN = 2.1Mbps; Drivers active & loaded.

(EIA-530/RS-449) 105 130 mA fIN = 1.0Mbps; Drivers active & loaded.

(Shutdown) 4 µA D0 = D1 = 0V, refer to

ENVIRONMENTAL AND MECHANICAL

Operating Temperature Range 0 +70 °C Storage Temperature Range –65 +150 °C

80 110 160 ns per Figure 21 and 26 80 110 160 ns per Figure 21 and 26

SKEW

4.75 5.00 5.25 Volts All ICC values are with V

= | t

Table 1

PLH

= +5V

- t

PHL

Page 5

OTHER AC CHARACTERISTICS

TA = +25°C and VCC = +5.0V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 DRIVERS

; Tri-state to Output LOW 0.70 5.0 µsCL = 100pF, Fig. 22 & 28 ; S1 closed

PZL

; Tri-state to Output HIGH 0.40 2.0 µsCL = 100pF, Fig. 22 & 28 ; S2 closed

PZH

; Output LOW to Tri-state 0.20 2.0 µsCL = 100pF, Fig. 22 & 28 ; S1 closed

PLZ

; Output HIGH to Tri-state 0.40 2.0 µsCL = 100pF, Fig. 22 & 28 ; S2 closed

PHZ

RS-423/V.10 DRIVERS

; Tri-state to Output LOW 0.15 2.0 µsCL = 100pF, Fig. 22 & 28 ; S1 closed

PZL

; Tri-state to Output HIGH 0.20 2.0 µsCL = 100pF, Fig. 22 & 28 ; S2 closed

PZH

; Output LOW to Tri-state 0.20 2.0 µsCL = 100pF, Fig. 22 & 28 ; S1 closed

PLZ

; Output HIGH to Tri-state 0.15 2.0 µsCL = 100pF, Fig. 22 & 28 ; S2 closed

PHZ

RS-422,/V.11 DRIVERS

; Tri-state to Output LOW 2.80 10.0 µsCL = 100pF, Fig. 22 & 25; S1 closed

PZL

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 22 & 25; S2 closed

PZH

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 22 & 25; S1 closed

PLZ

; Output HIGH to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 22 & 25; S2 closed

PHZ

RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 RECEIVERS

; Tri-state to Output LOW 0.12 2.0 µsCL = 100pF, Fig. 23 & 27 ; S1 closed

PZL

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 23 & 27 ; S2 closed

PZH

; Output LOW to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 23 & 27 ; S1 closed

PLZ

; Output HIGH to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 23 & 27 ; S2 closed

PHZ

RS-422/V.11RECEIVERS

; Tri-state to Output LOW 0.10 2.0 µsCL = 100pF, Fig. 23 & 27; S1 closed

PZL

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 23 & 27; S2 closed

PZH

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 23 & 27; S1 closed

PLZ

; Output HIGH to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 23 & 27; S2 closed

PHZ

Page 6

PINOUT

GND

R1INA

R1INB

R2INA

R2INB

R3INA

R3INB

R4INA

R4INB

R1OUT

4443424140393837363534

R2OUT

ENR4 ENR3 ENR2 ENR1

T4IN T3IN T2IN

T1IN ENT4 ENT3 ENT2

1 2 3 4 5 6 7 8

9 10 11

1213141516171819202122

ENT1

SP526

PIN ASSIGNMENTS

Pin 1 — ENR4 — Enables receiver 4; active high; TTL input.

Pin 2 — ENR3 — Enables receiver 3; active high; TTL input.

R3OUT

R4OUT

T4OUT

T3OUTA

T3OUTB

T2OUTA

T2OUTB

T1OUTA

T1OUTB

GND

C2-

C1-

C2+

GND

C1+

Pin 8 — T1IN — TTL input; transmit data source for DRA1 and DRB1 outputs.

Pins 9 — ENT4 — Enables driver 4, active low; TTL input.

Pin 3 — ENR2 — Enables receiver 2; active high; TTL input.

Pin 4 — ENR1 — Enables receiver 1; active high; TTL input.

Pin 5 — T4IN — TTL input; transmit data source for DRA4 and DRB4 outputs.

Pin 6 — T3IN — TTL input; transmit data source for DRA3 and DRB3 outputs.

Pin 7 — T2IN — TTL input; transmit data

Pins 10 — ENT3 — Enables driver 3, active low; TTL input.

Pins 11 — ENT2 — Enables driver 2, active low; TTL input.

Pins 12 — ENT1 — Enables driver 1, active low; TTL input.

Pins 13 — D1 — Transmitter and receiver decode register; configures transmitter and receiver modes; TTL inputs.

source for DRA2 and DRB2 outputs.

Page 7

Pins 14 — D0 — Transmitter and receiver decode register; configures transmitter and receiver modes; TTL inputs.

Pin 15 — VSS — –10V Charge Pump Capacitor — Connects from ground to VSS. Suggested capacitor size is 1.0µF, 16V.

Pin 16 — C Connects from C size is 1.0µF, 16V.

Pin 17 — C Connects from C size is 1.0µF, 16V.

–

— Charge Pump Capacitor —

–

to C

–

— Charge Pump Capacitor —

. Suggested capacitor

–

to C

. Suggested capacitor

Pin 18 — GND — Ground. Pin 19 — C

Connects from C size is 1.0µF, 16V.

— Charge Pump Capacitor —

–

to C

. Suggested capacitor

Pin 20 — VDD — +10V Charge Pump Capacitor — Connects from VDD to VCC. Suggested capacitor size is 1.0µF, 16V.

Pin 21 — C Connects from C size is 1.0µF, 16V.

— Charge Pump Capacitor —

–

to C

. Suggested capacitor

Pin 22 — VCC — +5V input. Pin 23 — GND — Ground. Pin 24 — T1OUTB — Analog Out — Send

data, non-inverted; sourced from TIN1. Pin 25 — T1OUTA — Analog Out — Send

data, inverted; sourced from TIN1.

Pin 31 — VCC — +5V input. Pin 32 — R4OUT — TTL output; sourced from

RINA4 and RINB4 inputs. Pin 33 — R3OUT — TTL output; sourced from

RINA3 and RINB3 inputs. Pin 34 — R2OUT — TTL output; sourced from

RINA2 and RINB2 inputs. Pin 35 — R1OUT — TTL output; sourced from

RINA1 and RINB1 inputs. Pin 36 — R4INB — Non-inverted analog input

to receiver 4. Pin 37 — R4INA — Inverted analog input to

receiver 4. Pin 38 — R3INB — Non-inverted analog input

to receiver 3. Pin 39— R3INA — Inverted analog input to

receiver 3. Pin 40 — R2INB — Non-inverted analog input

to receiver 2. Pin 41 — R2INA — Inverted analog input to

receiver 2. Pin 42 — R1INB — Non-inverted analog input

to receiver 1. Pin 43 — R1INA — Inverted analog input to

receiver 1. Pin 44 — GND — Ground.

Pin 26 — T2OUTB — Analog Out — Send data, non-inverted; sourced from TIN2.

Pin 27 — T2OUTA — Analog Out — Send data, inverted; sourced from TIN2.

Pin 28 — T3OUTB — Analog Out — Send data, non-inverted; sourced from TIN3.

Pin 29 — T3OUTA — Analog Out — Send data, inverted; sourced from TIN3.

Pin 30 — T4OUT — Analog Out — Send data, inverted; sourced from TIN4.

Page 8

TEST CIRCUITS

3kΩ

Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage

Oscilloscope

7kΩ

Scope used for slew rate measurement.

Figure 3. V.28 Driver Output Slew Rate

VCC = 0V

Figure 5. V.28 Driver Output Power-Off Impedance

±2V

Figure 4. V.28 Driver Output Short-Circuit Current

3kΩ

2500pF

Oscilloscope

Figure 6. Driver Output Rise/Fall Times

Page 9

±15V

Figure 7. V.28 Receiver Input Impedance

3.9kΩ

Figure 9. V.10 Driver Output Open-Circuit Voltage

Figure 8. V.28 Receiver Input Open Circuit Bias

450Ω

Figure 10. V.10 Driver Output Test Terminated Voltage

= 0V

±0.25V

Figure 12. V.10 Driver Output Power-Off CurrentFigure 11. V.10 Driver Output Short-Circuit Current

Page 10

450Ω

Figure 13. V.10 Driver Output Transition Time

50Ω

Oscilloscope

OCA

3.9kΩ

OCB

Figure 14. V.11 Driver Output Open-Circuit Voltage

Figure 15. V.11 Driver Output Test Terminated Voltage Figure 16. V.11 Driver Output Short-Circuit Current

Page 11

= 0V

±0.25V

= 0V

±10V

±0.25V

Figure 17. V.11 Driver Output Power-Off Current

50Ω

Oscilloscope

50Ω

±10V

Figure 18. V.11 Receiver Input Current

V.11 RECEIVER

+3.25mA

–3V–10V

+10V+3V

Maximum Input Current versus V oltage

–3.25mA

Figure 19. V.11 Driver Output Rise/Fall Time

Figure 20. V.11 Receiver Input IV Graph

Page 12

15pF

Output

Under

Test

500Ω

Figure 21. Driver/Receiver Timing Test Circuit

Receiver

Output

Test Point

1KΩC

1KΩ

Figure 23. Receiver Timing Test Load Circuit

+3V

DRIVER INPUT

DRIVER

OUTPUT

DIFFERENTIAL

OUTPUT

= |t

SKEW

DPLH

– V

- t

DPHL

–

Figure 22. Driver Timing Test Load Circuit

f = 1MHz; tR ≤ 10ns; tF ≤ 10ns

1.5V 1.5V t

PLH

1/2V

DPHL

PHL

DPLH

1/2V

Figure 24. Driver Propagation Delays

f = 1MHz; tR < 10ns; tF < 10ns

1.5V t

2.3V

Output normally LOW

Output normally HIGH

1.5V

0.5V

X or T

DEC

DX or TX_Enable

A, B

+3V

x_Enable

0V 5V

Figure 25. V.11 Driver Enable and Disable Times

Page 13

OD2

A – B

RECEIVER OUT

SKEW

= |t

PHL

- t

OD2

PLH

–

PLH

Figure 26. Receiver Propagation Delays

f = 1MHz; tR ≤ 10ns; tF ≤ 10ns

0V 0V

50%

INPUT

OUTPUT

PHL

50%

+3V

DEC

D0 or D1

0V 5V

RECEIVER OUT

Figure 27. Receiver Enable and Disable Times

OUT

+3V

OL(MIN)

0.5V

or ENT

f = 1MHz; tR ≤ 10ns; tF ≤ 10ns

1.5V 1.5V t

50%

Output normally LOW

Output normally HIGH

f = 60kHz; tR < 10ns; tF < 10ns

1.5V t

Output LOW

1.5V

0.5V

f = 60kHz; tR < 10ns; tF < 10ns

1.5V

Output HIGH

1.5V t

0.5V

DX or ENT

+3V

OH(MIN)

OUT

0.5V

Figure 28. V.28 (RS-232) and V.10 Driver Enable and Disable Times

Page 14

1.0µF

C1+

C1–

C2+

C2–

T1IN

ENT1

T2IN

ENT2

T3IN

ENT3

T4IN

ENT4

R1OUT

ENR1

R2OUT

ENR2

R3OUT

ENR3

R4OUT

1.0µF

+5V

SP526

1.0µF

T1OUTA

T1OUTB

T2OUTA

T2OUTB

T3OUTA

T3OUTB

T4OUT

R1INA

R1INB

R2INA

R2INB

R3INA

R3INB

R4INA

R4INB

1.0µF

ENR4

GND

14 D0

Figure 29. Typical Operating Circuit for the SP526

Page 15

FEATURES

THEORY OF OPERATION

The SP526 contains highly integrated serial transceivers that offer programmability between interface modes through software control. The SP526 offers the hardware interface modes for RS-232 (V.28), RS-423 (V.10), RS-422 (V.11), and RS-485. The interface mode selection is done via two control pins.

The SP526 has four drivers, four receivers, and an on-board charge pump that is ideally suited for low-cost wide area network connectivity and other multi-protocol applications. Based on our multi-mode SP500 family, Sipex has allocated specific transceiver cells, or "building blocks," from this product series and created the SP526. Sipex's "building blocks" concept allows these small transceiver cells to be packaged to offer a simple low-cost solution to networking applications that need only 4 interface modes. For example, an 8-channel applications requiring eight serial transceivers can be achieved implementing two SP526 devices. The SP526 can be implemented in series with other devices in our SP500 family. A 9-channel network application can be achieved implementing the SP505 which contains seven transceivers in conjunction with the SP526.

The SP526 device is made up of 1) the drivers,

2) the receivers, and 3) a charge pump.

Drivers

The SP526 has four enhanced independent drivers. Control for the mode selection is done via a two–bit control word into DP0 and DP1. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. The mode of each driver in the different interface modes that can be selected is shown in Table 1.

There are four basic types of driver circuits — RS-232 (V.28), RS-423 (V.10), RS-422 (V.11), and RS-485.

The RS-232 (V.28) drivers output single–ended signals with a minimum of ±5V (with 3KΩ & 2500pF loading), and can operate to at least 120Kbps. Since the SP526 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed ±10V.

The RS-423 (V.10) drivers are also single– ended signals which produce open circuit V and VOH measurements of ±4.0V to ±6.0V.

When terminated with a 450Ω load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance

SREVIRDSREVIECER

1D0D

1T2T3T4T1R2R3R4R

00 edoMetatS-irTnistuptuOxRdnaxT-NWODTUHS 01 11.V11.V11.V01.V11.V11.V11.V11.V

10 11.V11.V01.V01.V11.V11.V11.V11.V 11 82.V82.V82.V82.V82.V82.V82.V82.V

Table 1. SP526 Driver and Receiver Mode Selection with the Control Lines D1 and D0

Page 16

of the ITU V.10 specification. The RS-423 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category II signals from each of their corresponding specifications.

The third and fourth type of drivers are RS-422 (V.11)/RS-485 type differential drivers. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to singleended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain RS-485, ±1.5V differential output levels with a worst case load of 54Ω. The signal levels and drive capability of these drivers allow the drivers to also support RS-422 (V.11) requirements of ±2V differential output levels with 100Ω loads. The driver is designed to operate over a common mode range of +7V to -7V which follows the V.11 specification. The RS-422 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data. All of the differential drivers can operate to at least 10Mbps.

The drivers also have separate enable pins which simplifies half-duplex configurations for some applications and also provides simpler DTE/ DCE flexibility with one integrated circuit. The enable pins will tri-state the drivers when the ENT1, ENT2, ENT3, and ENT4 pins are at a logic HIGH ("1"). During tri-stated conditions, the driver outputs will be at a high impedance state.

The driver inputs are both TTL or CMOS compatible. Each driver input should have a pulldown or pull-up resistor so that the output will be at a defined state. Unused driver inputs should have pull-up resistors to +5V connected so that the output is at a logic LOW ("0"). Unused driver inputs should not be left floating. For differential drivers, the non-inverting output will be at a logic HIGH ("1"). The typical pull-up resistor value should be 400kΩ.

Receivers

The SP526 has four independent receivers which can be programmed for the different interface modes. Control for the mode selection is done via a two–bit control word that is the same as the driver control word. Therefore, if the modes for the drivers and receivers are supposed to be identical in the application, the control lines can be tied together.

Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface protocols of the receivers. Table 1 shows the mode of each receiver in the different interface modes that can be selected.

There are two basic types of receiver circuits — RS-232 (V.28) and RS-422 (V.11).

The RS-232 (V.28) receiver is single–ended and accepts RS-232 signals from the RS-232 driver. The RS-232 receiver has an operating voltage range of ±15V and can receive signals downs to ±3V. The input sensitivity complies with RS232 and V.28 at ±3V. The input impedance is 3kΩ to 7kΩ in accordance to RS-232 and V.28. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic "1" and a +0.8V maximum for a logic "0". RS-232(V.28) receivers can be used in RS-232 mode for data, clock or control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The RS-232 receivers can operate to at least 120kbps.

Page 17

The third type of receiver is a differential which supports RS-422/V.11 signals. This receiver has a typical input impedance of 10KΩ and a differential threshold of ±0.3V, which complies with the RS-422/V.11 specifications. Since the characteristics of the RS-422 (V.11) receivers are actually subsets of RS-485, the RS-422/ V.11 receivers can accept RS-485 signals. However, these receivers cannot support 32 transceivers on the signal bus due to the lower input impedance as specified in the RS-485 specifications. V.11 receivers are used in RS-422, RS-449, EIA-530, EIA-530A and V.36 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential receivers can receive signals up to at least 10Mbps.

All four receivers include an enable line for tri-state of the receiver output allowing convenient half-duplex configurations. When the enable lines are at a logic LOW ("0") active, the receiver outputs are high impedance and will be at approximately 10kΩ during tri-state.

All receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open. For single-ended RS-232 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high ("1") at the receiver outputs. The single-ended RS-423 receivers produce a logic LOW ("0") on the output when the inputs are open. This is due to a pull-up device connected to the input. The differential receivers have the same internal pull-up device on the non-inverting input which produces a logic HIGH ("1") at the receiver output.

Charge Pump

The charge pump is a Sipex–patented design (U.S. 5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 10V power supplies. There is a free–running oscillator that controls the four phases of the voltage shifting. A description of each phase follows.

Phase 1

— VSS charge storage —During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to +5V. C then switched to ground and the charge in C transferred to C +5V, the voltage potential across capacitor C2 is

–

. Since C

is connected to

–

now 10V.

Phase 2

— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the V storage capacitor and the positive terminal of C

to ground, and transfers the generated –l0V to C3. Simultaneously, the positive side of capacitor C 1 is switched to +5V and the negative side is connected to ground.

Phase 3

— VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –5V in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C voltage potential across C2 is l0V.

is at +5V, the

VCC = +5V

+5V

–5V –5V

Figure 30. Charge Pump — Phase 1

––

–

Storage Capacitor

–

Storage Capacitor

Page 18

Figure 31. Charge Pump — Phase 2

+10V

a) C

GND

–

b) C

–10V

VCC = +5V

––

–10V

–

Storage Capacitor

–

Storage Capacitor

Figure 32. Charge Pump Waveforms

Figure 33. Charge Pump — Phase 3

Figure 34. Charge Pump — Phase 4

VCC = +5V

+5V

–5V

––

–5V

VCC = +5V

+10V

––

–

Storage Capacitor

–

Storage Capacitor

–

Storage Capacitor

–

Storage Capacitor

Page 19

Phase 4

— VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers the generated l0V across C2 to C4, the VDD storage capacitor. Again, simultaneously with this, the positive side of capacitor C1 is switched to +5V and the negative side is connected to ground, and the cycle begins again.

Since both V+ and V– are separately generated from VCC; in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

The clock rate for the charge pump typically operates at 15kHz. The external capacitors can be as low as 1.0µF with a 16V breakdown voltage rating.

ESD Tolerance

The SP526 device incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least ±15kV without damage nor latch-up.

There are different methods of ESD testing applied:

a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact

The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 35. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently.

The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. The transceiver IC receives most

SW1

SW1SW1

DC Power Source

Figure 35. ESD Test Circuit for Human Body Model

SW2

SW2SW2

Device

Under T est

Page 20

Contact-Discharge Module

Contact-Discharge ModuleContact-Discharge Module

SW1

SW1SW1

DC Power Source

Figure 36. ESD Test Circuit for IEC1000-4-2

of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 36. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method.

With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD

RS and RV add up to 330Ω for IEC1000-4-2.

andand RR

S S

I ➙

30A

15A

Figure 37. ESD Test Waveform for IEC1000-4-2

SW2

SW2SW2

add up to 330add up to 330ΩΩ f for IEC1000-4-2.or IEC1000-4-2.

V V

t=0ns t=30ns

t ➙

Device Under Test

Device Pin Human Body IEC1000-4-2

Tested Model Air Discharge Direct Contact Level

Driver Outputs ±15kV ±15kV ±8kV 4 Receiver Inputs ±15kV ±15kV ±8kV 4

Table 2. Transceiver ESD Tolerance Levels

Page 21

potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed.

The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC.

The circuit models in Figures 35 and 36 represent the typical ESD testing circuits used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage.

For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are

1.5kΩ an 100pF, respectively. For IEC-1000-42, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively.

The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point.

NET1/NET2 European Compliancy

As with all of Sipex's previous multi-protocol serial transceiver ICs, the drivers and receivers have been designed to meet all the requirements to NET1/NET2. The SP526 is also tested and adheres to all the NET1/2 physical layer testing and the ITU Series V specifications. Please note that although the SP526, as with its predecessors, adheres to NET1/2 testing, any complex or unusual configuration should be double-checked to ensure NET compliance. Consult the factory for details.

Page 22

PACKAGE:

44-PIN LQFP

D D

0.30" RAD. TYP.

0.20" RAD. TYP.

-A-

-B-

Standoff

Lead

Coplanarity

ccc C

Seating

Plane

-C-

13˚ TYP.

6°±4°

.25

-DE

0.17 MAX.

ø L

13˚ TYP.

FOOTPRINT

DIMENSIONS

A A A

D D

ddd

ccc

1 2

(BODY +)

MAX.

MIN.

+0.05/-0.05

BASIC BASIC BASIC BASIC

+0.15/-0.15

BASIC

±0.05 MAX. NOM. NOM.

Another variation of Pin 1 Visual Aid

2.0 mm 44L

1.60

0.05

1.40

12.00

10.00

12.00

10.00

0.60

0.80

0.35

7°

0.10

0.20

Page 23

Model Temperature Range Package Types

ORDERING INFORMATION

SP526CF ........................................................................... 0°C to +70°C ............................................................................... 44–pin JEDEC LQFP

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP526CF Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual