Datasheet SP508CF Datasheet (Sipex Corporation)

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Page 1

SP508

Rugged 40Mbps, 8 Channel Multiprotocol Transceiver

with Programmable DCE/DTE and Termination Resistors

■ Fast 40Mbps Differential Transmission Rates

■ Improved ESD Tolerance for Analog I/Os

■ Internal Transceiver Termination Resistors for

V.11 and V.35

■ Interface Modes: ✓ RS-232 (V.28) ✓ EIA-530 (V.10 & V.11) ✓ X.21 (V.11) ✓ EIA-530A (V.10 & V.11) ✓ RS-449/V.36 (V.10 & V.11) ✓ V.35

■ Protocols are Software Selectable with 3-Bit

Word

■ Eight (8) Drivers and Eight (8) Receivers

■ Termination Network Disable Option

■ Internal Line or Digital Loopback for Diagnostic

Testing

■ Adheres to NET1/NET2 and TBR-2 Compliancy Requirements

■ Easy Flow-Through Pinout

■ +5V Only Operation

■ Individual Driver and Receiver Enable/Disable Controls

■ Operates in either DTE or DCE Mode

DESCRIPTION

The SP508 is a monolithic device that supports eight (8) popular serial interface standards for Wide Area Network (WAN) connectivity. The SP508 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex regulated charge pump allowing +5V only operation. Sipex's patented charge pump provides a regulated output of +5.8V, which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. The SP508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than four capacitors used for the internal charge pump. All necessary termination is integrated within the SP508 and is switchable when V.35 drivers and V.35 receivers, or when V.11 receivers are used. The SP508 provides the controls and transceiver availability for operating as either a DTE or DCE.

Additional features with the SP508 include internal loopback that can be initiated in any of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. The SP508 also includes a latch enable pin with the driver and receiver address decoder. The internal V.11 or V.35 termination can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and receivers in the SP508 include separate enable pins for added convenience. The SP508 is ideal for WAN serial ports in networking equipment such as routers, access concentrators, network muxes, DSU/CSU's, networking test equipment, and other access devices.

Applicable U.S. Patents-5,306,954; and others patents pending

PRELIMINARY INFORMATION

Page 2

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VCC................................................................................................ +7V

Input Voltages:

Output Voltages:

Storage Temperature ................................................ -65°C to +150°C

Power Dissipation ................................................................. 1520mW

(derate 19.0mW/°C above +70°C)

Logic ................................................-0.3V to (VCC+0.5V)

Drivers .............................................-0.3V to (VCC+0.5V)

Receivers ........................................................... ±15.5V

Logic ................................................-0.3V to (VCC+0.5V)

Drivers ................................................................... ±15V

Receivers ........................................ -0.3V to (VCC+0.5V)

STORAGE CONSIDERATIONS

Due to the relatively large package size of the 100-pin quad flatpack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order to remove moisture prior to soldering. Sipex ships the 100-pin LQFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.

Package Derating:

.................................................................................................................

....................................................................................................................

52.7 °C/W

6.5 °C/W

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

LOGIC INPUTS

2.0 Volts

LOGIC OUTPUTS

2.4 Volts I

V.28 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±15 Volts per Loaded Voltage ±5.0 ±15 Volts per Short-Circuit Current ±100 mA per Power-Off Impedance 300 Ω per

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 1.5 µs per Instantaneous Slew Rate 30 V/µs per Propagation Delay

PHL

PLH

Max.Transmission Rate 120 230 kbps

0.5 1 5 µs

0.8 Volts

0.4 Volts I

= –3.2mA

OUT

= 1.0mA

OUT

Figure 1 Figure 2 Figure 4 Figure 5

Figure 6 Figure 3

; +3V to -3V

V.28 RECEIVER

DC Parameters

Inputs

Input Impedance 3 7 kΩ per Open-Circuit Bias +2.0 Volts per

Figure 7 Figure 8

HIGH Threshold 1.7 3.0 Volts LOW Threshold 0.8 1.2 Volts

AC Parameters VCC = +5V for AC parameters

Propagation Delay

t t

PHL PLH

50 100 500 ns 50 100 500 ns

PRELIMINARY INFORMATION

Page 3

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

V.28 RECEIVER (continued)

AC Parameters (cont.)

Max.Transmission Rate 120 230 kbps

V.10 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±4.0 ±6.0 Volts per Test-Terminated Voltage 0.9V Short-Circuit Current ±150 mA per Power-Off Current ±100 µA per

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 200 ns per Propagation Delay

PHL

PLH

Max.Transmission Rate 120 kbps

30 100 500 ns 30 100 500 ns

Volts per

V.10 RECEIVER

DC Parameters

Inputs

Input Current –3.25 +3.25 mA per Input Impedance 4 kΩ Sensitivity ±0.3 Volts

AC Parameters VCC = +5V for AC parameters

Propagation Delay

PHL

PLH

Max.Transmission Rate 120 kbps

50 ns 50 ns

V.11 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±6.0 Volts per Test Terminated Voltage ±2.0 Volts per

Balance ±0.4 Volts per Offset +3.0 Volts per Short-Circuit Current ±150 mA per Power-Off Current ±100 µA per

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 10 ns per Propagation Delay Using CL = 50pF;

PHL

PLH

Differential Skew 10 ns per Max.Transmission Rate 40 Mbps

0.5V

0.67V

30 50 ns per 30 50 ns per

Volts

Figure 9 Figure 10 Figure 11 Figure 12

Figure 13

Figures 14

Figure 16 Figure 17

Figure 17 Figure 17 Figure 18 Figure 19

Figures 21 Figures 33

Figures 33 Figures 33

; 10% to 90%

and

and 36; 10% to 90% and

and

V.11 RECEIVER

DC Parameters

Inputs

Common Mode Range –7 +7 Volts Sensitivity ±0.2 Volts

PRELIMINARY INFORMATION

Page 4

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

V.11 RECEIVER (continued)

DC Parameters (cont.)

Input Current –3.25 ±3.25 mA per Current w/ 100Ω Termination ±60.75 mA per

Input Impedance 4 kΩ

AC Parameters VCC = +5V for AC parameters

Propagation Delay Using CL = 50pF; t

PHL

PLH

Skew 5 ns per Max.Transmission Rate 40 Mbps

30 50 ns per 30 50 ns per

V.35 DRIVER

DC Parameters

Outputs

Test Terminated Voltage ±0.44 ±0.66 Volts per Offset ±0.6 Volts per Output Overshoot -0.2V Source Impedance 50 150 Ω per Short-Circuit Impedance 135 165 Ω per

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 7 20 ns per Propagation Delay

PHL

PLH

Differential Skew 5 ns per Max.Transmission Rate 40 Mbps

+0.2V

30 50 ns per 30 50 ns per

Volts per

Figure 20

power on or off

Figure 23

Figures 33 Figures 33 Figure 33

Figure 25 Figure 25 Figure 25 Figure 27 Figure 28

Figure 29 Figures 33

Figures 33 Figures 33

and 22; and

and 38 and

; V

ST = Steady state value

; ZS = V2/V1 x 50

; 10% to 90%

and 36; CL = 20pF and 36; CL = 20pF and 36; CL = 20pF

V.35 RECEIVER

DC Parameters

Inputs

Sensitivity ±50 +100 mV Source Impedance 90 110 Ω per Short-Circuit Impedance 135 165 Ω per

AC Parameters VCC = +5V for AC parameters

Propagation Delay t

PHL

PLH

Skew 3 ns per Max.Transmission Rate 40 Mbps

30 50 ns per 30 50 ns per

Figure 30 Figure 31

Figures 33 Figures 33 Figure 33

; ZS = V2/V1 x 50Ω

and 38; CL = 20pF and 38; CL = 20pF

; CL = 20pF

TRANSCEIVER LEAKAGE CURRENTS

Driver Output 3-State Current 100 500 µA per Figure 32; Drivers disabled Rcvr Output 3-State Current 1 10 µATX & RX disabled, 0.4V - VO - 2.4V

POWER REQUIREMENTS

ICC (Shutdown Mode) 1 µA All ICC values are with VCC = +5V

(V.28/RS-232) 95 mA fIN = 120kbps; Drivers active & loaded (V.11/RS-422) 230 mA fIN = 10Mbps; Drivers active & loaded (EIA-530 & RS-449) 270 mA fIN = 10Mbps; Drivers active & loaded (V.35) 170 mA V.35 @ fIN = 10Mbps, V.28 @ 20kbps (EIA-530A) 200 mA fIN = 10Mbps; Drivers active & loaded

4.75 5.00 5.25 Volts

PRELIMINARY INFORMATION

Page 5

OTHER AC CHARACTERISTICS

TA = +25°C and VCC = +5.0V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28

; Tri-state to Output LOW 0.11 5.0 µsC

PZL

; Tri-state to Output HIGH 0.11 2.0 µsC

PZH

; Output LOW to Tri-state 0.05 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.05 2.0 µsC

PHZ

RS-423/V.10

; Tri-state to Output LOW 0.07 2.0 µsC

PZL

; Tri-state to Output HIGH 0.05 2.0 µsC

PZH

; Output LOW to Tri-state 0.55 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.12 2.0 µsC

PHZ

RS-422/V.11

; Tri-state to Output LOW 0.04 10.0 µsC

PZL

; Tri-state to Output HIGH 0.05 2.0 µsC

PZH

; Output LOW to Tri-state 0.03 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.11 2.0 µsC

PHZ

V.35

; Tri-state to Output LOW 0.85 10.0 µsC

PZL

; Tri-state to Output HIGH 0.36 2.0 µsC

PZH

; Output LOW to Tri-state 0.06 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.05 2.0 µsC

PHZ

RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28

; Tri-state to Output LOW 0.05 2.0 µsC

PZL

; Tri-state to Output HIGH 0.05 2.0 µsC

PZH

; Output LOW to Tri-state 0.65 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.65 2.0 µsC

PHZ

RS-423/V.10

; Tri-state to Output LOW 0.04 2.0 µsC

PZL

; Tri-state to Output HIGH 0.03 2.0 µsC

PZH

; Output LOW to Tri-state 0.03 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.03 2.0 µsC

PHZ

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 37; S

closed

= 100pF, Fig. 34 & 37; S

closed

= 15pF, Fig. 34 & 37; S

closed

= 15pF, Fig. 34 & 37; S

closed

= 100pF, Fig. 34 & 37; S

closed

= 100pF, Fig. 34 & 37; S

closed

= 15pF, Fig. 34 & 37; S

closed

= 15pF, Fig. 34 & 37; S

closed

= 100pF, Fig. 35 & 40; S

closed

= 100pF, Fig. 35 & 40; S

closed

= 100pF, Fig. 35 & 40; S

closed

= 100pF, Fig. 35 & 40; S

closed

= 100pF, Fig. 35 & 40; S

closed

= 100pF, Fig. 35 & 40; S

closed

= 100pF, Fig. 35 & 40; S

closed

= 100pF, Fig. 35 & 40; S

closed

PRELIMINARY INFORMATION

Page 6

OTHER AC CHARACTERISTICS (Continued)

TA = +25°C and VCC = +5.0V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-422/V.11

; Tri-state to Output LOW 0.04 2.0 µsC

PZL

; Tri-state to Output HIGH 0.03 2.0 µsC

PZH

; Output LOW to Tri-state 0.03 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.03 2.0 µsC

PHZ

V.35

; Tri-state to Output LOW 0.04 2.0 µsC

PZL

; Tri-state to Output HIGH 0.03 2.0 µsC

PZH

; Output LOW to Tri-state 0.03 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.03 2.0 µsC

PHZ

TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 32, 33, 36, 38) RS-232 Driver 100 ns [ (t

100 ns [ (t

RS-232 Receiver 20 ns [ (t

20 ns [ (t

RS-422 Driver 2 ns [ (t

2ns[ (t

RS-422 Receiver 2 ns [ (t

3ns[ (t

RS-423 Driver 5 ns [ (t

5ns[ (t

RS-423 Receiver 5 ns [ (t

5ns[ (t

V.35 Driver 2 ns [ (t

2ns[ (t

V.35 Receiver 2 ns [ (t

2ns[ (t

= 100pF, Fig. 35 & 39; S

closed

= 100pF, Fig. 35 & 39; S

closed

= 15pF, Fig. 35 & 39; S

closed

= 15pF, Fig. 35 & 39; S

closed

= 100pF, Fig. 35 & 39; S

closed

= 100pF, Fig. 35 & 39; S

closed

= 15pF, Fig. 35 & 39; S

closed

= 15pF, Fig. 35 & 39; S

closed

)

– (t

phl

Tx1

)

– (t

plh

Tx1

)

– (t

phl

Rx1

)

– (t

phl

Rx1

)

– (t

phl

Tx1

)

– (t

plh

Tx1

)

– (t

phl

Rx1

)

– (t

phl

Rx1

)

– (t

phl

Tx2

)

– (t

plh

Tx2

)

– (t

phl

Rx2

)

– (t

phl

Rx2

)

– (t

phl

Tx1

)

– (t

plh

Tx1

)

– (t

phl

Rx1

)

– (t

phl

Rx1

)

]

phl

Txn

)

]

plh

Txn

)

]

phl

Rxn

)

]

phl

Rxn

)

]

phl

Txn

)

]

plh

Txn

)

]

phl

Rxn

)

]

phl

Rxn

)

]

phl

Txn

)

]

plh

Txn

)

]

phl

Rxn

)

]

phl

Rxn

)

]

phl

Txn

)

]

plh

Txn

)

]

phl

Rxn

)

]

phl

Rxn

PRELIMINARY INFORMATION

Page 7

TEST CIRCUITS

3kΩ

Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage

Oscilloscope

7kΩ

Scope used for slew rate measurement.

Figure 3. V.28 Driver Output Slew Rate

VCC = 0V

Figure 5. V.28 Driver Output Power-Off Impedance

±2V

Figure 4. V.28 Driver Output Short-Circuit Current

3kΩ

2500pF

Oscilloscope

Figure 6. V.28 Driver Output Rise/Fall Times

PRELIMINARY INFORMATION

Page 8

±15V

Figure 7. V.28 Receiver Input Impedance

3.9kΩ

Figure 9. V.10 Driver Output Open-Circuit Voltage

Figure 8. V.28 Receiver Input Open Circuit Bias

450Ω

Figure 10. V.10 Driver Output Test Terminated Voltage

= 0V

±0.25V

Figure 12. V.10 Driver Output Power-Off CurrentFigure 11. V.10 Driver Output Short-Circuit Current

PRELIMINARY INFORMATION

Page 9

450Ω

Oscilloscope

±10V

Figure 13. V.10 Driver Output Transition Time

V.10 RECEIVER

+3.25mA

-3V-10V +10V+3V

Maximum Input Current versus V oltage

-3.25mA

Figure 15. V.10 Receiver Input IV Graph

Figure 14. V.10 Receiver Input Current

OCA

3.9kΩ

OCB

Figure 16. V.11 Driver Output Open-Circuit Voltage

50Ω

Figure 17. V.11 Driver Output Test Terminated Voltage Figure 18. V.11 Driver Output Short-Circuit Current

PRELIMINARY INFORMATION

Page 10

= 0V

±0.25V

±10V

= 0V

Figure 19. V.11 Driver Output Power-Off Current

±0.25V

Figure 20. V.11 Receiver Input Current

±10V

Oscilloscope

50Ω

V.11 RECEIVER

+3.25mA

-3V-10V +10V+3V

Maximum Input Current versus V oltage

-3.25mA

Figure 21. V.11 Driver Output Rise/Fall Time

Figure 22. V.11 Receiver Input IV Graph

PRELIMINARY INFORMATION

Page 11

100Ω to 150Ω

±6V

i [mA] = (V [V] - 3) / 4.0

V.11 RECEIVER

w/ Optional Cable Termination

(100ohms to 150ohms)

i [mA] = V [V] / 0.1

-3V-6V +6V+3V

i [mA] = (V [V] - 3) / 4.0

Maximum Input Current versus Voltage

Figure 24. V.11 Receiver Input Graph w/ Termination

100Ω to 150Ω

±6V

50Ω

Figure 23. V.11 Receiver Input Current w/ Termination

50Ω

Figure 26. V.35 Driver Output Offset Voltage

Figure 25. V.35 Driver Output Test Terminated Voltage

50Ω

24kHz, 550mV

Sine Wave

Figure 27. V.35 Driver Output Source Impedance

p-p

PRELIMINARY INFORMATION

Page 12

50Ω

Oscilloscope

±2V

50Ω

Figure 28. V.35 Driver Output Short-Circuit Impedance

50Ω

24kHz, 550mV

p-p

Sine Wave

Figure 30. V.35 Receiver Input Source Impedance

Figure 29. V.35 Driver Output Rise/Fall Time

±2V

Figure 31. V.35 Receiver Input Short-Circuit Impedance

Any one of the three conditions for disabling the driver.

00 0

VCC = 0V

Logic “1”

Figure 32. Driver Output Leakage Current Test

DEC

ZSC

±12V

A B

OUT

15pF

Figure 33. Driver/Receiver Timing Test Circuit

PRELIMINARY INFORMATION

Page 13

Output

Under

Test

500Ω

Receiver

Output

Test Point

1KΩC

1KΩ

Figure 34. Driver Timing Test Load Circuit

– V

+3V

A B

–

DRIVER

INPUT

DRIVER

OUTPUT

DIFFERENTIAL

OUTPUT

SKEW = | tDPLH - tDPHL

Figure 36. Driver Propagation Delays

+3V

Mx or Tx_Enable

0V 5V

A, B

Figure 35. Receiver Timing Test Load Circuit

f > 10MHz; tR < 10ns; tF < 10ns

1.5V 1.5V t

PLH

1/2V

DPLH

PHL

DPHL

1.5V 1.5V t

2.3V

Output normally LOW

Output normally HIGH

0.5V

1/2V

Figure 37. Driver Enable and Disable Times

f > 10MHz; tR < 10ns; tF < 10ns

A – B

RECEIVER OUT

= |

PHL

SKEW

0D2

–

0D2

PLH

0V 0V

INPUT

OUTPUT

(VOH - VOL)/2

PHL

- VOL)/2

Figure 38. Receiver Propagation Delays

PRELIMINARY INFORMATION

Page 14

_ENABLE

RECEIVER OUT

Figure 39. Receiver Enable and Disable Times

+3V

0V 5V

f = 1MHz; tR < 10ns; tF < 10ns

1.5V 1.5V t

1.5V

Output normally LOW

Output normally HIGH

0.5V

+3V

f = 60kHz; tR < 10ns; tF < 10ns

Tx_Enable

1.5V

OUT

- 0.5V Output LOW

f = 60kHz; tR < 10ns; tF < 10ns

+3V

Tx_Enable

1.5V

OUT

VOH - 0.5V

Output HIGH

Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times

1.5V t

VOH - 0.5V

- 0.5V

PRELIMINARY INFORMATION

Page 15

Figure 41. Typical V.28 Driver Output Waveform

Figure 43. Typical V.11 Driver Output Waveform Figure 44. Typical V.35 Driver Output Waveform

Figure 42. Typical V.10 Driver Output Waveform

PRELIMINARY INFORMATION

Page 16

PINOUT

Pin 19 — D0 — Mode Select Input. Pin 20 — D1 — Mode Select Input. Pin 21 — D2 — Mode Select Input. Pin 22 — TERM_OFF — Termination

Disable Input. Pin 23 — D_LATCH — Decoder Latch Input. Pin 24 — N/C — No Connection. Pin 25 — GND — Signal Ground. Pin 26 — VCC — +5V Power Supply Input. Pin 27—LOOPBACK—Loopback Mode

Enable Input. Pin 28 — TXD — TXD Driver TTL Input. Pin 29 — TXCE — TXCE Driver TTL Input.

VCC 1 GND

SDEN

TTEN 4 STEN

RSEN 6

TREN 7

RRCEN 8

RLEN 9

LLEN 10

RDEN 11

RTEN 12

TXCEN 13

CSEN 14 DMEN 15

RRTEN 16

ICEN 17

TMEN 18

TERM_OFF 22

D_LATCH 23

N/C 24

GND 25

100 SD(b)

99 V35TGND1

98 VCC

97 SD(a)

96 GND

95 TT(b)

94 V35TGND2

93 VCC

92 TT(a)

91 GND

90 ST(b)

89 V35TGND3

88 VCC

87 ST(a)

86 GND

85 RS(b)

84 VCC

83 RS(a)

82 GND

81 RRC(a)

80 VCC

79 RRC(b)

78 TR(b)

77 VCC

76 N/C

75 TR(a)

RD(a) 48

RT(b) 49

RT(a) 50

74 GND 73 VDD 72 C1+ 71 VCC 70 C2+ 69 C168 GND 67 C266 VSS 65 RL(a) 64 VCC 63 LL(a) 62 TM(a) 61 IC(a) 60 RRT(a) 59 RRT(b) 58 V10GND 57 DM(a) 56 DM(b) 55 CS(a) 54 CS(b) 53 TXC(a) 52 GND 51 TXC(b)

2 3

VCC 26

LOOPBACK 27

TXD 28

TXCE 29

SP508

RL 34

ST 30

RTS 32

DTR

RXD 36

RXC 37

DCD_DCE 33

TXC 38

CTS 39

DSR 40

RI 42

TM 43

DCD_DTE 41

GND 44

VCC 45

RD(b) 47

V35RGND 46

D0 19 D1 20 D2 21

Pin 30 — ST — ST Driver TTL Input.

PIN ASSIGNMENTS

Pin 1 — VCC — +5V Power Supply Input. Pin 2 — GND — Signal Ground. Pin 3 — SDEN — TXD Driver Enable Input.

Pin 31 —RTS — RTS Driver TTL Input. Pin 32 — DTR— DTR Driver TTL Input. Pin 33 — DCD_DCE — DCD

DCE

Driver

TTL Input.

Pin 4 — TTEN — TXCE Driver Enable Input.

Pin 34 — RL — RL Driver TTL Input.

Pin 5 — STEN — ST Driver Enable Input.

Pin 35 — LL — LL Driver TTL Input.

Pin 6 — RSEN — RTS Driver Enable Input.

Pin 36 — RXD — RXD Receiver TTL Output.

Pin 7 — TREN — DTR Driver Enable Input.

Pin 37 — RXC — RXC Receiver TTL Output.

Pin 8 — RRCEN — DCD

Input. Pin 9 — RLEN — RL Driver Enable Input. Pin 10 — LLEN — LL Driver Enable Input. Pin 11 — RDEN — RXD Receiver Enable Input.

Driver Enable

DCE

Pin 38 — TXC — TXC Receiver TTL Output. Pin 39 — CTS — CTS Receiver TTL Output. Pin 40 — DTR — DSR Receiver TTL Output. Pin 41 — DCD_DTE — DCD

TTL Output.

Receiver

DTE

Pin 12 — RTEN — RXT Receiver Enable Input.

Pin 42 — RI — RI Receiver TTL Output.

Pin 13 —TXCEN — TXC Receiver Enable Input.

Pin 43 — TM — TM Receiver TTL Output.

Pin 14 — CSEN — CTS Receiver Enable Input.

Pin 44 — GND — Signal Ground.

Pin 15 — DMEN — DSR Receiver Enable Input. Pin16 — RRTEN — DCD

Enable Input.

Receiver

DTE

Pin 45 — V Pin 46 — V35RGND — Receiver Termination

— +5V Power Supply Input.

Reference.

Pin 17 — ICEN — RI Receiver Enable Input.

Pin 47 — RD(b) — RXD Non-Inverting Input.

Pin 18 — TMEN — TM Receiver Enable Input.

PRELIMINARY INFORMATION

Page 17

Pin 48 — RD(a) — RXD Inverting Input. Pin 49 — RT(b) — RXT Non-Inverting Input. Pin 50 — RT(a) — RXT Inverting Input. Pin 51 — TXC(b) — TXC Non-Inverting Input. Pin 52 — GND — Signal Ground. Pin 53 — TXC(a) — TXC Inverting Input. Pin 54 — CS(b) — CTS Non-Inverting Input. Pin 55 — CS(a) — CTS Inverting Input. Pin 56 — DM(b) — DSR Non-Inverting Input. Pin 57 — DM(a) — DSR Inverting Input. Pin 58 — V10GND — V.10 RX Reference Node. Pin 59 — RRT(b) — DCD

Input. Pin 60 —RRT(a) — DCD Pin 61 — IC(a) — RI Receiver Input. Pin 62 — TM(a) — TM Receiver Input. Pin 63 — LL(a) — LL Driver Output. Pin 64 — VCC — +5V Power Supply Input. Pin 65 — RL(a) — RL Driver Output. Pin 66 — VSS — -2XVCC Charge Pump Output. Pin 67 — C2- — Charge Pump Capacitor. Pin 68 — GND — Signal Ground. Pin 69 — C1- — Charge Pump Capacitor. Pin 70 — C2+ — Charge Pump Capacitor. Pin 71 — VCC — +5V Power Supply Input. Pin 72 — C1+ — Charge Pump Capacitor.

Non-Inverting

DTE

Inverting Input.

DTE

Pin 79 — RRC(b) — DCD

Output. Pin 80 — VCC — +5V Power Supply Input. Pin 81 — RRC(a) — DCD Pin 82 — GND — Signal Ground. Pin 83 — RS(a) — RTS Inverting Output. Pin 84 — VCC — +5V Power Supply Input. Pin 85 — RS(b) — RTS Non-Inverting Output. Pin 86 — GND — Signal Ground. Pin 87 — ST(a) — ST Inverting Output. Pin 88 — VCC — +5V Power Supply Input. Pin 89 — V35TGND3 — ST Termination

Reference. Pin 90 — ST(b) — ST Non-Inverting Output. Pin 91 — GND — Signal Ground. Pin 92 — TT(a) — TXCE Inverting Output. Pin 93 — VCC — +5V Power Supply Input. Pin 94 — V35TGND2 — TXCE Termination

Reference. Pin 95 — TT(b) — TXCE Non-Inverting

Output. Pin 96 — GND — Signal Ground. Pin 97 — SD(a) — TXD Inverting Output. Pin 98 — VCC- — +5V Power Supply Input. Pin 99 — V35TGND1 — TXD Termination

Reference. Pin 100 — SD(b) — TXD Non-Inverting Output.

Non-Inverting

DCE

Inverting Output.

DCE

Pin 73 — VDD — 2XVCC Charge Pump Output. Pin 74 — GND — Signal Ground. Pin 75 — TR(a) — DTR Inverting Output. Pin 76 — N/C — No Connection. Pin 77 — VCC — +5V Power Supply Input. Pin 78 — TR(b) — DTR Non-Inverting Output.

PRELIMINARY INFORMATION

Page 18

SP508 Driver Table

niPtuptuOrevirD edoM53.V

EDOM

)2D,1D,0D(

100 010 110 001 101 011 111 )a(TUO53.V11.V82.V11.V11.V11.VZ-hgiH)a(DxT )b(TUO53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(DxT )a(TUO53.V11.V82.V11.V11.V11.VZ-hgiH)a(ECxT )b(TUO53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(ECxT )a(TUO53.V11.V82.V11.V11.V11.VZ-hgiH)a(ECD_CxT )b(TUO53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(ECD_CxT )a(TUO82.V11.V82.V11.V11.V11.VZ-hgiH)a(STR )b(TUOZ-hgiH11.VZ-hgiH11.V11.V11.VZ-hgiH)b(STR )a(TUO82.V11.V82.V01.V11.V11.VZ-hgiH)a(RTD )b(TUOZ-hgiH11.VZ-hgiHZ-hgiH11.V11.VZ-hgiH)b(RTD )a(TUO82.V11.V82.V11.V11.V11.VZ-hgiH)a(ECD_DCD )b(TUOZ-hgiH11.VZ-hgiH11.V11.V11.VZ-hgiH)b(ECD_DCD )a(TUO82.V01.V82.V01.V01.VZ-hgiHZ-hgiHLR )a(TUO82.V01.V82.V01.V01.VZ-hgiHZ-hgiHLL

Table 1. Driver Mode Selection

035-AIE

edoM

232-SR

edoM

)82.V(

A035-AIE

edoM

SP508 Receiver Table

944-SR

edoM

)63.V(

edoM12.X

)11.V(

nwodtuhS

detsegguS

langiS

Table 2. Receiver Mode Selection

PRELIMINARY INFORMATION

Page 19

+5V

(decoupling capacitor not shown)

RD(a)

RD(b) RT(a)

RT(b) TxC(a)

TxC(b) CS(a)

CS(b)

DM(a)

DM(b)

RRT(a)

RRT(b)

V35RGND

RxD

RDEN

RxC

RTEN

TxCEN

CTS

CSEN

DSR

DMEN

DCD_DTE

RRTEN

ICEN

TMEN

TxC

1µF

D-LATCH

TERM-OFF

LOOPBACK

C1-

C1+

Regulated Charge Pump

SP508

GND

1µF

C2-C2+

V.10-GND

1µF

TxD SD(a) V35TGND1 SD(b) SDEN

TxCE TT(a) V35TGND2 TT(b) TTEN

ST ST(a) V35TGND3 ST(b) STEN

RTS RS(a)

RS(b) RSEN

DTR TR(a)

TR(b) TREN

DCD_DCE RRC(a)

RRC(b) RRCEN

RL(a)

RLEN

LL(a)

LLEN

RECEIVER TERMINATION NETWORK

V.35 MODE

V.11 MODE

RX ENABLE

51ohms

124ohms

V.35 DRIVER TERMINATION NETWORK

51ohms

V.35 MODE

TX ENABLE

124ohms

51ohms

Figure 45. SP508 Block Diagram

PRELIMINARY INFORMATION

Page 20

FEATURES

The SP508 contains highly integrated serial transceivers that offer programmability between interface modes through software control. The SP508 offers the hardware interface modes for RS-232 (V.28), RS-449/V.36 (V.11 and V.10), EIA-530 (V.11 and V.10), EIA-530A (V.11 and V.10), V.35 (V.35 and V.28) and X.21(V.11). The interface mode selection is done via three control pins, which can be latched via microprocessor control.

The SP508 has eight drivers, eight receivers, and Sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. Other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail-safe when inputs are either open or shorted, individual termination resistor ground paths, separate driver and receiver ground outputs, enhanced ESD protection on driver outputs and receiver inputs.

THEORY OF OPERATION

The SP508 device is made up of 1) the drivers, 2) the receivers, 3) a charge pump, 4) DTE/DCE switching algorithm, and 5) control logic.

Drivers

The SP508 has eight enhanced independent drivers. Control for the mode selection is done via a threebit control word into D0, D1, and D2. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. The mode of each driver in the different interface modes that can be selected is shown in Table 1.

There are four basic types of driver circuits – ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423), ITU-T-V.11 (RS-422), and CCITT-V.35.

The V.28 (RS-232) drivers output single-ended signals with a minimum of +5V (with 3kΩ & 2500pF loading), and can operate over 120kbps. Since the SP550 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 driver architecture is similar to Sipex's standard line of RS-232 transceivers.

The RS-423 (V.10) drivers are also single-ended signals which produce open circuit VOL and V measurements of +4.0V to +6.0V. When terminated with a 450Ω load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 (RS-423) drivers are used in RS-449/V.36, EIA-530, and EIA-530A modes as Category II signals from each of their corresponding specifications. The V.10 driver can transmit over 1Mbps if necessary.

The third type of drivers are V.11 (RS-422) differential drivers. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain +2V differential output levels with a load of 100Ω. The signal levels and drive capability of these drivers allow the drivers to also support RS-485 requirements of +1.5V differential output levels with a 54Ω load. The strength allows the SP508 differential driver to drive over long cable lengths with minimal signal degradation. The V.11 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data. Sipex's new driver design over its predecessors allow the SP508 to operate over 40Mbps for differential transmission.

PRELIMINARY INFORMATION

Page 21

The fourth type of drivers are V.35 differential drivers. SP550 for data and clock (TxD, TxCE, and TxC in DCE mode). These drivers are current sources that drive loop current through a differential pair resulting in a 550mV differential voltage at the receiver. These drivers also incorporate fixed termination networks for each driver in order to set the VOH and VOL depending on load conditions. This termination network is basically a “Y” configuration consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors and a V35TGND output. Each of the three drivers and its associated termination will have its own V35TGND output for grounding convenience. Filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground.

The drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable DTE/DCE. The enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on Figure 45. The enable pins have internal pull-up and pulldown devices, depending on the active polarity of the receiver, that enable the driver upon power if the enable lines are left floating. During disabled conditions, the driver outputs will be at a high impedance 3-state.

The driver inputs are both TTL or CMOS compatible. All driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic LOW (“0”). Unused driver inputs can be left floating. The internal pull-up resistor value is approximately 500kΩ.

Receivers

The SP508 has eight enhanced independent receivers. Control for the mode selection is done via a three-bit control word that is the same as the driver control word. Therefore, the modes for the drivers and receivers are identical in the application.

Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface

PRELIMINARY INFORMATION

There are only three available on the

protocols of the receivers. Table 1 shows the mode of each receiver in the different interface modes that can be selected. There are two basic types of receiver circuits—ITU-T-V .28 (RS-232) and ITU-T-V.11, (RS-422).

The RS-232 (V.28) receiver is single-ended and accepts RS-232 signals from the RS-232 driver. The RS-232 receiver has an operating voltage range of +15V and can receive signals downs to +3V. The input sensitivity complies with RS-232 and V .28 at +3V. The input impedance is 3Ω to 7KΩ in accordance to RS-232 and V .28. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic “1” and a +0.8V maximum for a logic “0”. The RS-232 (V.28) protocol uses these receivers for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The RS-232 receivers can operate over 120kbps.

The second type of receiver is a differential type that can be configured internally to support ITU-T-V.10 and CCITT-V.35 depending on its input conditions. This receiver has a typical input impedance of 10kΩ and a differential threshold of less than +100mV, which complies with the ITU-T-V.11 (RS-422) specifications. V.11 receivers are used in RS-449/V.36, EIA-530, EIA-530A and X.21 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential V.11 transceiver has improved architecture that allows over 40Mbps transmission rates.

For receivers dedicated for data and clock (RxD, RxC, TxC) incorporate internal termination for V.11. The termination resistor is typically 120Ω connected between the A and B inputs. The termination is essential for minimizing crosstalk and signal reflection over the transmission line . The minimum value is guaranteed to exceed 100Ω, thus complying with the V.11 and RS-422 specifications. This resistor is invoked when the receiver is operating as a V.11 receiver, in modes EIA-530, EIA-530A, RS-449/V.36, and X.21.

Page 22

The same receivers also incorporate a termination network internally for V.35 applications. For V.35, the receiver input termination is a “Y” termination consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors and V35RGND output. The V35RGND is usually grounded. The receiver itself is identical to the V.11 receiver.

The differential receivers can be configured to be ITU-T-V.10 single-ended receivers by internally connecting the non-inverting input to ground. This is internally done by default from the decoder. The non-inverting input is rerouted to V10GND and can be grounded separately. The ITU-T-V.10 receivers can operate over 1Mbps and are used in RS-449/V.36, E1A-530, E1A-530A and X.21 modes as Category II signals as indicated by their corresponding specifications. All receivers include an enable/disable line for disabling the receiver output allowing convenient half-duplex configurations. The enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on Figure 45. The receiver’s enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. During disabled conditions, the receiver outputs will be at a high impedance state. If the receiver is disabled any associated termination is also disconnected from the inputs.

All receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. For single-ended V.28 and V.10 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high (“1”) at the receiver outputs. The differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic HIGH (“1”) at the receiver output.

PRELIMINARY INFORMATION

CHARGE PUMP

The charge pump is a Sipex-patented design (5,306,954) and uses a unique approach compared to older less-efficient designs. The charge pump still requires four external capacitors, but uses four-phase voltage shifting technique to attain symmetrical power supplies. The charge pump VDD and VSS outputs are regulated to +5.8V and

-5.8V, respectively. There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows.

Phase 1

__VSS charge storage ——During this phase of the clock cycle, the positive side of capacitors C and C2 are initially charged to VCC. C+ is then switched to ground and the charge in C1- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2XVCC.

Phase 2

—VSS transfer —Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to ground, and transfers the negative generated voltage to C3. This generated voltage is regulated to –5.8V. Simultaneously, the positive side of the capacitor C1 is switched to VCC and the negative side is connected to ground.

Phase 3

—VDD charge storage —The third phase of the clock is identical to the first phase—the charge transferred in C1 produces –VCC in the negative terminal of C1 which is applied to the negative side of the capacitor C2 . Since C2+ is at VCC, the voltage potential across C2 is 2XVCC.

Phase 4

—VDD transfer —The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers the generated 5.8V across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.8V. At the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor C1 is switched to VCC and the negative side is connected to ground, and the cycle begins again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.

Page 23

Since both V+ and V- are separately generated from VCC; in a no-load condition V+ and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent inefficiencies in the design.

There are internal pull-up devices on D0, D1, and D2, which allow the device to be in SHUTDOWN mode (“111”) upon power up. However , if the device is powered -up with the D_LATCH at a logic HIGH, the decoder state of the SP508 will be undefined.

The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 1µF with a 16V breakdown voltage rating.

TERM_OFF FUNCTION

The SP508 contains a TERM_OFF pin that disables all three receiver input termination networks regardless of mode. This allows the device to be used in monitor mode applications typically found in networking test equipment. The TERM_OFF pin internally contains a pull-down device with an impedance of over 500kΩ, which will default in a “ON” condition during power-up if V.35 receivers are used. The individual receiver enable line and the SHUTDOWN mode from the decoder will disable the termination regardless of TERM_OFF.

LOOPBACK FUNCTION

The SP508 contains a LOOPBACK pin that invokes a loopback path. This loopback path is illustrated in Figure 50. LOOPBACK has an internal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. During loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications.

ESD TOLERANCE

The SP508 device incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electrostatic discharges and associated transients. Actual ESD figures will be disclosed in the final data sheet.

CTR1/CTR2 EUROPEAN COMPLIANCY

As with all of Sipex’s previous multi-protocol serial transceiver IC’s the drivers and receivers have been designed to meet all the requirements to NET1/NET2 and TBR2 in order to meet CTR1/CTR2 compliancy. The SP508 is also tested in-house at Sipex and adheres to all the NET1/2 physical layer testing and the ITU Series V specifications before shipment. Please note that although the SP508 , as with its predecessors, adhere to CTR1/CTR2 compliancy testing, any complex or unusual configuration should be double-checked to ensure CTR1/CTR2 compliance. Consult the factory for details.

DECODER AND D_LATCH FUNCTION

The SP508 contains a D_LATCH pin that latches the data into the D0, D1, and D2 decoder inputs. If tied to a logic LOW (“0”), the latch is transparent, allowing the data at the decoder inputs to propagate through and program the SP508 accordingly. If tied to a logic HIGH(“1”), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic LOW.

PRELIMINARY INFORMATION

Page 24

TxD

RxD

TxCE

RxC

TxC

RTS

CTS

DTR

DSR

DCD_DCE

DCD_DTE

SD(a)

SD(b)

RD(a)

RD(b)

TT(a)

TT(b)

RT(a)

RT(b)

ST(a)

ST(b)

TxC(a)

TxC(b)

RS(a)

RS(b)

CS(a)

CS(b)

TR(a)

TR(b)

DM(a)

DM(b)

RRC(a)

RRC(b)

RRT(a)

RRT(b)

RL(a)

LL(a)

TM(a)

Figure 46. SP508 Loopback Path

PRELIMINARY INFORMATION

Page 25

20 (V.11, V.28) DTR_DSR_A

23 (V.11) DTR_DSR_B

1µF

C1-

C2-

C1+

C2+

1µF

SP508CF

TxD

TxCE

RTS

DTR

DCD_DCE

RxC

TxC

CTS

DSR

DCD_DTE

10µF

DB-26 Serial Port Connector Pins Signal (DTE_DCE)

2 (V.11, V .35, V.28) TXD_RXD_A

14 (V.11, V.35) TXD_RXD_B

11 (V.11, V.35) TXCE_TXC_B

25 (V.10, V.28) LL_TM

15 (V.11, V .35, V.28)

*TXC_RXC_A

12 (V.11, V.35) *TXC_RXC_B

SDEN

24 (V.11, V .35, V.28) TXCE_TXC_A

3 (V.11, V .35, V.28) RXD_TXD_A

16 (V.11, V.35) RXD_TXD_B

8 (V.11, V.28) DCD_DCD_A

10 (V.11) DCD_DCD_B

Typical SP508 DB-26 Serial Port Configuration

Customer :

Title :

Date :

Doc. # :

Rev.

Reference Design Schematic

233 South Hillview Dr. • Milpitas, CA. 95035

SIGNAL GND (Pins 7)

9 (V.11, V.35) RXC_TXCE_B

17 (V.11, V .35, V.28) RXC_TXCE_A

LLEN

STEN

GND

* - Driver applies for DCE only on pins 15 and 12.

Receiver applies for DTE only on pins 15 and 12.

+5V

#103 (TxD)

#108 (DTR)

#105 (RTS)

#141 (LL)

#105 (RXD)

#115 (RXC)

#106 (CTS)

#107 (DSR)

#109 (DCD)

DTE

I/O Lines represented by double arrowhead signifies a bi-directional bus.

Input Line

Output Line

#114 (TxC)

#113 (TXCE)

#109 (DCD)

DCE

RxD

TTEN

TREN

RSEN

RRCEN

RLEN

RDEN

TMEN

TxCEN

RTEN

DMEN

CSEN

RRTEN

ICEN

V10_GND

V35TGND1

V35TGND2

V35TGND3

V35RGND

TERM_OFF

D_LATCH

D0D1D2

Charge Pump Section

Transceiver Section

Logic Section

+5V

21 (V.10, V.28) RL_RI

22 (V.10, V.28) RI_RL

18 (V.10, V.28) LL_TM

#125 (RI)

#142 (TM)

#140 (RL)

DCE/DTE

Driver applies for DCE only on pins 8 and 10.

Receiver applies for DTE only on pins 8 and 10.

LOOPBACK

+5V

19 (V.11) RTS_CTS_B

4 (V.11, V.28) RTS_CTS_A

6 (V.11, V.28) DSR_DTR_A

22 (V.11) DSR_DTR_B

13 (V.11) CTS_RTS_B

5 (V.11, V.28) CTS_RTS_A

Figure 47. SP508 Typical Operating Configuration to Serial Port Connector with DCE/DTE programmability

PRELIMINARY INFORMATION

Page 26

SEE

FIG 4

PACKAGE:

5 2

D1/2

-A-

D/2

-D-

-E-

-B-

2 5

QUAD FLATPACK LQFP OUTLINE

-H-

(b)

(L1)

GAUGE PLANE

.25

PLATING

WITH

D1/4

ddd M

– D –

E1/4

A-B S

D S

(See Fig 2)

A–B

bbb

(N-4)X

– C –

N / 4 Tips

—

0.05 S

ALL DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.

THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15mm.

DATUMS AND TO BE DETERMINED AT DATUM PLANE

TO BE DETERMINED AT SEATING PLANE

DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH.

DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

RECTANGULAR VARIATIONS AHA AND BHA HAVE 38 AND 26 LEADS ON SIDES D AND E RESPECTIVELY. RECTANGULAR VARIATIONS AHB AND BHB HAVE 30 AND 20 LEADS ON SIDES D AND E RESPECTIVELY.

ALL DIMENSIONS ARE IN MILLIMETER.

DIMENSIONS b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm.DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm FOR 0.4mm AND 0.5mm PITCH PACKAGES.

EXACT SHAPE OF EACH CORNER IS OPTIONAL.

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10mm AND 0.25mm FROM THE LEAD TIP.

A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY.

aaa

A – B

A–B

ccc

E1/2

SEA TING

-CPLANE

– H –

e/2

-X-

X = A, B or D

EVEN LEAD SIDES

TOP VIEW

A1 A2

b1 R2 R1 00 01 02 03

aaa bbb ccc ddd

ODD LEAD SIDES

TOP VIEW

S Y

B O L

N e b

S c

ISSUE

NOTE

MS-026

BED

SQUARE

MIN

NOM

1.40

1.50

0.05

0.10

1.35

1.40

16.00 BSC

14.00 BSC

16.00 BSC

14.00 BSC

100

0.50 BSC

0.17

0.22

0.17

0.20

0.08

–

0.08

–

0 11 11

0.20

0.09

0.45

Tolerance of Form and Position

REF

3.5

–

– – –

0.60

1.00 REF

0.20

0.08

0.08 1, 8

11 - 411

(b)

-X-

X = A, B or D

MAX

1.60

0.15

1.45

0.27

0.23

0.20

0.16

0.75

N O

T E

5, 2

–

PRELIMINARY INFORMATION

Page 27

Model Temperature Range Package Types

ORDERING INFORMATION

SP508CF ........................................................................... 0°C to +70°C ............................................................................. 100–pin JEDEC LQFP

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

PRELIMINARY INFORMATION

Datasheet SP508CF Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual