Datasheet SP506CF Datasheet (Sipex Corporation)

®

SP506

5V, Single Chip W AN Multi-Mode Serial Transceiver

■ Interface Modes Supported: ✓ RS-232 (V.28) ✓ X.21/RS-422 (V.11) ✓ EIA-530 (V.10 & V.11) ✓ EIA-530A (V.10 & V.11) ✓ RS-449 (V.10 & V.11) ✓ V.35 (V.35 & V.28) ✓ V.36 (V.10 & V.11) ✓ RS-485 (unterminated V.11)

■ Software Selectable Protocol

■ Highest Differential Transmission Rates

at over 20Mbps

■ +5V Only Operation

■ Seven (7) Drivers and Seven (7) Receivers

■ Driver and Receiver Tri-state Control

■ Internal Transceiver Termination Resistors for

V.11 and V.35 Protocols

■ Loopback Self-Test Mode

■ Improved ESD Tolerance for Analog I/Os

■ Compliant to NET1/2 and TBR2 Physical Layer

Requirements

■ Used in WAN Serial Ports in Routers, Switches,

DSU/CSU's and other Access Devices

DESCRIPTION

The SP506 is a monolithic IC that supports eight (8) popular serial interface standards for DTE to DCE connectivity. The SP506 is pin-to-pin compatible to our SP505 multi-protocol transceiver but with faster throughput. The seven (7) drivers and seven (7) receivers can transmit and receive signals at 20Mbps. As with the SP505, the SP506 requires no additional external components for compliant operation for all of the eight (8) modes of operation. All necessary termination is integrated within the SP506 and is switchable when V.35 drivers, V.35 receivers, and V.11 receivers are used. The SP506 can operate as either a DTE or DCE.

Additional features with the SP506 include internal loopback that can be initiated in either singleended or differential modes. While in loopback mode, driver outputs are internally connected to receiver inputs creating an internal signal path convenient for diagnostic testing. This eliminates the need for an external loopback plug. The SP506 also includes a latch enable pin with the driver and receiver address decoder. Tri-state ability for the driver and receiver outputs is controlled by supplying a 4-bit word into the address decoder. Seven (7) drivers and one (1) receiver in the SP506 include separate enable pins for added convenience.

V.35

EIA-530

WAN

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VCC............................................................................+7V

Input Voltages:

Logic...............................-0.3V to (VCC+0.5V)

Drivers............................-0.3V to (VCC+0.5V)

Receivers........................................±15.5V

Output Voltages:

Logic................................-0.3V to (VCC+0.5V)

Drivers................................................±15V

STORAGE CONSIDERATIONS

Due to the relatively large package size of the 80-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order remove moisture prior to soldering. Sipex ships the 80-pin QFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.

Receivers........................-0.3V to (VCC+0.5V)

Storage Temperature..........................-65˚C to +150˚C

Power Dissipation per package 80-pin QFP (derate 18.3mW/˚C above +70oC)...1500mW

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

LOGIC INPUTS

V

IL

V

IH

2.0 Volts

LOGIC OUTPUTS

V

OL

V

OH

2.4 Volts I

V.28 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±15 Volts per Figure 1 Loaded Voltage ±5.0 ±15 Volts per Figure 2 Short-Circuit Current ±100 mA per Figure 4 Power-Off Impedance 300 Ω per Figure 5

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 1.5 µs per Figure 6; +3V to -3V Instantaneous Slew Rate 30 V/µs per Figure 3 Propagation Delay

t

PHL

t

PLH

Max.Transmission Rate 120 230 kbps

0.5 1 5 µs

0.8 Volts

0.4 Volts I

= –3.2mA

OUT

= 1.0mA

OUT

V.28 RECEIVER

DC Parameters

Inputs

Input Impedance 3 7 kΩ per Figure 7 Open-Circuit Bias +2.0 Volts per Figure 8 HIGH Threshold 1.7 3.0 Volts LOW Threshold 0.8 1.2 Volts

AC Parameters VCC = +5V for AC parameters

Propagation Delay

t

PHL

t

PLH

50 100 500 ns 50 100 500 ns

2

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

V.28 RECEIVER (continued)

AC Parameters (cont.)

Max.Transmission Rate 120 230 kbps

V.10 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±4.0 ±6.0 Volts per Figure 9 Test-Terminated Voltage 0.9V Short-Circuit Current ±150 mA per Figure 11

OC

Power-Off Current ±100 µA per Figure 12

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 200 ns per Figure 13; 10% to 90% Propagation Delay

t

PHL

t

PLH

Max.Transmission Rate 120 kbps

50 100 500 ns 50 100 500 ns

V.10 RECEIVER

DC Parameters

Inputs

Input Current –3.25 +3.25 mA per Figures 14 and 15 Input Impedance 4 kΩ Sensitivity ±0.3 Volts

AC Parameters VCC = +5V for AC parameters

Propagation Delay

t

PHL

t

PLH

Max.Transmission Rate 120 kbps

50 120 250 ns 50 120 250 ns

V.11 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±5.0 Volts per Figure 16 Test Terminated Voltage ±2.0 Volts per Figure 17

Balance ±0.4 Volts per Figure 17 Offset +3.0 Volts per Figure 17 Short-Circuit Current ±150 mA per Figure 18 Power-Off Current ±100 µA per Figure 19

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 20 ns per Figures 21 and 36; 10% to 90% Propagation Delay

t

PHL

t

PLH

Differential Skew 10 20 ns per Figures 33 and 36, CL = 50pF Max.Transmission Rate 20 Mbps per Figure 33, CL = 50pF

0.5V

OC

0.67V

50 65 85 ns per Figures 33 and 36, CL = 50pF 50 65 85 ns per Figures 33 and 36, CL = 50pF

Volts per Figure 10

Volts

OC

fIN = 10MHz

V.11 RECEIVER

DC Parameters

Inputs

Common Mode Range –7 +7 Volts Sensitivity ±0.3 Volts

3

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

V.11 RECEIVER (continued)

DC Parameters (cont.)

Input Current –3.25 ±3.25 mA per Figure 20 and 22 Current w/ 100Ω Termination ±60.75 mA per Figure 23 and 24 Input Impedance 4 kΩ

AC Parameters VCC = +5V for AC parameters

Propagation Delay t

PHL

t

PLH

Differential Skew 10 ns per Figure 33; CL = 50pF Max.Transmission Rate 20 Mbps per Figure 33; CL = 50pF

V.35 DRIVER

DC Parameters

Outputs

Open Circuit Voltage ±1.20 Volts per Figure 16 Test Terminated Voltage ±0.44 ±0.66 Volts per Figure 25 Offset ±0.6 Volts per Figure 25 Source Impedance 50 150 Ω per Figure 27; ZS = V2/V1 x 50Ω Short-Circuit Impedance 135 165 Ω per Figure 28

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 30 40 ns per Figure 29; 10% to 90% Propagation Delay

t

PHL

t

PLH

Differential Skew 7 10 ns per Figures 33 and 36; CL = 20pF Max.Transmission Rate 20 Mbps per Figure 33; CL = 20pF

30 65 85 ns per Figures 33 and 38; CL = 50pF 30 65 85 ns per Figures 33 and 38; CL = 50pF

fIN = 10MHz

50 70 90 ns per Figures 33 and 36; CL = 20pF 50 70 90 ns per Figures 33 and 36; CL = 20pF

fIN = 10MHz

V.35 RECEIVER

DC Parameters

Inputs

Sensitivity ±80 mV Source Impedance 90 110 Ω per Figure 30; ZS = V2/V1 x 50Ω Short-Circuit Impedance 135 165 Ω per Figure 31

AC Parameters VCC = +5V for AC parameters

Propagation Delay t

PHL

t

PLH

Differential Skew 10 ns per Figure 33; CL = 20pF

30 75 90 ns per Figures 33 and 38; CL = 20pF 30 75 90 ns per Figures 33 and 38; CL = 20pF

Max.Transmission Rate 20 Mbps per Figure 33; CL = 20pF

fIN = 10MHz

TRANSCEIVER LEAKAGE CURRENTS

Driver Output 3-State Current 500 µA per Figure 32; Drivers disabled Rcvr Output 3-State Current 1 10 µA DECX = 0000, 0.4V ≤ VO ≤ 2.4V

4

OTHER AC CHARACTERISTICS

TA = +25°C and VCC = +5.0V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28

t

; Tri-state to Output LOW 0.70 5.0 µsCL = 100pF, Fig. 34 & 40; S

PZL

t

; Tri-state to Output HIGH 0.40 2.0 µsCL = 100pF, Fig. 34 & 40; S

PZH

t

; Output LOW to Tri-state 0.20 2.0 µsCL = 100pF, Fig. 34 & 40; S

PLZ

t

; Output HIGH to Tri-state 0.40 2.0 µsCL = 100pF, Fig. 34 & 40; S

PHZ

RS-423/V.10

t

; Tri-state to Output LOW 0.15 2.0 µsCL = 100pF, Fig. 34 & 40; S

PZL

t

; Tri-state to Output HIGH 0.20 2.0 µsCL = 100pF, Fig. 34 & 40; S

PZH

t

; Output LOW to Tri-state 0.20 2.0 µsCL = 100pF, Fig. 34 & 40; S

PLZ

t

; Output HIGH to Tri-state 0.15 2.0 µsCL = 100pF, Fig. 34 & 40; S

PHZ

RS-422/V.11

t

; Tri-state to Output LOW 2.80 10.0 µsCL = 100pF, Fig. 34 & 37; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 34 & 37; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 34 & 37; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 34 & 37; S

PHZ

V.35

t

; Tri-state to Output LOW 2.60 10.0 µsCL = 100pF, Fig. 34 & 37; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 34 & 37; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 34 & 37; S

PLZ

t

; Output HIGH to Tri-state 0.15 2.0 µsCL = 15pF, Fig. 34 & 37; S

PHZ

RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28

t

; Tri-state to Output LOW 0.12 2.0 µsCL = 100pF, Fig. 35 & 38; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 35 & 38; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 35 & 38; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 35 & 38; S

PHZ

RS-423/V.10

t

; Tri-state to Output LOW 0.10 2.0 µsCL = 100pF, Fig. 35 & 38; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 35 & 38; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 35 & 38; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 100pF, Fig. 35 & 38; S

PHZ

closed closed closed closed

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

5

OTHER AC CHARACTERISTICS (Continued)

TA = +25°C and VCC = +5.0V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-422/V.11

t

; Tri-state to Output LOW 0.10 2.0 µsCL = 100pF, Fig. 35 & 39; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 35 & 39; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 35 & 39; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 35 & 39; S

PHZ

V.35

t

; Tri-state to Output LOW 0.10 2.0 µsCL = 100pF, Fig. 35 & 39; S

PZL

t

; Tri-state to Output HIGH 0.10 2.0 µsCL = 100pF, Fig. 35 & 39; S

PZH

t

; Output LOW to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 35 & 39; S

PLZ

t

; Output HIGH to Tri-state 0.10 2.0 µsCL = 15pF, Fig. 35 & 39; S

PHZ

TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 33, 36, 38) V.28 Driver 100 ns [ (t

100 ns [ (t

V.28 Receiver 20 ns [ (t

20 ns [ (t

V.11 Driver 2 ns [ (t

2ns[ (t

V.11 Receiver 3 ns [ (t

3ns[ (t

V.10 Driver 5 ns [ (t

5ns[ (t

V.10 Receiver 5 ns [ (t

5ns[ (t

V.35 Driver 4 ns [ (t

4ns[ (t

V.35 Receiver 6 ns [ (t

6ns[ (t

closed closed closed closed

phl

plh

phl plh

phl

plh

phl plh

phl

plh

phl plh

phl

plh

phl plh

) )

Tx1 Tx1

) )

Tx1 Tx1

) )

Tx2 Tx2

) )

Tx1 Tx1

) )

Rx1 Rx1

Rx2 Rx2

Rx1 Rx1

– (t – (t

)

phl

)

plh

phl phl

)

phl

)

plh

phl phl

)

phl

)

plh

phl phl

)

phl

)

plh

phl phl

Tx6,7 Tx6,7

)

Rx2,7

)

Rx2,7

Tx6,7 Tx6,7

)

Rx2,7

)

Rx2,7

Tx3,4,5 Tx3,4,5

)

Rx3,4,5

)

Rx3,4,5

Tx6,7 Tx6,7

)

Rx2,7

)

Rx2,7

1

2

1

2

1

2

1

2

] ]

]

] ] ]

]

] ]

]

] ] ]

] ]

POWER REQUIREMENTS

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

V

CC

I

(No Mode Selected) 30 mA All ICC values are with V

CC

(V.28/RS-232) 65 mA fIN = 120kbps; Drivers active & loaded.

4.75 5.00 5.25 Volts

CC

= +5V

(V.11/X.21) 175 mA fIN = 10Mbps; Drivers active & loaded. (EIA-530 & RS-449) 250 mA fIN = 10Mbps; Drivers active & loaded. (V.35) 100 mA V.35 @ fIN = 10Mbps, V.28 @ 20kbps;

Drivers active & loaded.

6

TEST CIRCUITS

A

V

OC

C

A

3kΩ

Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage

A

Oscilloscope

7kΩ

C

V

T

Scope used for slew rate measurement.

C

A

V

T

I

sc

Figure 3. V.28 Driver Output Slew Rate

VCC = 0V

A

C

I

x

Figure 5. V.28 Driver Output Power-Off Impedance

±2V

Figure 4. V.28 Driver Output Short-Circuit Current

A

3kΩ

C

2500pF

Oscilloscope

Figure 6. V.28 Driver Output Rise/Fall Times

7

A

I

ia

±15V

A

V

oc

C

Figure 7. V.28 Receiver Input Impedance

A

3.9kΩ

V

OC

C

Figure 9. V.10 Driver Output Open-Circuit Voltage

C

Figure 8. V.28 Receiver Input Open Circuit Bias

A

450Ω

V

t

C

Figure 10. V.10 Driver Output Test Terminated Voltage

V

= 0V

CC

A

I

sc

C

I

x

±0.25V

Figure 12. V.10 Driver Output Power-Off CurrentFigure 11. V.10 Driver Output Short-Circuit Current

8

A

450Ω

Oscilloscope

A

I

ia

±10V

C

Figure 13. V.10 Driver Output Transition Time Figure 14. V.10 Receiver Input Current

V.10 RECEIVER

+3.25mA

A

3.9kΩ

–3V–10V

+10V+3V

B

Maximum Input Current

C

versus V oltage

–3.25mA

Figure 15. V.10 Receiver Input IV Graph

Figure 16. V.11 and V.35 Driver Output Open-Circuit Voltage

V

OCA

V

OC

V

OCB

A

50Ω

V

T

50Ω

B

C

V

OS

C

A

B

I

sa

I

sb

Figure 17. V.11 Driver Output Test Terminated Voltage Figure 18. V.11 Driver Output Short-Circuit Current

9

V

= 0V

CC

A

I

xa

±0.25V

I

ia

±10V

B

C

V

= 0V

CC

A

I

xb

B

C

Figure 19. V.11 Driver Output Power-Off Current

±0.25V

B

C

A

I

B

C

Figure 20. V.11 Receiver Input Current

±10V

ib

V.11 RECEIVER

A

B

Oscilloscope

50Ω

–3V–10V

V

E

+3.25mA

+10V+3V

C

Maximum Input Current versus V oltage

–3.25mA

Figure 21. V.11 Driver Output Rise/Fall Time

Figure 22. V.11 Receiver Input IV Graph

10

100Ω to 150Ω

V.11 RECEIVER

A

I

ia

±6V

i [mA] = (V [V] – 3) / 4.0

w/ Optional Cable Termination

(100Ω to 150Ω)

i [mA] = V [V] / 0.1

–3V–6V

B

C

A

100Ω to 150Ω

I

ib

B

±6V

C

Figure 23. V.11 Receiver Input Current w/ Termination

+6V+3V

i [mA] = (V [V] – 3) / 4.0

i [mA] = V [V] / 0.1

Maximum Input Current versus V oltage

Figure 24. V.11 Receiver Input Graph w/ Termination

A

50Ω

V

T

50Ω

B

V

OS

C

Figure 25. V.35 Driver Output Test Terminated Voltage

V

1

A

50Ω

V

T

50Ω

B

C

Figure 26. V.35 Driver Output Offset Voltage

V

OS

C

Figure 27. V.35 Driver Output Source Impedance

A

50Ω

24kHz, 550mV

p-p

V

2

B

Sine Wave

11

A

50Ω

Oscilloscope

I

B

SC

±2V

50Ω

B

50Ω

C

Figure 28. V.35 Driver Output Short-Circuit Impedance

V

1

A

50Ω

24kHz, 550mV

p-p

V

2

Sine Wave

B

C

Figure 30. V.35 Receiver Input Source Impedance

C

Figure 29. V.35 Driver Output Rise/Fall Time

A

I

B

sc

±2V

C

Figure 31. V.35 Receiver Input Short-Circuit Impedance

Any one of the three conditions for disabling the driver.

00 0

VCC = 0V

Logic “1”

Figure 32. Driver Output Leakage Current Test

0

DEC

3

V

CC

0

1

2

A

I

±15V

ZSC

T

IN

A B

f

(50% Duty Cycle, 2.5V

B

IN

C

L1

C

L2

)

P-P

A

R

OUT

B

15pF

Figure 33. Driver/Receiver Timing Test Circuit

12

Output

Under

Test

V

S

500Ω

C

L

1

S

2

CC

Receiver

Output

Test Point

RL

1KΩC

1KΩ

V

S

1

S

2

CC

Figure 34. Driver Timing Test Load Circuit

INPUT

– V

A

+3V

0V

A B

+

V

O

0V

–

V

O

B

|

DRIVER

OUTPUT

DIFFERENTIAL

OUTPUT

V

t

SKEW = | tDPLH - tDPHL

Figure 36. Driver Propagation Delays

+3V

DECx or Tx_Enable

0V 5V

A, B

V

OL

V

OH

A, B

0V

Figure 35. Receiver Timing Test Load Circuit

f > 10MHz; tR < 10ns; tF < 10ns

1.5V 1.5V t

PLH

1/2V

O

V

O

t

DPLH

t

R

t

PHL

t

DPHL

1.5V 1.5V t

ZL

2.3V

Output normally LOW

Output normally HIGH

t

ZH

1/2V

t

F

0.5V

O

t

LZ

t

HZ

Figure 37. Driver Enable and Disable Times

f > 10MHz; tR < 10ns; tF < 10ns

+

V

A – B

RECEIVER OUT

t

SKEW = | tPHL - tPLH |

0D2

–

V

0D2

V

OH

V

OL

t

PLH

0V 0V

INPUT

OUTPUT

(VOH - VOL)/2

t

PHL

(VOH - VOL)/2

Figure 38. Receiver Propagation Delays

13

DECx or RCVR Enable

+3V

0V 5V

RECEIVER OUT

V

IL

V

IH

RECEIVER OUT

0V

Figure 39. Receiver Enable and Disable Times

1.5V 1.5V t

ZL

1.5V

Output normally LOW

Output normally HIGH

t

ZH

0.5V

t

LZ

t

HZ

+3V

DECx or Tx_Enable

1.5V

0V

t

0V

T

OUT

V

OL

ZL

Output LOW

0.5V

+3V

DECx or Tx_Enable

1.5V

0V

t

T

OUT

V

OH

0.5V

0V

ZH

Output HIGH

Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times

0.5V

1.5V

t

LZ

0.5V

t

HZ

14

Figure 41. Typical V.28 Driver Output Waveform

Figure 43. Typical V.11 Driver Output Waveforms Figure 44. Typical V.35 Driver Output Waveforms

Figure 42. Typical V.10 Driver Output Waveform

15

PINOUT

RxD 1

SDEN

2

TREN

3

RSEN 4

LLEN

5

TTEN 6

SCTEN 7

LATCH 8

DEC

9

3

DEC

10

2

DEC

11

1

DEC

12

0

DTR 13

TxD 14 TxC 15

RTS 16

RL 17

RLEN 18

DCD 19

RxC 20

80 CTS

RI 21

79 SCT

ST 22

78 DSR

STEN 23

77 SCT(b)

76 SCT(a)

75 GND

74 VCC73 VCC72 GND

SP506

25

27

26

+

1

LL 24

CC

DD

C

V

Pin 61 — SD(a) — Analog Out — Send data, inverted; sourced from TxD.

Pin 63 — TT(a) — Analog Out — Terminal

71 RD(b)

70 RD(a)

69 DM(b)

68 DM(a)

67 CS(b)

66 CS(a)

65 TT(b)

64 GND

63 TT(a)

62 VCC61 SD(a)

60 GND 59 SD(b) 58 TR(a) 57 GND 56 TR(b) 55 V

CC

54 RS(a) 53 GND 52 RS(b) 51 LL(a) 50 GND 49 LL(b) 48 V

CC

47 RL(a) 46 GND 45 RL(b) 44 ST(b) 43 GND 42 ST(a) 41 V

CC

32

33

28

30

31

–

+

1

2

SS

CC

C

V

GND 34

IC(a) 39

GND 29

RR(a) 35

RR(b) 36

RT(a) 37

RT(b) 38

IC(b) 40

Timing, inverted; sourced from TxC Pin 65 — TT(b) — Analog Out — Terminal

Timing, non–inverted; sourced from TxC. Pin 70 — RD(a) — Receive Data, analog input;

inverted; source for RxD. Pin 71 — RD(b) — Receive Data; analog input;

non-inverted; source for RxD. Pin 76 — SCT(a) — Serial Clock Transmit;

analog input, inverted; source for SCT. Pin 77 — SCT(b) — Serial Clock Transmit:

analog input, non–inverted; source for SCT Pin 79 — SCT — Serial Clock Transmit; TTL

output; sources from SCT(a) and SCT(b) inputs.

PIN ASSIGNMENTS CLOCK AND DATA GROUP

Pin 1 — RxD — Receive Data; TTL output, sourced from RD(a) and RD(b) inputs.

Pin 14 — TxD — TTL input ; transmit data source for SD(a) and SD(b) outputs.

Pin 15 — TxC — Transmit Clock; TTL input for TT driver outputs.

Pin 20 — RxC — Receive Clock; TTL output sourced from RT(a) and RT(b) inputs.

Pin 22 — ST — Send Timing; TTL input; source for ST(a) and ST(b) outputs.

Pin 37 — RT(a) — Receive Timing; analog input, inverted; source for RxC.

Pin 38 — RT(b) — Receive Timing; analog input, non-inverted; source for RxC.

Pin 42 — ST(a) — Send Timing; analog output, inverted; sourced from ST.

Pin 44 — ST(b) — Send Timing; analog output, non-inverted; sourced from ST.

Pin 59 — SD(b) — Analog Out — Send data, non-inverted; sourced from TxD.

CONTROL LINE GROUP

Pin 13 — DTR — Data Terminal Ready; TTL input; source for TR(a) and TR(b) outputs.

Pin 16 — RTS — Ready To Send; TTL input; source for RS(a) and RS(b) outputs.

Pin 17 — RL — Remote Loopback; TTL input; source for RL(a) and RL(b) outputs.

Pin 19 — DCD— Data Carrier Detect; TTL output; sourced from RR(a) and RR(b) inputs.

Pin 21 — RI — Ring In; TTL output; sourced from IC(a) and IC(b) inputs.

Pin 24 — LL — Local Loopback; TTL input; source for LL(a) and LL(b) outputs.

Pin 35 — RR(a)— Receiver Ready; analog input, inverted; source for DCD.

Pin 36 — RR(b)— Receiver Ready; analog input, non-inverted; source for DCD.

Pin 39 — IC(a)— Incoming Call; analog input, inverted; source for RI.

Pin 40 — IC(b)— Incoming Call; analog input,non-inverted; source for RI.

16

Pin 45 — RL(b) — Remote Loopback; analog output, non-inverted; sourced from RL.

Pin 7 — SCTEN — Enables SCT receiver; active high; TTL input.

Pin 47 — RL(a) — Remote Loopback; analog output inverted; sourced from RL.

Pin 49— LL(b) — Local Loopback; analog output, non-inverted; sourced from LL.

Pin 51 — LL(a) — Local Loopback; analog output, inverted; sourced from LL.

Pin 52 — RS(b) — Ready To Send; analog output, non-inverted; sourced from RTS.

Pin 54 — RS(a) — Ready To Send; analog output, inverted; sourced from RTS.

Pin 56 — TR(b) — Terminal Ready; analog output, non-inverted; sourced from DTR.

Pin 58 — TR(a) — Terminal Ready; analog output, inverted; sourced from DTR.

Pin 66 — CS(a)— Clear To Send; analog input, inverted; source for CTS.

Pin 67 — CS(b)— Clear To Send; analog input, non-inverted; source for CTS.

Pin 68 — DM(a)— Data Mode; analog input, inverted; source for DSR.

Pin 69 — DM(b)— Data Mode; analog input, non-inverted; source for DSR

Pin 78 — DSR— Data Set Ready; TTL output; sourced from DM(a), DM(b) inputs.

Pin 80 — CTS— Clear To Send; TTL output; sourced from CS(a) and CS(b) inputs.

Pin 8 — LATCH — Latch control for decoder bits (pins 9-12), active low. Logic high input will make decoder transparent.

Pins 12–9 — DEC0 – DEC3 — Transmitter and receiver decode register; configures transmitter and receiver modes; TTL inputs.

Pin 18 — RLEN — Enables RL driver; active low; TTL input.

Pin 23 — STEN — Enables ST driver; active low; TTL input.

POWER SUPPLIES

Pins 25, 33, 41, 48, 55, 62, 73, 74 — VCC — +5V input.

Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 — GND — Ground.

Pin 27 — VDD +10V Charge Pump Capacitor — Connects from VDD to VCC. Suggested capacitor size is 22µF, 16V.

Pin 32 — VSS –10V Charge Pump Capacitor — Connects from ground to VSS. Suggested capacitor size is 22µF, 16V.

Pins 26 and 30 — C Capacitor — Connects from C

+

1

Suggested capacitor size is 22µF, 16V. Pins 28 and 31 — C

Capacitor — Connects from C

+

2

Suggested capacitor size is 22µF, 16V.

and C

–

— Charge Pump

1

–

— Charge Pump

2

+

to C

1

+

to C

2

1

2

–

.

–

.

CONTROL REGISTERS

Pins 2 — SDEN — Enables TxD driver, active low; TTL input.

Pins 3 — TREN — Enables DTR driver, active low; TTL input.

Pins 4 — RSEN — Enables RTS driver, active low; TTL input.

Pins 5 — LLEN — Enables LL driver, active low; TTL input.

Pin 6 — TTEN — Enables TT driver, active low; TTL input.

17

SP506 Driver Mode Selection

RS422

V.11– V.11+ V.11– V.11+

V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+

w/ Term.

0101

V.11– V.11+

V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11–

V.11+ V.11–

V.11– V.11+ V.11– V.11+ tri-state V.11– V.11+

V.10

tri-state

V.10

tri-state

V.11– V.11+ V.11+ V.11–

V.11+

V.11–

V.11+

1100 1101 1111

V.11– V.11+

V.11–

V.11+ V.11– V.11+ V.11– V.11+

V.11– V.11+

V.11–

V.11+

V.11–

V.11+

V.10

tri-state

V.11–

tri-state

V.11– V.11+

Pin Label Mode: RS232 V.35 RS422 RS449 EIA530 EIA-530A

DEC – DEC

30

SD(a) tri-state SD(b) TR(a) tri-state

0000 0010 1110 0100

tri-state

V.28

tri-state

V.28

V.35– V.35+

V.28 TR(b) tri-state tri-state tri-state RS(a) tri-state

V.28 V.11–

V.28 RS(b) tri-state tri-state tri-state RL(a) tri-state RL(b) tri-state LL(a) tri-state LL(b) tri-state ST(a) tri-state ST(b)

tri-state TT(a) tri-state TT(b)

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.35– V.35+ V.35– V.35+

Table 1. SP506 Driver Decoder Table

SP506 Receiver Mode Selection

Pin Label

DEC – DEC

30

RD(a) RD(b) RT(a) RT(b) CS(a) CS(b) DM(a) DM(b) RR(a) RR(b) IC(a) IC(b)

SCT(a) SCT(b)

Table 2. SP506 Receiver Decoder Table

Mode: RS232 V.35 RS422

w/ Term.

RS422 RS449 EIA530 EIA-530A

0000 0010 1110 0100 0101 1100 1101 1111

>10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND

>10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND

>10kΩ to GND >10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28 V.11–

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>12kΩ to GND

V.35– V.35+ V.35–

V.35+

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.35– V.35+

V.11– V.11+ V.11– V.11+

V.11– V.11+

V.11+ V.11– V.11+ V.11– V.11+

V.11– V.11+

V.11–

120Ω

V.11+ V.11–

120Ω

V.11+ V.11– V.11+

V.11– V.11+ V.11– V.11+ V.11–

V.11+ V.11–

120Ω

V.11+

V.11– V.11+ V.11– V.11+

V.11– V.11+ V.11– V.11+ V.11– V.11+

V.10

V .11–

120Ω

V .11+ V.11–

120Ω

V.11+

V.11– V.11+ V.11– V.11+ V.11– V.11+

V.10

>10kΩ to GND >10kΩ to GND

V.11– V.11+

V .11–

120Ω

V .11+

120Ω

V .11– V .11+ V .11– V .11+

>10kΩ to GND

V .11– V .11+

V.10

V.11+ V.11– V.11+

V.11– V.11+

V.10

V.11– V.11+

V.10

V.36

0110

V.11– V.11+

tri-state

V.11– V.11+ V.11– V.11+

V.36

0110

V .11–

120Ω

V .11+ V .11–

120Ω

V .11+

>10kΩ to GND

V .11–

120Ω

V .11+

V.10

120Ω

V.10

120Ω

18

(SEE PINOUT FOR VCC PINS)

RS-422 Mode Input Word

1

0

1

0

+5V

10µF

1N5819

25 26

VCCV

22µF

27

DD

Charge Pump

22µF

C1+

A

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM (b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

IC(b) 40

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

9

10

11

12

8

LATCH

(SEE PINOUT ASSIGNMENTS FOR GROUND PINS)

X

MODE

DECODER LATCH

SP506

C1-

2830

C2+

22µF

31

C2-

22µF

32

V

SS

B

14 TxD 61 SD(a) 59 SD(b) 2 SDEN

13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN

24 LL 51 LL(a) 49 LL(b)

5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

A — Receiver Tri-State circuitry,

V.11, & V.35 termination resistor circuitry (RxD, RxC & SCT).

B — Driver Tri-State circuitry &

V.35 termination circuitry (TxD, TxC & ST).

Figure 45. SP506 Typical Operating Circuit

19

PIN 1

PACKAGE: QUAD FLATPACK

JEDEC "BE-2" OUTLINE

D D1

0.3" RAD. TYP.

0.2" RAD. TYP.

C

L

0.009"/0.015" (0.220/0.380)

C

L

0.02559"/– (0.65/–)

DIMENSIONS in Inches

A1

Minimum/Maximum

(mm)

A

A1

D

D1

E

E1

L

E1

E

0°–7°

AA

Seating

Plane

JEDEC BE-2 Outline

80–PIN

–/0.0925 (–/2.350)

–/0.010

(–/0.250)

0.667/0.687

(16.950/17.450)

0.547/0.555

(13.900/14.100)

0.667/0.687

(16.950/17.450)

0.547/0.555

(13.900/14.100)

0.0255/0.0375 (0.650/0.950)

0.005/0.009" (0.13/0.23)

10°-16°

6°±4°

10°-16°

L

20

Model Temperature Range Package Types

ORDERING INFORMATION

SP506CF ........................................................................... 0°C to +70°C ......................................................... 80–pin JEDEC (BE-2 Outline) QFP

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

21

Datasheet SP506CF Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual