Datasheet SP505ACF, SP505BCF Datasheet (Sipex Corporation)

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Page 1

SP505

WAN Multi-Mode Serial Transceiver

■ +5V Only Operation

■ Seven (7) Drivers and Seven (7) Receivers

■ Driver and Receiver Tri-state Control

■ Internal Transceiver Termination Resistors for

V.11 and V.35 Protocols

■ Loopback Self-Test Mode

■ Software Selectable Protocol Selection

■ Interface Modes Supported: ✓ RS-232 (V.28) ✓ X.21/RS-422 (V.11) ✓ EIA-530 (V.10 & V.11) ✓ EIA-530A (V.10 & V.11) ✓ RS-449 (V.10 & V.11) ✓ V.35 (V.35 & V.28) ✓ V.36 (V.10 & V.11) ✓ RS-485 (un-terminated V.11)

■ Improved ESD Tolerance for Analog I/Os

■ High Differential Transmission Rates

➥ SP505A - 10Mbps ➥ SP505B - over 16Mbps

■ Compliant to NET1/2 and TBR2 Physical

Layer Requirements

(TUV Test Report NET2/052101/98) (TUV Test Report CTR2/052101/98)

DESCRIPTION...

The SP505 is a monolithic device that supports eight (8) popular serial interface standards for DTE to DCE connectivity. The SP505 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Seven (7) drivers and seven (7) receivers can be configured via software for any of the above interface modes at any time. The SP505 requires no additional external components for compliant operation for all of the eight (8) modes of operation. All necessary termination is integrated within the SP505 and is switchable when V.35 drivers, V.35 receivers, and V.11 receivers are used. The SP505 can operate as either a DTE or DCE.

Additional features with the SP505 include internal loopback that can be initiated in either single-ended or differential modes. While in loopback mode, driver outputs are internally connected to receiver inputs creating an internal signal path convenient for diagnostic testing. This eliminates the need for an external loopback plug. The SP505 also includes a latch enable pin with the driver and receiver address decoder. Tri-state ability for the driver and receiver outputs is controlled by supplying a 4-bit word into the address decoder. Seven (7) drivers and one (1) receiver in the SP505 include separate enable pins for added convenience. The SP505 is ideal for WAN serial ports in networking equipment such as routers, switches, DSU/CSU's, and other access devices.

V.35

EIA-530

WAN

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ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

VCC............................................................................+7V

Input Voltages:

Logic...............................-0.3V to (VCC+0.5V)

Drivers............................-0.3V to (VCC+0.5V)

Receivers........................................±15.5V

Output Voltages:

Logic................................-0.3V to (VCC+0.5V)

Drivers................................................±15V

STORAGE CONSIDERATIONS

Due to the relatively large package size of the 80-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order remove moisture prior to soldering. Sipex ships the 80-pin QFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.

Receivers........................-0.3V to (VCC+0.5V)

Storage Temperature..........................-65˚C to +150˚C

Power Dissipation.........................................2000mW

Package Derating:

øJA....................................................46 °C/W

øJC...................................................16 °C/W

SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

LOGIC INPUTS

2.0 Volts

LOGIC OUTPUTS

2.4 Volts I

V.28 DRIVER

DC Parameters

Outputs

Open Circuit Voltage +15 Volts per Figure 1 Loaded Voltage +5.0 +15 Volts per Figure 2 Short-Circuit Current +100 mA per Figure 4 Power-Off Impedance 300 Ω per Figure 5

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 1.5 µs per Figure 6; +3V to -3V Instantaneous Slew Rate 30 V/µs per Figure 3 Propagation Delay

PHL

PLH

Max.Transmission Rate 120 230 kbps

0.5 1 5 µs

0.8 Volts

0.4 Volts I

= –3.2mA

OUT

= 1.0mA

OUT

V.28 RECEIVER

DC Parameters

Inputs

Input Impedance 3 7 kΩ per Figure 7 Open-Circuit Bias +2.0 Volts per Figure 8 HIGH Threshold 1.7 3.0 Volts LOW Threshold 0.8 1.2 Volts

AC Parameters VCC = +5V for AC parameters

Propagation Delay

PHL

PLH

50 100 500 ns 50 100 500 ns

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SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

V.28 RECEIVER (continued)

AC Parameters (cont.)

Max.Transmission Rate 120 230 kbps

V.10 DRIVER

DC Parameters

Outputs

Open Circuit Voltage +4.0 +6.0 Volts per Figure 9 Test-Terminated Voltage 0.9V Short-Circuit Current +150 mA per Figure 11

Power-Off Current +100 µA per Figure 12

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 200 ns per Figure 13; 10% to 90% Propagation Delay

PHL

PLH

Max.Transmission Rate 120 kbps

50 100 500 ns 50 100 500 ns

V.10 RECEIVER

DC Parameters

Inputs

Input Current –3.25 +3.25 mA per Figures 14 and 15 Input Impedance 4 kΩ Sensitivity +0.3 Volts

AC Parameters VCC = +5V for AC parameters

Propagation Delay

PHL

PLH

Max.Transmission Rate 120 kbps

50 120 250 ns 50 120 250 ns

V.11 DRIVER

DC Parameters

Outputs

Open Circuit Voltage +5.0 Volts per Figure 16 Test Terminated Voltage +2.0 Volts per Figure 17

0.5V

Balance +0.4 Volts per Figure 17

0.67V

Offset +3.0 Volts per Figure 17 Short-Circuit Current +150 mA per Figure 18 Power-Off Current +100 µA per Figure 19

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 20 ns per Figures 21 and 36; 10% to 90% Propagation Delay

PHL

PLH

Differential Skew 10 20 ns per Figures 33 and 36, CL = 50pF

50 85 110 ns per Figures 33 and 36, CL = 50pF 50 85 110 ns per Figures 33 and 36, CL = 50pF

Max.Transmission Rate per Figure 33, CL = 50pF

SP505ACF 10 12 Mbps fIN = 5MHz SP505BCF 16.4 18 Mbps fIN = 8.2MHz

V.11 RECEIVER

DC Parameters

Inputs

Common Mode Range –7 +7 Volts Sensitivity +0.3 Volts

Volts per Figure 10

Volts

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SPECIFICATIONS

TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.

MIN. TYP. MAX. UNITS CONDITIONS

V.11 RECEIVER (continued)

DC Parameters (cont.)

Input Current –3.25 +3.25 mA per Figure 20 and 22 Current w/ 100Ω Termination +60.75 mA per Figure 23 and 24 Input Impedance 4 kΩ

AC Parameters VCC = +5V for AC parameters

Propagation Delay t

PHL

PLH

Differential Skew 20 ns per Figure 33; CL = 50pF Max.Transmission Rate per Figure 33; CL = 50pF

SP505ACF 10 12 Mbps fIN = 5MHz

SP505BCF 16.4 18 Mbps fIN = 8.2MHz

V.35 DRIVER

DC Parameters

Outputs

Open Circuit Voltage +1.20 Volts per Figure 16 Test Terminated Voltage +0.44 +0.66 Volts per Figure 25 Offset +0.6 Volts per Figure 25 Source Impedance 50 150 Ω per Figure 27; ZS = V2/V1 x 50Ω Short-Circuit Impedance 135 165 Ω per Figure 28

AC Parameters VCC = +5V for AC parameters

Outputs

Transition Time 30 40 ns per Figure 29; 10% to 90% Propagation Delay

PHL

PLH

Differential Skew 20 30 ns per Figures 33 and 36; CL = 20pF Max.Transmission Rate per Figure 33; CL = 20pF

SP505ACF 10 12 Mbps fIN = 5MHz

SP505BCF 16.4 18 Mbps fIN = 8.2MHz

V.35 RECEIVER

DC Parameters

Inputs

Sensitivity +80 mV Source Impedance 90 110 Ω per Figure 30; ZS = V2/V1 x 50Ω Short-Circuit Impedance 135 165 Ω per Figure 31

AC Parameters VCC = +5V for AC parameters

Propagation Delay t

PHL

PLH

Differential Skew 20 ns per Figure 33; CL = 20pF Max.Transmission Rate per Figure 33; CL = 20pF

SP505ACF 10 12 Mbps fIN = 5MHz

SP505BCF 16.4 18 Mbps fIN = 8.2MHz

TRANSCEIVER LEAKAGE CURRENTS

Driver Output 3-State Current 100 500 µA per Figure 32; Drivers disabled Rcvr Output 3-State Current 1 10 µA DECX = 0000, 0.4V ≤ VO ≤ 2.4V

80 110 130 ns per Figures 33 and 38; CL = 50pF 80 110 130 ns per Figures 33 and 38; CL = 50pF

50 90 110 ns per Figures 33 and 36; CL = 20pF 50 90 110 ns per Figures 33 and 36; CL = 20pF

80 110 130 ns per Figures 33 and 38; CL = 20pF 80 110 130 ns per Figures 33 and 38; CL = 20pF

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OTHER AC CHARACTERISTICS

TA = +25°C and VCC = +5.0V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28

; Tri-state to Output LOW 0.70 5.0 µsC

PZL

; Tri-state to Output HIGH 0.40 2.0 µsC

PZH

; Output LOW to Tri-state 0.20 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.40 2.0 µsC

PHZ

RS-423/V.10

; Tri-state to Output LOW 0.15 2.0 µsC

PZL

; Tri-state to Output HIGH 0.20 2.0 µsC

PZH

; Output LOW to Tri-state 0.20 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.15 2.0 µsC

PHZ

RS-422/V.11

; Tri-state to Output LOW 2.80 10.0 µsC

PZL

; Tri-state to Output HIGH 0.10 2.0 µsC

PZH

; Output LOW to Tri-state 0.10 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.10 2.0 µsC

PHZ

V.35

; Tri-state to Output LOW 2.60 10.0 µsC

PZL

; Tri-state to Output HIGH 0.10 2.0 µsC

PZH

; Output LOW to Tri-state 0.10 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.15 2.0 µsC

PHZ

RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28

; Tri-state to Output LOW 0.12 2.0 µsC

PZL

; Tri-state to Output HIGH 0.10 2.0 µsC

PZH

; Output LOW to Tri-state 0.10 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.10 2.0 µsC

PHZ

RS-423/V.10

; Tri-state to Output LOW 0.10 2.0 µsC

PZL

; Tri-state to Output HIGH 0.10 2.0 µsC

PZH

; Output LOW to Tri-state 0.10 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.10 2.0 µsC

PHZ

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 40; S

closed

= 100pF, Fig. 34 & 37; S

closed

= 100pF, Fig. 34 & 37; S

closed

= 15pF, Fig. 34 & 37; S

closed

= 15pF, Fig. 34 & 37; S

closed

= 100pF, Fig. 34 & 37; S

closed

= 100pF, Fig. 34 & 37; S

closed

= 15pF, Fig. 34 & 37; S

closed

= 15pF, Fig. 34 & 37; S

closed

= 100pF, Fig. 35 & 38; S

closed

= 100pF, Fig. 35 & 38; S

closed

= 100pF, Fig. 35 & 38; S

closed

= 100pF, Fig. 35 & 38; S

closed

= 100pF, Fig. 35 & 38; S

closed

= 100pF, Fig. 35 & 38; S

closed

= 100pF, Fig. 35 & 38; S

closed

= 100pF, Fig. 35 & 38; S

closed

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OTHER AC CHARACTERISTICS (Continued)

TA = +25°C and VCC = +5.0V unless otherwise noted.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-422/V.11

; Tri-state to Output LOW 0.10 2.0 µsC

PZL

; Tri-state to Output HIGH 0.10 2.0 µsC

PZH

; Output LOW to Tri-state 0.10 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.10 2.0 µsC

PHZ

V.35

; Tri-state to Output LOW 0.10 2.0 µsC

PZL

; Tri-state to Output HIGH 0.10 2.0 µsC

PZH

; Output LOW to Tri-state 0.10 2.0 µsC

PLZ

; Output HIGH to Tri-state 0.10 2.0 µsC

PHZ

TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 33, 36, 38) V.28 Driver 100 ns | (t

100 ns | (t

V.28 Receiver 20 ns | (t

20 ns | (t

V.11 Driver 2 ns | (t

2ns| (t

V.11 Receiver 3 ns | (t

3ns| (t

V.10 Driver 5 ns | (t

5ns| (t

V.10 Receiver 5 ns | (t

5ns| (t

V.35 Driver 4 ns | (t

4ns| (t

V.35 Receiver 6 ns | (t

6ns| (t

= 100pF, Fig. 35 & 39; S

closed

= 100pF, Fig. 35 & 39; S

closed

= 15pF, Fig. 35 & 39; S

closed

= 15pF, Fig. 35 & 39; S

closed

= 100pF, Fig. 35 & 39; S

closed

= 100pF, Fig. 35 & 39; S

closed

= 15pF, Fig. 35 & 39; S

closed

= 15pF, Fig. 35 & 39; S

closed

)

– (t

Tx1 Tx1

Rx1 Rx1

Tx1 Tx1

Rx1 Rx1

Tx2 Tx2

Rx2 Rx2

Tx1 Tx1

Rx1 Rx1

– (t

– (t – (t

)

phl

)

plh

phl phl

)

phl

)

plh

phl phl

)

phl

)

plh

phl phl

)

phl

)

plh

phl phl

phl

plh

phl phl

phl

plh

phl phl

phl

plh

phl phl

phl

plh

phl phl

)

) ) )

)

) ) )

)

) ) )

)

Tx6,7 Tx6,7

)

Rx2,7

)

Rx2,7

Tx6,7 Tx6,7

)

Rx2,7

)

Rx2,7

Tx3,4,5 Tx3,4,5

)

Rx3,4,5

)

Rx3,4,5

Tx6,7 Tx6,7

)

Rx2,7

)

Rx2,7

| |

| | |

| |

| | |

| |

POWER REQUIREMENTS

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

(No Mode Selected) 30 mA All ICC values are with V

(V.28/RS-232) 60 mA T = + 2 5oC, all drivers are loaded to

4.75 5.00 5.25 Volts

= +5V,

(V.11/RS-422) 300 mA their specified maximum load and all (RS-449) 250 mA drivers are active at their maximum (V.35) 105 mA specified data transmission rates. EIA-530 260 mA EIA-530A 250 mA V.36 65 mA

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TEST CIRCUITS...

3kΩ

Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage

Oscilloscope

7kΩ

Scope used for slew rate measurement.

Figure 3. V.28 Driver Output Slew Rate

VCC = 0V

Figure 5. V.28 Driver Output Power-Off Impedance

±2V

Figure 4. V.28 Driver Output Short-Circuit Current

3kΩ

2500pF

Oscilloscope

Figure 6. V.28 Driver Output Rise/Fall Times

Page 8

±15V

Figure 7. V.28 Receiver Input Impedance

3.9kΩ

Figure 9. V.10 Driver Output Open-Circuit Voltage

Figure 8. V.28 Receiver Input Open Circuit Bias

450Ω

Figure 10. V.10 Driver Output Test Terminated Voltage

= 0V

±0.25V

Figure 12. V.10 Driver Output Power-Off CurrentFigure 11. V.10 Driver Output Short-Circuit Current

Page 9

450Ω

Oscilloscope

±10V

Figure 13. V.10 Driver Output Transition Time

V.10 RECEIVER

+3.25mA

–3V–10V

+10V+3V

Maximum Input Current versus V oltage

–3.25mA

Figure 15. V.10 Receiver Input IV Graph

Figure 14. V.10 Receiver Input Current

OCA

3.9kΩ

OCB

Figure 16. V.11 and V.35 Driver Output Open-Circuit Voltage

50Ω

Figure 17. V.11 Driver Output Test Terminated Voltage Figure 18. V.11 Driver Output Short-Circuit Current

Page 10

= 0V

±0.25V

±10V

= 0V

Figure 19. V.11 Driver Output Power-Off Current

±0.25V

Figure 20. V.11 Receiver Input Current

±10V

V.11 RECEIVER

Oscilloscope

50Ω

–3V–10V

+3.25mA

+10V+3V

Maximum Input Current versus V oltage

–3.25mA

Figure 21. V.11 Driver Output Rise/Fall Time

Figure 22. V.11 Receiver Input IV Graph

Page 11

100Ω to 150Ω

V.11 RECEIVER

±6V

i [mA] = (V [V] – 3) / 4.0

w/ Optional Cable Termination

(100Ω to 150Ω)

i [mA] = V [V] / 0.1

–3V–6V

100Ω to 150Ω

±6V

Figure 23. V.11 Receiver Input Current w/ Termination

+6V+3V

i [mA] = (V [V] – 3) / 4.0

i [mA] = V [V] / 0.1

Maximum Input Current versus V oltage

Figure 24. V.11 Receiver Input Graph w/ Termination

50Ω

Figure 25. V.35 Driver Output Test Terminated Voltage

50Ω

Figure 26. V.35 Driver Output Offset Voltage

Figure 27. V.35 Driver Output Source Impedance

50Ω

24kHz, 550mV

p-p

Sine Wave

Page 12

50Ω

Oscilloscope

±2V

50Ω

Figure 28. V.35 Driver Output Short-Circuit Impedance

50Ω

24kHz, 550mV

p-p

Sine Wave

Figure 30. V.35 Receiver Input Source Impedance

Figure 29. V.35 Driver Output Rise/Fall Time

±2V

Figure 31. V.35 Receiver Input Short-Circuit Impedance

Any one of the two conditions for disabling the driver.

00 0

VCC = +5V

Logic “1”

Figure 32. Driver Output Leakage Current Test

DEC

±15V

ZSC

A B

(50% Duty Cycle, 2.5V

)

P-P

OUT

15pF

Figure 33. Driver/Receiver Timing Test Circuit

Page 13

Output

Under

Test

500Ω

Receiver

Output

Test Point

1KΩC

1KΩ

Figure 34. Driver Timing Test Load Circuit

– V

+3V

A +

–

DRIVER

INPUT

DRIVER

OUTPUT

DIFFERENTIAL

OUTPUT

SKEW = | tDPLH - tDPHL

Figure 36. Driver Propagation Delays

ENABLE

DEC

+3V

0V 5V

A, B

Figure 35. Receiver Timing Test Load Circuit

f > 5MHz; tR < 10ns; tF < 10ns

1.5V 1.5V

1/2V

PLH

DPLH

PHL

DPHL

f = 1MHz; tR ≤ 10ns; tF ≤ 10ns

1.5V 1.5V t

2.3V

Output normally LOW

Output normally HIGH

0.5V

1/2V

Figure 37. Driver Enable and Disable Times

f > 5MHz; tR < 10ns; tF < 10ns

A – B

RECEIVER OUT

SKEW = | tPHL - tPLH |

0D2

–

0D2

PLH

0V 0V

INPUT

OUTPUT

(VOH - VOL)/2

PHL

OH - VOL)/2

Figure 38. Receiver Propagation Delays

Page 14

+3V

DEC

RCVR

ENABLE

0V 5V

RECEIVER OUT

Figure 39. Receiver Enable and Disable Times

f = 1MHz; tR ≤ 10ns; tF ≤ 10ns

1.5V 1.5V t

1.5V

Output normally LOW

Output normally HIGH

0.5V

0.5V t

+3V

X or Tx_Enable

DEC

OUT

+3V

DECX or Tx_Enable

OUT

f = 60kHz; tR < 10ns; tF < 10ns

1.5V t

– .5V

Output LOW

f = 60kHz; tR < 10ns; tF < 10ns

1.5V

Output HIGH

VOH – .5V

1.5V t

– .5V

1.5V t

VOH – .5V

Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times

Page 15

- 0V

INPUT

- 0V

Figure 41. Typical V.28 Driver Output Waveform

Figure 43. Typical V.11 Driver Output Waveform

- 0V

OUTPUT

Figure 42. Typical V.10 Driver Output Waveform

INPUT

OUT

DIFF

OUT

Figure 44. Typical V.35 Driver Output Waveform

- 0V

Page 16

PINOUT…

RxD 1

SDEN

TREN

RSEN 4

LLEN

TTEN 6

SCTEN 7

LATCH 8

DEC

DTR 13

TxD 14 TxC 15

RTS 16

RL 17

RLEN 18

DCD 19

RxC 20

80 CTS

RI 21

79 SCT

ST 22

78 DSR

STEN 23

77 SCT(b)

76 SCT(a)

75 GND

74 VCC73 VCC72 GND

SP505

LL 24

Pin 61 — SD(a) — Analog Out — Send data, inverted; sourced from TxD.

Pin 63 — TT(a) — Analog Out — Terminal Timing, inverted; sourced from TxC

71 RD(b)

70 RD(a)

69 DM(b)

68 DM(a)

67 CS(b)

66 CS(a)

65 TT(b)

64 GND

63 TT(a)

62 VCC61 SD(a)

60 GND 59 SD(b) 58 TR(a) 57 GND 56 TR(b) 55 V 54 RS(a) 53 GND 52 RS(b) 51 LL(a) 50 GND 49 LL(b) 48 V 47 RL(a) 46 GND 45 RL(b) 44 ST(b) 43 GND 42 ST(a) 41 V

Pin 65 — TT(b) — Analog Out — Terminal Timing, non–inverted; sourced from TxC.

Pin 70 — RD(a) — Receive Data, analog input; inverted; source for RxD.

Pin 71 — RD(b) — Receive Data; analog input; non-inverted; source for RxD.

Pin 76 — SCT(a) — Serial Clock Transmit; analog input, inverted; source for SCT.

Pin 77 — SCT(b) — Serial Clock Transmit:

–

GND 29

GND 34

IC(a) 39

IC(b) 40

RT(a) 37

RT(b) 38

RR(a) 35

RR(b) 36

analog input, non–inverted; source for SCT Pin 79 — SCT — Serial Clock Transmit; TTL

output; sources from SCT(a) and SCT(b) inputs.

PIN ASSIGNMENTS… CLOCK AND DATA GROUP

Pin 1 — RxD — Receive Data; TTL output, sourced from RD(a) and RD(b) inputs.

Pin 14 — TxD — TTL input ; transmit data source for SD(a) and SD(b) outputs.

Pin 15 — TxC — Transmit Clock; TTL input for TT driver outputs.

Pin 20 — RxC — Receive Clock; TTL output sourced from RT(a) and RT(b) inputs.

Pin 22 — ST — Send Timing; TTL input; source for ST(a) and ST(b) outputs.

Pin 37 — RT(a) — Receive Timing; analog input, inverted; source for RxC.

Pin 38 — RT(b) — Receive Timing; analog input, non-inverted; source for RxC.

Pin 42 — ST(a) — Send Timing; analog output, inverted; sourced from ST.

Pin 44 — ST(b) — Send Timing; analog output, non-inverted; sourced from ST.

Pin 59 — SD(b) — Analog Out — Send data, non-inverted; sourced from TxD.

CONTROL LINE GROUP

Pin 13 — DTR — Data Terminal Ready; TTL input; source for TR(a) and TR(b) outputs.

Pin 16 — RTS — Ready To Send; TTL input; source for RS(a) and RS(b) outputs.

Pin 17 — RL — Remote Loopback; TTL input; source for RL(a) and RL(b) outputs.

Pin 19 — DCD— Data Carrier Detect; TTL output; sourced from RR(a) and RR(b) inputs.

Pin 21 — RI — Ring In; TTL output; sourced from IC(a) and IC(b) inputs.

Pin 24 — LL — Local Loopback; TTL input; source for LL(a) and LL(b) outputs.

Pin 35 — RR(a)— Receiver Ready; analog input, inverted; source for DCD.

Pin 36 — RR(b)— Receiver Ready; analog input, non-inverted; source for DCD.

Pin 39 — IC(a)— Incoming Call; analog input, inverted; source for RI.

Pin 40 — IC(b)— Incoming Call; analog input,non-inverted; source for RI.

Page 17

Pin 45 — RL(b) — Remote Loopback; analog output, non-inverted; sourced from RL.

Pin 7 — SCTEN — Enables SCT receiver; active high; TTL input.

Pin 47 — RL(a) — Remote Loopback; analog output inverted; sourced from RL.

Pin 49— LL(b) — Local Loopback; analog output, non-inverted; sourced from LL.

Pin 51 — LL(a) — Local Loopback; analog output, inverted; sourced from LL.

Pin 52 — RS(b) — Ready To Send; analog output, non-inverted; sourced from RTS.

Pin 54 — RS(a) — Ready To Send; analog output, inverted; sourced from RTS.

Pin 56 — TR(b) — Terminal Ready; analog output, non-inverted; sourced from DTR.

Pin 58 — TR(a) — Terminal Ready; analog output, inverted; sourced from DTR.

Pin 66 — CS(a)— Clear To Send; analog input, inverted; source for CTS.

Pin 67 — CS(b)— Clear To Send; analog input, non-inverted; source for CTS.

Pin 68 — DM(a)— Data Mode; analog input, inverted; source for DSR.

Pin 69 — DM(b)— Data Mode; analog input, non-inverted; source for DSR

Pin 78 — DSR— Data Set Ready; TTL output; sourced from DM(a), DM(b) inputs.

Pin 80 — CTS— Clear To Send; TTL output; sourced from CS(a) and CS(b) inputs.

Pin 8 — LATCH — Latch control for decoder bits (pins 9-12), active low. Logic high input will make decoder transparent.

Pins 12–9 — DEC0 – DEC3 — Transmitter and receiver decode register; configures transmitter and receiver modes; TTL inputs.

Pin 18 — RLEN — Enables RL driver; active low; TTL input.

Pin 23 — STEN — Enables ST driver; active low; TTL input.

POWER SUPPLIES

Pins 25, 33, 41, 48, 55, 62, 73, 74 — VCC — +5V input.

Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 — GND — Ground.

Pin 27 — VDD +10V Charge Pump Capacitor — Connects from VDD to VCC. Suggested capacitor size is 22µF, 16V.

Pin 32 — VSS –10V Charge Pump Capacitor — Connects from ground to VSS. Suggested capacitor size is 22µF, 16V.

Pins 26 and 30 — C Capacitor — Connects from C

gested capacitor size is 22µF, 16V. Pins 28 and 31 — C

Capacitor — Connects from C

gested capacitor size is 22µF, 16V.

and C

–

— Charge Pump

–

to C

. Sug-

–

. Sug-

–

— Charge Pump

CONTROL REGISTERS

Pins 2 — SDEN — Enables TxD driver, active low; TTL input.

Pins 3 — TREN — Enables DTR driver, active low; TTL input.

Pins 4 — RSEN — Enables RTS driver, active low; TTL input.

Pins 5 — LLEN — Enables LL driver, active low; TTL input.

Pin 6 — TTEN — Enables TT driver, active low; TTL input.

Page 18

FEATURES…

The SP505 is a highly integrated serial transceiver that allows software control of its interface modes. Similar to the SP504, the SP505 offers the same hardware interface modes for RS-232 (V.28), RS-422A (V.11), RS-449, RS485, V.35, EIA-530 and includes V.36 and EIA530A. The interface mode selection is done via a 4–bit switch for the drivers and receivers. The SP505 is fabricated using low–power BiCMOS process technology, and incorporates a Sipex– patented (5,306,954) charge pump allowing +5V only operation. Each device is packaged in an 80–pin JEDEC Quad FlatPack package.

The SP505 is ideally suited for wide area network connectivity based on the interface modes offered and the driver and receiver configurations. The SP505 has seven (7) independent drivers and seven (7) independent receivers. In V.35 mode, the SP505 includes the necessary components and termination resistors internal within the device for compliant V.35 operation.

THEORY OF OPERATION

The SP505 is made up of five separate circuit blocks — the charge pump, drivers, receivers, decoder and switching array. Each of these circuit blocks is described in more detail below.

A typical +10V charge pump would require external clamping such as 5V zener diodes on VDD and VSS to ground. The +5V output has symmetrical levels as in the +10V output. The +5V is used in the following modes where RS423 (V.10) are used: RS-449, EIA-530, EIA530A and V.36.

Phase 1 (±10V)

— VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to +5V. C then switched to ground and the charge on C transferred to C +5V, the voltage potential across capacitor C2 is

–

. Since C

is connected to

–

now 10V.

Phase 1 (±5V)

— VSS & VDD charge storage and transfer — With the C1 and C2 capacitors initially charged to +5V, C charge on C capacitor. Simultaneously the C ground and 5V charge on C the VDD storage capacitor.

is then switched to ground and the

–

is transferred to the VSS storage

–

is switched to

is transferred to

Charge–Pump

VCC = +5V

The SP505 charge pump is based on the SP504 design where Sipex's patented charge pump design (5,306,954) uses a four–phase voltage shifting technique to attain symmetrical 10V power supplies. The charge pump still requires external capacitors to store the charge. In addi-

–5V

+5V

––

–5V

–

Storage Capacitor

tion the SP504 charge pump supplies +10V or +5V on VSS and VDD depending on the mode of operation. There is a free–running oscillator

Figure 45. Charge Pump Phase 1 for +10V.

that controls the four phases of the voltage shifting. A description of each phase follows.

The SP505 charge pump is used for RS-232 where the output voltage swing is typically +10V and also used for RS-423. However, RS423 requires the voltage swing on the driver output be between +4V to +6V during an opencircuit (no load). The charge pump would need

VCC = +5V

–5V

+5V

––

–

Storage Capacitor

–

Storage Capacitor

to be regulated down from +10V to +5V.

Figure 46. Charge Pump Phase 1 for +5V.

Page 19

Phase 2 (±10V)

— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the V storage capacitor and the positive terminal of C

to ground, and transfers the generated –l0V or the generated –5V to C3. Simultaneously, the positive side of capacitor C 1 is switched to +5V and the negative side is connected to ground.

Phase 2 (±5V)

— VSS & VDD charge storage — C nected to VCC to recharge the C1 capacitor. C is switched to ground and C The 5V charge from Phase 1 is now transferred

–

is connected to C3.

is recon-

to the VSS storage capacitor. VSS receives a continuous charge from either C1 or C2. With the C1 capacitor charged to 5V, the cycle begins again.

Phase 3

— VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –5V in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C voltage potential across C2 is l0V. For the 5V output, C potential on C2 is only +5V.

is connected to ground so that the

is at +5V, the

Phase 4

— VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to ground and transfers the generated l0V or the generated 5V across C2 to C4, the VDD storage capacitor. Again, simultaneously with this, the positive side of capacitor C1 is switched to +5V and the negative side is connected to ground, and the cycle begins again.

Since both VDD and VSS are separately generated from VCC in a no–load condition, VDD and VSS will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design.

The clock rate for the charge pump typically operates at 15kHz. The external capacitors must be a minimum of 22µF with a 16V breakdown rating.

External Power Supplies

For applications that do not require +5V only, external supplies can be applied at the V+ and V– pins. The value of the external supply volt-

ages must be no greater than +l0.5V. The tolerance should be +5% from +10V. The current drain for the supplies is used for RS-232 and RS423 drivers. For the RS-232 driver, the current requirement will be 3.5mA per driver. The RS423 driver worst case current drain will be 11mA per driver. Power sequencing is required

for the SP505. The supplies must be sequenced accordingly: +10V, +5V and –10V. It is important to prevent VSS from starting up before V or VDD.

VCC = +5V

–10V

––

Figure 47. Charge Pump Phase 2 for +10V.

VCC = +5V

––

–5V

Figure 48. Charge Pump Phase 2 for +5V.

VCC = +5V

–5V

+5V

––

–5V

Figure 49. Charge Pump Phase 3.

VCC = +5V

+10V

––

Figure 50. Charge Pump Phase 4.

–

Storage Capacitor

VDD Storage Capacitor

Storage Capacitor

Page 20

Drivers

The SP505 has seven (7) enhanced independent drivers. Control for the mode selection is done via a four–bit control word. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line signal levels. Table 1 shows the mode of each driver in the different interface modes that can be selected.

There are four basic types of driver circuits — V.28, V.11, V.10 and V.35.

V.28 Drivers

The V.28 drivers output single–ended signals with a minimum of +5V (with 3kΩ & 2500pF loading), and can operate to at least 120kbps under full load. Since the SP505 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 drivers are used in RS-232 mode for all signals, and also in V.35 mode where four (4) drivers are used as the control line signals (DTR, RTS, LL, and RL).

V.10 Drivers

The V.10 (RS-423) drivers are also single– ended signals which produce open circuit V and VOH measurements of +4.0V to +6.0V.

When terminated with a 450Ω load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category II signals from each of their corresponding specifications.

V.11 Drivers

The third type of driver is a V.11 (RS-422) type differential driver. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain typically +2.2V differential output levels with a load of 100Ω. The signal levels and drive capability of these drivers allow the drivers to also support RS-485

requirements of ±1.5V minimum differential output levels with a 54Ω load. The driver is designed to operate over a common mode range of +12V to -7V, which follows the RS-485 specification. This also covers the +7V to -7V common mode range for V.11 (RS-422) requirements. The V.11 drivers are used in RS449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data signals.

V.35 Drivers

The fourth type of driver is the V.35 driver. These drivers were specifically designed to comply with the requirements of V.35. Unique to the industry, the Sipex's V.35 driver architecture used in the SP505 does not need external termination resistors to operate and comply with V.35. This simplifies existing V.35 implementations that use external termination schemes. The V.35 drivers can produce +0.55V driver output signals with minimum deviation (maximum 20%) given an equivalent load of 100Ω. With the help of internal resistor networks, the drivers achieve the 50Ω to 150Ω source impedance and the 135Ω to 165Ω short-circuit impedance for V.35. The V.35 driver is disabled and transparent when the decoder is in all other modes. All of the differential drivers; V.11 (RS-

422) and V.35, can operate over 10Mbps.

Driver Enable and Input

All the drivers in the SP505 contain individual enable lines which can tri-state the driver outputs when a logic "1" is applied. This simplifies half-duplex configurations for some applications and also provides simpler DTE/DCE flexibility with one integrated circuit.

The driver inputs are both TTL or CMOS compatible. Each driver input should have a pull-down or pull-up resistor so that the output will be at a defined state. Unused driver inputs should not be left floating.

Receivers

The SP505 has seven (7) independent receivers which can be programmed for the different interface modes. Control for the mode selection is done via a 4–bit control word, which is the same as the driver's 4-bit control word. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous

Page 21

serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line receivers. Table 2 shows the mode of each receiver in the different interface modes that can be selected.

There are three basic types of receiver circuits — V.28, V.10, and V.11.

V.28 Receivers

The V.28 receiver is single–ended and accepts V.28 signals from the V.28 driver. The V.28 receiver has an operating voltage range of +15V and can receive signals down to +3V. The input sensitivity complies with RS-232 and V.28 specifications at +3V. The input impedance is 3kΩ to 7kΩ in accordance to RS-232 and V.28 over a +15V input range. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic "1" and a +0.8V maximum for a logic "0". V.28 receivers are used in RS-232 mode for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The V.28 receivers can operate to at least 120kbps.

V.10 Receivers

The V.10 receivers are also single–ended as with the V.28 receivers but have an input threshold as low as +200mV. The input impedance is guaranteed to be greater than 4KΩ, with an operating voltage range of +7V. The V.10 receivers can operate to at least 120kbps. V.10 receivers are used in RS-449, EIA-530, EIA530A and V.36 modes as Category II signals as indicated by their corresponding specifications.

V.11 Receivers

The third type of receiver is a differential which supports V.11 and RS-485 signals. This receiver has a typical input impedance of 10kΩ and a typical differential threshold of +200mV, which complies with the V.11 specification. Since the characteristics of the V.11 receivers are actually subsets of RS-485, the V.11 receivers can accept RS-485 signals. However, these receivers cannot support 32-transceivers on the signal bus due to the lower input impedance as specified in the RS-485 specification. Three receivers (RxD, RxC, and SCT) include a typical 120Ω cable termination resistor across the A and B inputs. The resistor for the three receivers

is switched on when the SP505 is configured in a mode which uses V.11 receivers. The V.11 cable termination resistor is switched off when the receiver is disabled or in another operating mode not using V.11 receivers. The V.11 receivers are used in X.21, RS-449, EIA-530, EIA-530A and V.36 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential receivers can receive signals over 10Mbps.

V.35 Receiver

The V.11 receivers are also used for the V.35 mode. Unlike the older implementations of differential receivers used for V.35, the SP505 contains an internal resistor termination network that ensures a V.35 input impedance of 100Ω (+10Ω) and a short-circuit impedance of 150Ω (+15Ω). The traditional V.35 implementations required external termination resistors to achieve the proper V.35 impedances. The internal network is connected via low on-resistance FET switches when the decoder is changed to V.35 mode. These FET switches can accept input signals of up to +15V without any forward biasing and other parasitic affects. The V.35 termination resistor network is switched off when the receiver is disabled either by the decoder or receiver enable pin. The termination network is transparent when all other modes are selected. The V.35 receivers can operate over 10Mbps.

To Inverting Input of Receiver

V.11 TERMINATION

MODE [0100]

To Non-Inverting Input of Receiver

Figure 51. Simplified RIN Termination Circuit

= 20Ω

= 1Ω

51Ω

124Ω

51Ω

RIN [a]

V.35 MODE

= 1Ω

[b]

Receiver Enable and Output

Only one receiver includes an enable line. The SCTEN input for the SCT receiver can enable or tri-state the output of the receiver. When the pin is at a logic "0", the receiver output is high impedance and any input termination internal connected is switched off. The inputs will be at approximately 10kΩ during tri-state.

Page 22

All receivers include a fail-safe feature that outputs a logic "1" when the receiver inputs are open. The differential receivers allocated for data and clock signals (RxD, RxC, and SCT) have advanced fail-safe that outputs a logic "1" when the inputs are either open, shorted, or terminated. Other discrete or integrated implementations require external pull-up and pulldown resistors to define the receiver output state. For single-ended V.28 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high ("1") at the receiver outputs. The single-ended V.10 receivers produce a logic LOW ("0") on the output when the inputs are open. This is due to an internal pullup device connected to the input. The differential receivers have the same internal pull-up device on the non-inverting input which produces a logic HIGH ("1") at the receiver output, representing an "OFF" state to the HDLC controller. The three differential receivers when configured in V.35 mode (RxD, RxC & SCT) will also include fail-safe even when the internal termination resistor network is connected and the inputs are either shorted or floating.

Decoder

The SP505 has the ability to change the interface mode of the drivers or receivers via a 4–bit switch. The decoder for the drivers and receivers can be latched through a control pin.

The SP505 contains internal loopback capabili- ties for self-diagnostic tests. Loopback is enabled through the decoder. To initiate singleended mode loopback, the decoder word is 1010. To initiate differential mode loopback, the decoder word is 1011. The minimum transmission rates into the SP505 under loopback conditions are 120kbps for single-ended mode and 5Mbps for differential mode. The driver outputs are tristated and the receiver inputs are disabled during loopback. The receiver input impedance during loopback is approximately 10kΩ.

The SP505 is equipped with a latch control for the four (4) decoder bits. The latch control pin is pin 8 of the SP505. The latch control is active low, a logic low on pin 8 will latch the decoder signals. A logic "1" on pin 8 will force the latch to be transparent to the user. A pulse width of at least 30ns is required to latch the decoder for the next mode. The resultant output is typically 600ns after the latch control pin is toggled assuming that the decoder word is set.

NET1/2 & TBR2 European Compliancy

As with all of Sipex's previous multi-protocol serial transceiver ICs, the drivers and receivers have been designed to meet all the requirements to NET1/2. The SP505 is internally tested to all the NET1/2 physical layer testing parameters and the ITU Series V specifications.

The control word can be latched either high or low to write the appropriate code into the SP505. The codes shown in Tables 1 and 2 are the only specified, valid modes for the SP505. Undefined codes may represent other interface modes

With the emergence of ETSI TBR2 (Technical Basis for Regulation) document now in place as an alternative for European compliancy, Sipex has tested the SP505 to TBR2 specifications to

ensure "CE" approval for either testing method. not specified (consult the factory for more information). The drivers and receivers are controlled with the data bits labeled DEC3–DEC0. All of the drivers outputs and receiver outputs can be put into tri-state mode by writing 0000 to the driver decode switch. All internal termina-

The SP505 was externally tested by TUV

Telecom Services, Division of TUV Rheinland,

and passed both NET1/2 and TBR2 require-

ments. Test reports (NET2/052101/98 for NET1/2 and CTR2/

05101/98 for TBR2) can be furnished upon request.

tion networks are switched off during this mode. Individual tri-state capability is possible for all drivers through each driver's own enable control input. The SCT receiver also contains an individual enable input. When this control pin is

Please note that although the SP505 adheres to

NET1/2 testing; any complex or unusual con-

figuration should be double-checked to ensure

NET compliance. Consult factory for details. disabled (logic "0"), the V.11 and V.35 input termination is deactivated. The 0000 decoder word will override the enable control line for the one receiver (SCT).

Page 23

SP505 Driver Mode Selection

RS422

V.11– V.11+ V.11– V.11+

V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+

w/ Term.

0101

V.11–

V.11+

V.11–

V.11+

V.11–

V.11+

V.11–

V.11+

V.11–

V.11+ V.11–

V.11– V.11+ V.11– V.11+ tri-state V.11– V.11+ V.10

tri-state

V.10

tri-state

V.11–

V.11+ V.11+

V.11– V.11+

1100 1101 1111

V.11– V.11+ V.11– V.11+ V.11–

V.11+ V.11– V.11+

V.10

tri-state

tri-state V.11– V.11+

V.11– V.11+

Pin Label Mode: RS232 V.35 RS422 RS449 EIA530 EIA-530A DEC – DEC

SD(a) tri-state SD(b) TR(a) tri-state

0000 0010 1110 0100

tri-state

V.28

tri-state

V.28

V.35– V.35+

V.28 TR(b) tri-state tri-state tri-state RS(a) tri-state

V.28 V.11–

V.28 RS(b) tri-state tri-state tri-state RL(a) tri-state RL(b) tri-state

LL(a) tri-state

LL(b) tri-state ST(a) tri-state ST(b)

tri-state TT(a) tri-state TT(b)

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.28

tri-state

V.35– V.35+ V.35– V.35+

Table 1. SP505 Driver Decoder Table

SP505 Receiver Mode Selection

Pin Label

DEC – DEC

RD(a) RD(b) RT(a) RT(b) CS(a) CS(b) DM(a) DM(b) RR(a) RR(b) IC(a) IC(b)

SCT(a) SCT(b)

Table 2. SP505 Receiver Decoder Table

Mode: RS232 V.35 RS422

w/ Term.

RS422 RS449 EIA530 EIA-530A

0000 0010 1110 0100 0101 1100 1101 1111

>10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND

>10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND >10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28 V.11–

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>12kΩ to GND

V.35– V.35+

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.28

>10kΩ to GND

V.35– V.35+

V.11– V.11+ V.11– V.11+

V.11– V.11+

V.11+ V.11– V.11+ V.11– V.11+

V.11– V.11+

V.11–

120Ω

V.11+ V.11–

120Ω

V.11+ V.11– V.11+

V.11–

V.11+

V.11– V.11+ V.11–

V.11+ V.11–

120Ω

V.11+

V.11– V.11+ V.11– V.11+

V.11– V.11+ V.11– V.11+ V.11– V.11+

V.10

>10kΩ to GND >10kΩ to GND

V.11– V.11+

V .11–

120Ω

V .11+

V.11– V.11+

120Ω

V.11– V.11+ V.11– V.11+ V.11– V.11+

V.10

V .11–

120Ω

V .11+

120Ω

V .11– V .11+ V .11– V .11+

>10kΩ to GND

V .11– V .11+

V.11– V.11+

V.10

V.11– V.11+ V.11– V.11+

V.10

V.11– V.11+ V.11– V.11+

V.11– V.11+

V.10

V.11– V.11+

V.10

V.36

0110

V.11– V.11+

tri-state

V.11– V.11+ V.11– V.11+

V.36

0110

V .11–

120Ω

V .11+ V .11–

120Ω

V .11+

>10kΩ to GND

V .11–

120Ω

V .11+

V.10

120Ω

V.10

120Ω

Page 24

(SEE PINOUT FOR VCC PINS)

RS-422 Mode Input Word

+5V

10µF

1N5819

25 26

VCCV

22µF

C1+

Charge Pump

22µF

C1-

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM (b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

IC(b) 40

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

LATCH

(SEE PINOUT ASSIGNMENTS FOR GROUND PINS)

MODE

DECODER LATCH

SP505

2830

C2+

22µF

C2-

22µF

14 TxD 61 SD(a) 59 SD(b) 2 SDEN

13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN

17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

A — Receiver Tri-State circuitry,

V.11, & V.35 ter mination resistor circuitry (RxD, RxC & SCT).

B — Driver Tri-State circuitry &

V.35 termination circuitry (TxD, TxC & ST).

Figure 52. SP505 Typical Operating Circuit

Page 25

RD(a) 70

RxD 1

RT(a) 37

RxC 20

CS(a) 66

CTS 80

DM(a) 68

DSR 78

MODE: RS-232 (V.28)

DRIVER/RECEIVER

DEC

DEC2 DEC1 DEC

0 0 1 0

14 TxD 61 SD(a)

2 SDEN 13 DTR

58 TR(a)

3 TREN 16 RTS

54 RS(a)

4 RSEN 17 RL

47 RL(a)

18 RLEN

RR(a) 35

DCD 19

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

24 LL 51 LL(a)

5 LLEN 22 ST

42 ST(a)

23 STEN 15 TxC

63 TT(a)

6 TTEN

RECEIVERS DRIVERS

Figure 53. Mode Diagram — RS-232

Page 26

MODE: V.35

DRIVER/RECEIVER

DEC

DEC2 DEC1 DEC

1 1 1 0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

DM(a) 68

DSR 78

RR(a) 35

DCD 19

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

V.35 Ntwk

RECEIVERS DRIVERS

V.35 Ntwk

V.35 NtwkV.35 Ntwk

14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR

58 TR(a)

3 TREN 16 RTS

54 RS(a)

4 RSEN 17 RL

47 RL(a)

18 RLEN 24 LL

51 LL(a)

5 LLEN 22 ST

42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

Figure 54. Mode Diagram — V.35

Page 27

MODE: RS-422

[w/ termination]

DRIVER/RECEIVER

DEC2 DEC1 DEC

DEC

0 1 0 0

RD(a) 70

RxD 1

RD(b) 71 RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM(b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

IC(b) 40

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

120Ω

RECEIVERS DRIVERS

14 TxD 61 SD(a) 59 SD(b) 2 SDEN

13 DTR 58 TR(a) 56 TR(b) 3 TREN

16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN

24 LL 51 LL(a) 49 LL(b)

5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

Figure 55. Mode Diagram — RS-422

Page 28

MODE: RS-449

DRIVER/RECEIVER

DEC

DEC2 DEC1 DEC

1 1 0 0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM(b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7 SCT(b) 77

120Ω

120Ω120Ω

RECEIVERS DRIVERS

14 TxD 61 SD(a) 59 SD(b) 2 SDEN

13 DTR 58 TR(a) 56 TR(b) 3 TREN

16 RTS 54 RS(a) 52 RS(b) 4 RSEN

17 RL

47 RL(a)

18 RLEN 24 LL

51 LL(a)

5 LLEN 22 ST

42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

Figure 56. Mode Diagram — RS-449

Page 29

MODE: RS-422

[no termination]

DRIVER/RECEIVER

DEC

DEC2 DEC1 DEC

0 1 0 1

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

DM(b) 69

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

IC(b) 40

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

14 TxD 61 SD(a) 59 SD(b) 2 SDEN

13 DTR 58 TR(a) 56 TR(b) 3 TREN

16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN

24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

RECEIVERS DRIVERS

Figure 57. Mode Diagram — RS-422 w/o termination

Page 30

MODE: EIA-530

DRIVER/RECEIVER

DEC

DEC2 DEC1 DEC

1 1 0 1

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78 DM(b) 69 RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

120Ω

120Ω120Ω

RECEIVERS DRIVERS

14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN

16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL

51 LL(a)

5 LLEN 22 ST

42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

Figure 58. Mode Diagram — EIA-530

Page 31

MODE: EIA-530A

DRIVER/RECEIVER

DEC

DEC2 DEC1 DEC

1 1 1 1

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78

RR(a) 35

DCD 19

RR(b) 36

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

120Ω

120Ω120Ω

RECEIVERS DRIVERS

14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR

58 TR(a)

3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN

17 RL 47 RL(a) 45 RL(b) 18 RLEN

24 LL 51 LL(a)

5 LLEN 22 ST

42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

Figure 59. Mode Diagram — EIA-530A

Page 32

MODE: V.36

DRIVER/RECEIVER

DEC

DEC2 DEC1 DEC

0 1 1 0

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

DM(a) 68

DSR 78

RR(a) 35

DCD 19

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

SCT(b) 77

120Ω

120Ω120Ω

RECEIVERS DRIVERS

14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR

58 TR(a)

3 TREN 16 RTS

54 RS(a)

4 RSEN 17 RL

47 RL(a)

18 RLEN 24 LL

51 LL(a)

5 LLEN 22 ST

42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

Figure 60. Mode Diagram — V.36

Page 33

LOOPBACK MODE...

The SP505 is equipped with two loopback modes. Single-ended loopback internally connects V.28 driver outputs to V.28 receiver inputs. The signal path is non-inverting and will support data rates up to 120kbps. The propagation delay times are as specified in the electrical specifications. To initiate a single-ended loopback, the code "1010" should be written to the driver decoder. Differential loopback is implemented by applying "1011" to the driver decoder. This internally connects V.11 driver

MODE:

Single-Ended Loopback

DRIVER/RECEIVER

DEC2 DEC1 DEC

DEC

RD(a) 70

RxD 1

RT(a) 37

RxC 20

CS(a) 66

CTS 80

DM(a) 68

DSR 78

RR(a) 35

DCD 19

IC(a) 39

RI 21

SCT(a) 76

SCT 79

SCTEN 7

1 0 1 0

RECEIVERS DRIVERS

14 TxD 61 SD(a)

2 SDEN 13 DTR

58 TR(a)

3 TREN 16 RTS

54 RS(a)

4 RSEN 17 RL

47 RL(a)

18 RLEN 24 LL

51 LL(a)

5 LLEN 22 ST

42 ST(a)

23 STEN 15 TxC

63 TT(a)

6 TTEN

outputs to V.11 receiver inputs. The signal path again is non-inverting; the differential loopback data rate can be at least 5Mbps.

Under loopback conditions the receiver decoder is disabled. While the SP505 is in either singleended or differential loopback mode, the driver outputs are tri-stated and the receiver inputs are disabled.

MODE:

Differential Loopback

DRIVER/RECEIVER

DEC2 DEC1 DEC

DEC

RD(a) 70

RxD 1

RD(b) 71

RT(a) 37

RxC 20

RT(b) 38

CS(a) 66

CTS 80

CS(b) 67

DM(a) 68

DSR 78 DM(b) 69 RR(a) 35

DCD 19 RR(b) 36

IC(a) 39

RI 21

IC(b) 40

SCT(a) 76

SCT 79

SCTEN 7 SCT(b) 77

1 0 1 1

RECEIVERS DRIVERS

14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN

17 RL 47 RL(a) 45 RL(b)

18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN

Mode Driver Output Receiver Input Driver Receiver

non-inverting inverting non-inverting inverting Input Output

Loopback

DEC=1010 DEC=1011

tri-state tri-state >10KΩ to GND >10KΩ to GND active active tri-state tri-state >10KΩ to GND >10KΩ to GND active active

Power down clamped

VCC=VDD=VSS=0V

tri-state tri-state >10KΩ to GND >10KΩ to GND inactive at ±0.6V

Tri-state

DEC=0000

tri-state tri-state >10KΩ to GND >10KΩ to GND inactive tri-state

Page 34

PIN 1

PACKAGE: QUAD FLATPACK

JEDEC "BE-2" OUTLINE

D D1

0.3" RAD. TYP.

0.2" RAD. TYP.

0.009"/0.015" (0.220/0.380)

0.02559"/– (0.65/–)

DIMENSIONS in Inches

Minimum/Maximum

(mm)

0°–7°

Seating

Plane

JEDEC BE-2 Outline

80–PIN

–/0.0925

(–/2.350)

–/0.010

(–/0.250)

0.667/0.687

(16.950/17.450)

0.547/0.555

(13.900/14.100)

0.667/0.687

(16.950/17.450)

0.547/0.555

(13.900/14.100)

0.0255/0.0375 (0.650/0.950)

0.005/0.009" (0.13/0.23)

10°-16°

6°±4°

10°-16°

Page 35

Model Temperature Range Package Types

ORDERING INFORMATION

SP505ACF ........................................................................0°C to +70°C ......................................................... 80–pin JEDEC (BE-2 Outline) QFP

SP505BCF ........................................................................0°C to +70°C ......................................................... 80–pin JEDEC (BE-2 Outline) QFP

Please consult the factory for pricing and availability on a Tape-On-Reel option.

Corporation

SIGNAL PROCESSING EXCELLENCE

Sipex Corporation Headquarters and

Sales Office

22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com

Sales Office

233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Datasheet SP505ACF, SP505BCF Datasheet (Sipex Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual