Datasheet MT093AE, MT093AP, MT093AC, SP5055SMP Datasheet (MITEL)

SP5055

2.6GHz Bidirectional I2C BUS Controlled Synthesiser

Supersedes version in April 1994 Consumer IC Handbook, HB3120 - 2.0 DS2384 - 4.4 May 1996

The SP5055 is a single chip frequency synthesiser designed
for TV tuning systems. Control data is entered in the standard
I2C BUS format. The device contains 4 addressable current
limited outputs and 4 addressable Bi-Directional open collector
ports one of which is a 3 bit ADC. The information on these
ports can be read via the I2C BUS. The device has one fixed
I2C BUS address and 3 programmable addresses, programmed
by applying a specific input voltage to one of the current limited
outputs. This enables 2 or more synthesisers to be used in a
system.

FEATURES

■ Complete 2.6GHz Single Chip System

■ Programmable via I

■ Low power consumption (5V 65mA)

■ Low Radiation

■ Phase Lock Detector

■ Varactor Drive Amp Disable

■ 6 Controllable Outputs, 4 Bi-Directional

■ 5 Level ADC

■ Variable I

2

C BUS Address For Multi Tuner Applications

■ Full ESD Protection*

* Normal ESD handling procedures should be observed.

2

C BUS

Fig. 1 Pin connections – top view

APPLICATIONS

■ Satellite TV

■ High IF Cable Tuning Systems

ORDERING INFORMATION

SP5055S MP - (16 lead Miniature Plastic package)

SP5055

ELECTRICAL CHARACTERISTICS

T

amb

= -20°C to +80°C, VCC = +4.7V to 5.3V.
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient
temperature and supply voltage unless otherwise stated. Reference frequency = 4MHz unless otherwise stated.

VCC = 5V
500MHz to 2.6GHz Sinewave
120MHz, see Fig. 5

Input voltage = V

CC

Input voltage = 0V
When VCC = 0V

I

sink

= 3mA

Byte 4, bit 2 = 0, pin 1 = 2V
Byte 4, bit 2 = 1, pin 1 = 2V
Byte 4, bit 4 = 1, pin 1 = 2V
V

pin 16

= 0·7V

V

OUT

= 12V

V

OUT

= 13·2V

V

OUT

= 0.7V

V

OUT

= 13·2V

V

pin 10

= 13.2V

V

pin 10

= 0V

See Table 3 for ADC Levels

Supply current
Prescaler input voltage
Prescaler input voltage

Prescaler input impedance
Prescaler input capacitance

SDA, SCL

Input high voltage
Input low voltage
Input high current
Input low current
Leakage current

SDA

Output voltage

Charge pump current low
Charge pump current high
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance

Output Ports

P0, P3 sink current
P0, P3 leakage current
P4-P7 sink current
P4-P7 leakage current

Input Ports

P3 input current high
P3 input current low
P4,P5,P7 input voltage low
P4,P5,P7 input voltage high
P6 input current high
P6 input current low

12
13, 14
13, 14

13, 14

4, 5
4, 5
4, 5
4, 5
4, 5

4
1

1
1

16

2
2

10, 11
10, 11

9-6
9-6

10

10

9,8,6
9,8,6

7
7

Typ.

Value

Conditions

Characteristic Pin

50

100

3
0

500

10

750

0.7

10

2.7

65

50

2

±50

±170

6400

80

1

80
300
300

5.5

1.5
10

-10
10

0.4

±5

200

1.5
10

10

+10

-10

0.8

+10

-10

Units

Min. Max.

mA

mV

RMS

mV

RMS

Ω

pF

V

V
µA
µA
µA

V
µA

µA
nA
µA

Ω

mVp-p

Ω

mA

µA

mA

µA

µA
µA

V

V
µA
µA

2

SP5055

FUNCTIONAL DESCRIPTION

The SP5055 is programmed from an I2C BUS. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I2C BUS format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
Tables in Fig. 3 illustrate the format of the data. The device
can be programmed to respond to several addresses, which
enables the use of more than one synthesiser in an I2C Bus
system. Table 4 shows how the address is selected by
applying a voltage to P3. The last bit of the address byte
(R/W) sets the device into read mode if it is high and write
mode if it is low. When the SP5055 receives a correct address
byte it pulls the SDA line low during the acknowledge period
and during following acknowledge periods after further data
bytes are programmed. When the SP5055 is programmed
into the read mode the controlling device accepting the data
must pull down the SDA line during the following acknowledge
period to read another status byte.

WRITE MODE (FREQUENCY SYNTHESIS)

When the device is in the write mode Bytes 2 + 3 select the
synthesised frequency while bytes 4 + 5 select the output port
states and charge pump information.

Once the correct address is received and acknowledged,
the first Bit of the next Byte determines whether that byte is
interpreted as byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data bytes can be entered without the need to
re-address the device until an I2C stop condition is recognised.
This allows a smooth frequency sweep for fine tuning or AFC
purposes.

If the transmission of data is stopped mid-byte (i.e., by
another device on the bus) then the previously programmed
byte is maintained.

Frequency data from bytes 2 and 3 is stored in a 15-bit shift
register and is used to control the division ratio of the 15-bit
programmable divider which is preceded by a divide-by-16
prescaler and amplifier to give excellent sensitivity at the local
oscillator input; see Fig 5. The input impedance is shown in
Fig 7.

The programmed frequency can be calculated by
multiplying the programmed division ratio by 16 times the
comparison frequency F

comp

.

When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the
programmable divider is frequency and phase locked to the
comparison frequency.

The reference frequency may be generated by an external
source capacitively coupled into pin 2 or provided by an on­board 4MHz crystal controlled oscillator.

Note that the comparison frequency is 7·8125kHz when a
4MHz reference is used.

Bit 2 of byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for ±170µA and
a logic 0 for ±50µA, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of byte 4 (T0) disables the
charge pump if set to a logic 1. Bit 8 of byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P6 and P7, a logic
1 connects F

comp

to P6 and F

div

to P7.

Byte 5 programs the output ports P0 to P7; on a logic 0 for
a high impedance output, logic 1 for low impedance (on).

READ MODE

When the device is in the read mode the status data read from
the device on the SDA line takes the form shown in Table 2.

Bit 1 (POR) is the power-on reset indicator and is set to a logic
1 if the power supply to the device has dropped below 3V and the
programmed information lost (e.g., when the device is initially
turned on). The POR is set to 0 when the read sequence is
terminated by a stop command. The outputs are all set to high
impedance when the device is initially powered up. Bit 2 (FL)
indicates whether the device is phase locked, a logic 1 is present
if the device is locked and a logic 0 if the device is unlocked.

Fig. 2 Block diagram

3

SP5055

A0

0
1
0
1
0

Voltage input to P6

0.6V

CC

to 13.2V

0·45VCC to 0·6V

CC

0·3VCC to 0·45V

CC

0·15VCC to 0·3V

CC

0 to 0.15V

CC

Bits 3, 4 and 5 (I2,I1,I0) show the status of the I/O Ports P7,
P5 and P4 respectively. A logic 0 indicates a low level and a logic
1 a high level. If the ports are to be used as inputs they should
be programmed to a high impedance state (logic 1). These
inputs will then respond to data complying with TTL type voltage
levels. Bits 6, 7 and 8 (A2,A1,A0) combine to give the output of
the 5 level ADC.

The 5 level ADC can be used to feed AFC information to
the microprocessor from the IF section of the receiver, as
illustrated in the typical application circuit.

APPLICATION

A typical Application is shown in Fig. 4. All input/output
interface circuits are shown in Fig. 6.

Table 1 Write data format (MSB transmitted first)

Byte 1
Byte 2
Byte 3
Byte 4
Byte 5

Address
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits

1

2

14

2

6

CP
P6

0

2

13

2

5

T1

P5

0

2

12

2

4

T0

P4

0

2

11

2

3

1

P3

MA0

2

9

2

1

1
X

MA1

2

10

2

2

1
X

A
A
A
A
A

MSB

1
0

2

7

1

P7

LSB

0

2

8

2

0

OS

P0

Table 2 Read data format (MSB is transmitted first)

Byte 1
Byte 2

Address
Status byte

1FL0I20I10

I0

MA0

A1

MA1

A2

A
A

1

POR

1

A0

A : Acknowledge bit
MA1, MA0 : Variable address bits (see Table 4)
CP : Charge Pump current select
T1 : Test mode selection
T0 : Charge pump disable
OS : Varactor drive Output disable Switch
P7, P6, P5, P4, : Control output states
P3, P0
POR : Power On Reset indicator
FL : Phase lock detect flag
I2, I1, I0 : Digital information from Ports P7, P5 and P4, respectively
A2, A1, A0 : 5 Level ADC data from P6 (see Table 3)
X : Don't care

Table 4 Address selection

MA0

0
1
0
1

MA1

0
0
1
1

Voltage input to P3

0V to 0·2V

CC

Always valid

0·3VCC to 0·7V

CC

0·8VCC -13.2V

A1

0
1
1
0
0

A2

1
0
0
0
0

Table 3 ADC levels

Fig. 3 Data formats

4

SP5055

APPLICATION

A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6.

Fig. 5 Typical input sensitivity

Fig. 4 Typical application

5

SP5055

Fig. 6 SP5055 Input/output interface circuits

6

SP5055

ABSOLUTE MAXIMUM RATINGS

All voltages are referred to VEE and pin 3 at 0V

Parameter

Fig. 7 Typical input impedance

Min.

Value

Max.

Pin

Units

Conditions

Supply voltage
RF input voltage

Port voltage

Total port output current
RF input DC offset

Charge pump DC offset
Drive DC offset
Crystal oscillator DC offset
SDA, SCL input voltage

Storage temperature
Junction temperature
MP 16 Thermal resistance, chip-to-ambient

MP 16 Thermal resistance, chip-to-case
Power consumption at 5.5V

12

13, 14

6-11
6-9

10, 11
6-11

13, 14

1

16

2

4, 5

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

-55

7

2.5

14

6

14

50

VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3

VCC+0.3

5.5
+125
+150

111

41

440

V

Vp-p

V

V

V

mA

V
V
V
V

V

V
°C
°C

°C/W

°C/W

mW

Port in off state
Port in on state
Port in on state

With VCC applied
VCC not applied

All ports off

7

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