The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
D
Quad Bus Buffers
D
3-State Outputs
D
Separate Control for Each Channel
description
These bus buffers feature three-state outputs
that, when enabled, have the low impedance
characteristics of a TTL output with additional
drive capability at high logic levels to permit
driving heavily loaded bus lines without external
pullup resistors. When disabled, both output
transistors are turned off, presenting a
high-impedance state to the bus so the output will
act neither as a significant load nor as a driver. The
’125 and ’LS125A devices’ outputs are disabled
when G
outputs are disabled when G is low.
is high. The ’126 and ’LS126A devices’
SN54125, SN54126, SN54LS125A,
SN54LS126A . . . J OR W PACKAGE
SN74LS125A, SN74LS126A . . . D, N, OR NS PACKAGE
SN74125, SN74126 ...N PACKAGE
(TOP VIEW)
1G, 1G*
2G, 2G
GND
*G
on ’125 and ’LS125A devices;
G on 126 and ’LS126A devices
SN54LS125A, SN54LS126A . . . FK PACKAGE
1Y
NC
2G, 2G
*
NC
2A
1
1A
2
1Y
3
*
4
2A
5
2Y
6
7
(TOP VIEW)
1A
1G, 1G*
3212019
4
5
6
7
8
910111213
14
13
12
11
10
9
8
NC
V
CC
4G, 4G*
4A
4Y
3G, 3G
3A
3Y
CC
4G, 4G*
V
18
17
16
15
14
*
4A
NC
4Y
NC
3G, 3G
*
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
3Y
NC
3A
2Y
GND
*G on ’125 and ’LS125A devices;
G on 126 and ’LS126A devices
NC – No internal connection
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
Page 2
SN54125, SN54126, SN54LS125A, SN54LS126A,
PDIP
N
LS125A
0°C to 70°C
SOIC
D
LS126A
SOP
NS
CDIP
J
55°C to 125°C
.
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
ORDERING INFORMATION
T
A
–
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
TubeSN74LS125ANSN74LS125AN
TubeSN74LS126ANSN74LS126AN
TubeSN74LS125AD
Tape and reelSN74LS125ADR
TubeSN74LS126AD
Tape and reelSN74LS126ADR
Tape and reelSN74LS125ANSR74LS125A
Tape and reelSN74LS126ANSR74LS126A
TubeSN54LS125AJSN54LS125AJ
TubeSNJ54LS125AJSNJ54LS125AJ
ORDERABLE
PART NUMBER
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
TOP-SIDE
MARKING
’125, ’LS125A
G
AY
’126, ’LS126A
G
AY
Y = A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
schematics (each gate)
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
CONTROL
INPUT G
DATA
INPUT A
CONTROL
INPUT G
4 k
’125 CIRCUITS
V
CC
85
4 k
W
2.5 k
W
1.6 k
W
4 k
W
2.5 k
W
1.6 k
W
1 k
625
W
4 k
W
W
W
OUTPUT Y
GND
’126 CIRCUITS
V
2.5 k
4.25 k
W
W
W
4 k
W
2.5 k
W
1 k
W
4 k
85
W
W
CC
OUTPUT Y
1.6 k
W
DATA
INPUT A
1.6 k
W
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
625
W
GND
†
(’125 and ’126)
Supply voltage, V
Input voltage, V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
VIL = 0.7 V,IOL = 12 mA0.250.4
VIL = 0.8 V,IOL = 12 mA0.250.4
VIL = 0.8 V,IOL = 24 mA0.350.5
=
IL
=
IL
VO = 2.4 V20
VO = 0.4 V–20
VO = 2.4 V20
VO = 0.4 V–20
’LS125A11201120
’LS126A12221222
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
SN54LS125A
SN54LS126A
MINNOMMAXMINNOMMAX
SN54LS125A
SN54LS126A
MIN TYP‡MAXMIN TYP‡MAX
SN74LS125A
SN74LS126A
SN74LS125A
SN74LS126A
UNIT
UNIT
V
µ
switching characteristics, VCC = 5 V, T
PARAMETERTEST CONDITIONS
t
6
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
=
=
=
,
,
,
= 25°C (see Figure 1)
A
SN54LS125A
SN74LS125A
p
= 45
p
= 45
p
= 5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS126A
SN74LS126A
915915
718818
12201625
15252135
2025
2025
UNIT
Page 7
.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
V
CC
R
L
(see Note B)
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
SERIES 54/74 DEVICES
V
From Output
Under Test
(see Note A)
CC
V
CC
R
L
Test
Point
C
L
From Output
Under Test
(see Note A)
Test
R
Point
C
L
L
S1
(see Note B)
1 kΩ
S2
FOR 2-STATE TOTEM-POLE OUTPUTS
High-Level
Low-Level
In-Phase
(see Note D)
Out-of-Phase
(see Note D)
NOTES: A. CL includes probe and jig capacitance.
LOAD CIRCUIT
Pulse
Pulse
Input
t
PLH
Output
t
PHL
Output
PROPAGATION DELAY TIMES
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
1.5 V1.5 V
t
w
1.5 V1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V1.5 V
1.5 V1.5 V
1.5 V1.5 V
VOLTAGE WAVEFORMS
, t
PLH
PHL
t
PHL
t
PLH
, t
FOR OPEN-COLLECTOR OUTPUTS
PHZ
LOAD CIRCUIT
3 V
0 V
V
OH
V
OL
V
OH
V
OL
, and t
PLZ
Timing
Input
Data
Input
Output
Control
(low-level
enabling)
t
PZL
Waveform 1
(see Notes C
and D)
t
PZH
Waveform 2
(see Notes C
and D)
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
; S1 is open and S2 is closed for t
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.5 V
t
su
1.5 V1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
; S1 is closed and S2 is open for t
PZH
3 V
0 V
t
h
3 V
0 V
3 V
0 V
t
PLZ
≈1.5 V
VOL + 0.5 V
V
OL
t
PHZ
V
OH
VOH – 0.5 V
≈1.5 V
.
PZL
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
SN54125, SN54126, SN54LS125A, SN54LS126A,
.
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
From Output
Under Test
(see Note A)
Test
Point
C
L
V
CC
R
(see Note B)
V
CC
L
R
L
From Output
Under Test
(see Note A)
C
L
Test
Point
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
V
CC
From Output
Under Test
(see Note A)
Test
R
Point
C
L
L
S1
(see Note B)
5 kΩ
S2
FOR 2-STATE TOTEM-POLE OUTPUTS
High-Level
Low-Level
In-Phase
(see Note D)
Out-of-Phase
(see Note D)
NOTES: A. CL includes probe and jig capacitance.
LOAD CIRCUIT
Pulse
Pulse
Input
t
PLH
Output
t
PHL
Output
PROPAGATION DELAY TIMES
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
JM38510/32301B2AACTIVELCCCFK201TBDPOST-PLATE N / A for Pkg Type
JM38510/32301BCAACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
JM38510/32301BDAACTIVECFPW141TBDA42N / A for Pkg Type
JM38510/32301SCAACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
JM38510/32301SDAACTIVECFPW141TBDA42N / A for Pkg Type
SN54126JOBSOLETECDIPJ14TBDCall TICall TI
SN54LS125AJACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
SN74125NOBSOLETEPDIPN14TBDCall TICall TI
SN74125N3OBSOLETEPDIPN14TBDCallTICall TI
SN74126NOBSOLETEPDIPN14TBDCall TICall TI
SN74LS125ADACTIVESOICD1450Green (RoHS &
SN74LS125ADBRACTIVESSOPDB142000 Green (RoHS &
SN74LS125ADBRE4ACTIVESSOPDB142000 Green (RoHS &
SN74LS125ADBRG4ACTIVESSOPDB142000 Green (RoHS &
SN74LS125ADE4ACTIVESOICD1450Green (RoHS &
SN74LS125ADG4ACTIVESOICD1450Green (RoHS &
SN74LS125ADRACTIVESOICD142500 Green (RoHS &
SN74LS125ADRE4ACTIVESOICD142500 Green (RoHS &
SN74LS125ADRG4ACTIVESOICD142500 Green (RoHS &
SN74LS125ANACTIVEPDIPN1425Pb-Free
SN74LS125AN3OBSOLETEPDIPN14TBDCallTICall TI
SN74LS125ANE4ACTIVEPDIPN1425Pb-Free
SN74LS125ANSRACTIVESONS142000 Green (RoHS &
SN74LS125ANSRE4ACTIVESONS142000 Green (RoHS &
SN74LS125ANSRG4ACTIVESONS142000 Green (RoHS &
SN74LS126ADACTIVESOICD1450Green (RoHS &
SN74LS126ADE4ACTIVESOICD1450Green (RoHS &
SN74LS126ADG4ACTIVESOICD1450Green (RoHS &
SN74LS126ADRACTIVESOICD142500 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
4-Jun-2007
(3)
Addendum-Page 1
Page 11
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
SN74LS126ADRE4ACTIVESOICD142500 Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-1-260C-UNLIM
4-Jun-2007
(3)
no Sb/Br)
SN74LS126ADRG4ACTIVESOICD142500 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
SN74LS126AJOBSOLETECDIPJ14TBDCall TICall TI
SN74LS126ANACTIVEPDIPN1425Pb-Free
CU NIPDAUN / A for Pkg Type
(RoHS)
SN74LS126ANE4ACTIVEPDIPN1425Pb-Free
CU NIPDAUN / A for Pkg Type
(RoHS)
SN74LS126ANSRACTIVESONS142000 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
SN74LS126ANSRE4ACTIVESONS142000 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
SN74LS126ANSRG4ACTIVESONS142000 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
SNJ54126JOBSOLETECDIPJ14TBDCall TICall TI
SNJ54126WOBSOLETECFPW14TBDCall TICall TI
SNJ54LS125AFKACTIVELCCCFK201TBDPOST-PLATE N / A for Pkg Type
SNJ54LS125AJACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
SNJ54LS125AWACTIVECFPW141TBDA42N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
Page 18
Page 19
Page 20
Page 21
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150