Datasheet SN74126AN Specification

Page 1
.
The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
D
D
3-State Outputs
D
Separate Control for Each Channel
description
These bus buffers feature three-state outputs that, when enabled, have the low impedance characteristics of a TTL output with additional drive capability at high logic levels to permit driving heavily loaded bus lines without external pullup resistors. When disabled, both output transistors are turned off, presenting a high-impedance state to the bus so the output will act neither as a significant load nor as a driver. The ’125 and ’LS125A devices’ outputs are disabled when G outputs are disabled when G is low.
is high. The ’126 and ’LS126A devices’
SN54125, SN54126, SN54LS125A,
SN54LS126A . . . J OR W PACKAGE
SN74LS125A, SN74LS126A . . . D, N, OR NS PACKAGE
SN74125, SN74126 ...N PACKAGE
(TOP VIEW)
1G, 1G*
2G, 2G
GND
*G
on ’125 and ’LS125A devices;
G on 126 and ’LS126A devices
SN54LS125A, SN54LS126A . . . FK PACKAGE
1Y
NC
2G, 2G
*
NC
2A
1
1A
2
1Y
3
*
4
2A
5
2Y
6 7
(TOP VIEW)
1A
1G, 1G*
3212019
4 5 6 7 8
910111213
14 13 12 11 10
9 8
NC
V
CC
4G, 4G* 4A 4Y 3G, 3G 3A 3Y
CC
4G, 4G*
V
18 17 16 15 14
*
4A NC 4Y NC 3G, 3G
*
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
3Y
NC
3A
2Y
GND
*G on ’125 and ’LS125A devices; G on 126 and ’LS126A devices NC – No internal connection
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
Page 2
SN54125, SN54126, SN54LS125A, SN54LS126A,
PDIP
N
LS125A
0°C to 70°C
SOIC
D
LS126A
SOP
NS
CDIP
J
55°C to 125°C
.
SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
ORDERING INFORMATION
T
A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
logic diagram (each gate)
PACKAGE
CFP – W Tube SNJ54LS125AW SNJ54LS125AW LCCC – FK Tube SNJ54LS125AFK SNJ54LS125AFK
Tube SN74LS125AN SN74LS125AN Tube SN74LS126AN SN74LS126AN Tube SN74LS125AD Tape and reel SN74LS125ADR Tube SN74LS126AD Tape and reel SN74LS126ADR Tape and reel SN74LS125ANSR 74LS125A Tape and reel SN74LS126ANSR 74LS126A Tube SN54LS125AJ SN54LS125AJ Tube SNJ54LS125AJ SNJ54LS125AJ
ORDERABLE
PART NUMBER
The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied
TOP-SIDE MARKING
’125, ’LS125A
G
AY
’126, ’LS126A
G
AY
Y = A
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Page 3
.
The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied
schematics (each gate)
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
CONTROL
INPUT G
DATA
INPUT A
CONTROL
INPUT G
4 k
125 CIRCUITS
V
CC
85
4 k
W
2.5 k
W
1.6 k
W
4 k
W
2.5 k
W
1.6 k
W
1 k
625
W
4 k
W
W
W
OUTPUT Y
GND
126 CIRCUITS
V
2.5 k
4.25 k
W
W
W
4 k
W
2.5 k
W
1 k
W
4 k
85
W
W
CC
OUTPUT Y
1.6 k
W
DATA
INPUT A
1.6 k
W
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
625
W
GND
(’125 and ’126)
Supply voltage, V Input voltage, V Package thermal impedance, θ Storage temperature range, T
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 2):N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
Page 4
SN54125, SN54126, SN54LS125A, SN54LS126A,
.
SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
schematics (each gate)
LS125A CIRCUITS
10 k
INPUT G
INPUT A
18 kW12 k
W
8 k
W
4 k
W
5 k
W
W
8 k
W
18 k
W
LS126A CIRCUITS
18 k
W
6 k
The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied
V
W
750
6 k
4 k
W
W
4 k
W
W
20 k
1.5 k
50
W
W
W
50
CC
OUTPUT
GND
W
V
CC
INPUT G
5 k
W
INPUT A
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
4 k
W
OUTPUT
GND
750
20 k
W
W
1.5 k
W
(’LS125A and ’LS126A)
Supply voltage, V Input voltage, V Package thermal impedance, θ
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 2):D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Page 5
TEST CONDITIONS
V
V
V
0.4
0.4
V
I
A
I
CC
mA
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
R
L
400 Ω
C
L
F
ns
R
L
400 Ω
C
L
F
ns
R
L
400 Ω
C
L
F
ns
.
The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
recommended operating conditions
V V V I I T
CC IH
IL OH OL
A
SN54125 SN54126
MIN NOM MAX MIN NOM MAX
Supply voltage 4.5 5 5.5 4.75 5 5.25 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V High-level output current –2 –5.2 mA Low-level output current 16 16 mA Operating free-air temperature –55 125 0 70 °C
SN74125 SN74126
UNIT
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54125
PARAMETER
V
IK
OH
OL
OZ
I
I
I
IH
I
IL
§
I
OS
CC
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be shorted at a time.
NOTE 3: Data inputs = 0 V; output control = 4.5 V for 125 and 0 V for ’126.
VCC = MIN, II = –12 mA –1.5 –1.5 V VCC = MIN, VIH = 2 V, IOH = –2 mA 2.4 3.3 VIL = 0.8 V IOH = –5.2 mA 2.4 3.1 VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOL = 16 mA VCC = MAX VIH = 2 V, VO = 2.4 V 40 40 VIL = 0.8 V VO = 0.4 V –40 –40 VCC = MAX, VI = 6.5 V 1 1 mA VCC = MAX, VI = 2.4 V 40 40 µA VCC = MAX, VI = 0.4 V –1.6 –1.6 mA VCC = MAX –30 –70 –28 –70 mA
VCC = MAX (see Note 3)
TEST CONDITIONS
125 32 54 32 54126 36 62 36 62
SN54126
MIN TYP‡MAX MIN TYP‡MAX
SN74125 SN74126
UNIT
µ
switching characteristics, VCC = 5 V, T
PARAMETER TEST CONDITIONS
t t t t t t
PLH PHL PZH PZL PHZ PLZ
=
=
=
,
,
,
= 25°C (see Figure 1)
A
SN54125 SN74125
p
= 50
p
= 50
p
= 5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN54126 SN74126
8 13 8 13
12 18 12 18 11 17 11 18
16 25 16 25
5 8 10 16 7 12 12 18
UNIT
5
Page 6
SN54125, SN54126, SN54LS125A, SN54LS126A,
TEST CONDITIONS
V
V
V
IH
V
V
0.7 V
I
CC
,
A
V
0.8 V
I
I
CC
mA
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
R
L
667 Ω
C
L
F
ns
R
L
667 Ω
C
L
F
ns
R
L
667 Ω
C
L
F
ns
.
SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
recommended operating conditions
V V V I
OH
I
OL
T
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 4: Data inputs = 0 V; output control = 4.5 V for LS125A and 0 V for ’LS126A.
Supply voltage 4.5 5 5.5 4.75 5 5.25 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.7 0.8 V
IL
High-level output current –1 –2.6 mA Low-level output current 12 24 mA Operating free-air temperature –55 125 0 70 °C
A
PARAMETER
V
IK
OH
V
OL
OZ
I
I
I
IH
IL
§
I
OS
CC
VCC = MIN, II = –18 mA –1.5 –1.5 V VCC = MIN, VIL = 0.7 V, IOH = –1 mA 2.4 VIH = 2 V VIL = 0.8 V IOH = –2.6 mA 2.4
VCC = MIN,
= 2
V
= MAX,
VIH = 2 V,
VCC = MAX, VI = 7 V 0.1 0.1 mA VCC = MAX, VI = 2.7 V 20 20 µA VCC = MAX, ’LS125A-G inputs –0.2 –0.2 mA VI = 0.4 V LS125A-A inputs; LS126A All inputs –0.4 –0.4 mA VCC = MAX –40 –225 –40 –225 mA
VCC = MAX (see Note 4)
TEST CONDITIONS
VIL = 0.7 V, IOL = 12 mA 0.25 0.4 VIL = 0.8 V, IOL = 12 mA 0.25 0.4 VIL = 0.8 V, IOL = 24 mA 0.35 0.5
=
IL
=
IL
VO = 2.4 V 20 VO = 0.4 V –20 VO = 2.4 V 20 VO = 0.4 V –20
LS125A 11 20 11 20LS126A 12 22 12 22
The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied
SN54LS125A SN54LS126A
MIN NOM MAX MIN NOM MAX
SN54LS125A SN54LS126A
MIN TYP‡MAX MIN TYP‡MAX
SN74LS125A SN74LS126A
SN74LS125A SN74LS126A
UNIT
UNIT
V
µ
switching characteristics, VCC = 5 V, T
PARAMETER TEST CONDITIONS
t
6
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
=
=
=
,
,
,
= 25°C (see Figure 1)
A
SN54LS125A SN74LS125A
p
= 45
p
= 45
p
= 5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN54LS126A SN74LS126A
9 15 9 15 7 18 8 18
12 20 16 25 15 25 21 35
20 25 20 25
UNIT
Page 7
.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
V
CC
R
L
(see Note B)
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
SERIES 54/74 DEVICES
V
From Output
Under Test
(see Note A)
CC
V
CC
R
L
Test Point
C
L
From Output
Under Test
(see Note A)
Test
R
Point
C
L
L
S1
(see Note B)
1 k
S2
FOR 2-STATE TOTEM-POLE OUTPUTS
High-Level
Low-Level
In-Phase
(see Note D)
Out-of-Phase
(see Note D)
NOTES: A. CL includes probe and jig capacitance.
LOAD CIRCUIT
Pulse
Pulse
Input
t
PLH
Output
t
PHL
Output
PROPAGATION DELAY TIMES
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for t E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
, t
PLH
PHL
t
PHL
t
PLH
, t
FOR OPEN-COLLECTOR OUTPUTS
PHZ
LOAD CIRCUIT
3 V
0 V
V
OH
V
OL
V
OH
V
OL
, and t
PLZ
Timing
Input
Data
Input
Output
Control
(low-level
enabling)
t
PZL
Waveform 1
(see Notes C
and D)
t
PZH
Waveform 2
(see Notes C
and D)
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
; S1 is open and S2 is closed for t
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
; S1 is closed and S2 is open for t
PZH
3 V
0 V
t
h
3 V
0 V
3 V
0 V
t
PLZ
1.5 V VOL + 0.5 V
V
OL
t
PHZ
V
OH
VOH – 0.5 V 1.5 V
.
PZL
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7
Page 8
SN54125, SN54126, SN54LS125A, SN54LS126A,
.
SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
From Output
Under Test
(see Note A)
Test
Point
C
L
V
CC
R
(see Note B)
V
CC
L
R
L
From Output
Under Test
(see Note A)
C
L
Test Point
The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied
V
CC
From Output
Under Test
(see Note A)
Test
R
Point
C
L
L
S1
(see Note B)
5 k
S2
FOR 2-STATE TOTEM-POLE OUTPUTS
High-Level
Low-Level
In-Phase
(see Note D)
Out-of-Phase
(see Note D)
NOTES: A. CL includes probe and jig capacitance.
LOAD CIRCUIT
Pulse
Pulse
Input
t
PLH
Output
t
PHL
Output
PROPAGATION DELAY TIMES
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 Ω, tr 1.5 ns, tf 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
, t
PLH
PHL
t
PHL
t
PLH
, t
FOR OPEN-COLLECTOR OUTPUTS
PHZ
LOAD CIRCUIT
3 V
0 V
V
OH
V
OL
V
OH
V
OL
, and t
PLZ
Timing
Input
Data
Input
Output
Control
(low-level
enabling)
t
PZL
Waveform 1
(see Notes C
and D)
t
PZH
Waveform 2
(see Notes C
and D)
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
; S1 is open and S2 is closed for t
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V
t
su
1.3 V 1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.3 V 1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
; S1 is closed and S2 is open for t
PZH
3 V
0 V
t
h
3 V
0 V
3 V
0 V
t
PLZ
1.5 V VOL + 0.5 V
V
OL
t
PHZ
V
OH
VOH – 0.5 V 1.5 V
.
PZL
Figure 2. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Page 9
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Page 10
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device Status
JM38510/32301B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type JM38510/32301BCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type JM38510/32301BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type JM38510/32301SCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type JM38510/32301SDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN54126J OBSOLETE CDIP J 14 TBD Call TI Call TI
SN54LS125AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SN74125N OBSOLETE PDIP N 14 TBD Call TI Call TI
SN74125N3 OBSOLETE PDIP N 14 TBD CallTI Call TI
SN74126N OBSOLETE PDIP N 14 TBD Call TI Call TI
SN74LS125AD ACTIVE SOIC D 14 50 Green (RoHS &
SN74LS125ADBR ACTIVE SSOP DB 14 2000 Green (RoHS &
SN74LS125ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &
SN74LS125ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &
SN74LS125ADE4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74LS125ADG4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74LS125ADR ACTIVE SOIC D 14 2500 Green (RoHS &
SN74LS125ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
SN74LS125ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
SN74LS125AN ACTIVE PDIP N 14 25 Pb-Free
SN74LS125AN3 OBSOLETE PDIP N 14 TBD CallTI Call TI
SN74LS125ANE4 ACTIVE PDIP N 14 25 Pb-Free
SN74LS125ANSR ACTIVE SO NS 14 2000 Green (RoHS &
SN74LS125ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
SN74LS125ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
SN74LS126AD ACTIVE SOIC D 14 50 Green (RoHS &
SN74LS126ADE4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74LS126ADG4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74LS126ADR ACTIVE SOIC D 14 2500 Green (RoHS &
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
4-Jun-2007
(3)
Addendum-Page 1
Page 11
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
(2)
SN74LS126ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
4-Jun-2007
(3)
no Sb/Br)
SN74LS126ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br) SN74LS126AJ OBSOLETE CDIP J 14 TBD Call TI Call TI SN74LS126AN ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
SN74LS126ANE4 ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
SN74LS126ANSR ACTIVE SO NS 14 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS126ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS126ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54126J OBSOLETE CDIP J 14 TBD Call TI Call TI
SNJ54126W OBSOLETE CFP W 14 TBD Call TI Call TI
SNJ54LS125AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LS125AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SNJ54LS125AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Page 12
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
Page 13
PACKAGE MATERIALS INFORMATION
www.ti.com
Device Package Pins Site Reel
Diameter
(mm)
SN74LS125ADBR DB 14 MLA 330 16 8.2 6.6 2.5 12 16 Q1
SN74LS125ADR D 14 MLA 330 16 6.5 9.0 2.1 8 16 Q1
SN74LS125ANSR NS 14 MLA 330 16 8.2 10.5 2.5 12 16 Q1
SN74LS126ADR D 14 MLA 330 16 6.5 9.0 2.1 8 16 Q1
SN74LS126ANSR NS 14 MLA 330 16 8.2 10.5 2.5 12 16 Q1
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
16-Jul-2007
Pin1
Quadrant
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
SN74LS125ADBR DB 14 MLA 346.0 346.0 33.0
SN74LS125ADR D 14 MLA 346.0 346.0 33.0
SN74LS125ANSR NS 14 MLA 346.0 346.0 33.0
SN74LS126ADR D 14 MLA 346.0 346.0 33.0
SN74LS126ANSR NS 14 MLA 346.0 346.0 33.0
Pack Materials-Page 2
Page 14
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Pack Materials-Page 3
Page 15
Page 16
Page 17
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
24
19
20
21
22
23
25
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342 (8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358 (9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307 (7,80)
0.406
(10,31)
0.495
(12,58)
0.495
(12,58)
0.850 (21,6)
1.047 (26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358 (9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858 (21,8)
1.063 (27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
Page 18
Page 19
Page 20
Page 21
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38 0,22
15
14
A
0,05 MIN
0,15
5,60 5,00
M
8,20 7,40
Seating Plane
0,10
0,25 0,09
0°ā8°
Gage Plane
0,25
0,95 0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Page 22
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