Datasheet SM9103M Datasheet (NPC)

SM9103M

NIPPON PRECISION CIRCUITS—1

NIPPON PRECISION CIRCUITS INC.

DVDRAM Head Amplifier LSI

OVERVIEW

The SM9103M is a photodiode photoelectric cur­rent-to-voltage conversion head amplifier LSI for
optical disk pickups in DVDRAM/DVDROM equip­ment. It sums the photodiode current data signals and
then converts the signals to a differential signal for
output. The output tracking servo and focusing servo
signals are derived from built-in sum and difference
circuits, and the gain for these servo signals can be
adjusted using serial interface controls. Each of the
signals from the photodiodes, used to generate DPD
(Differential Phase Detection) tracking servo signal,
is current-to-voltage converted and then also output.
It operates from a single 5 V supply, and is available
in 36-pin plastic SSOP packages.

FEATURES

■

RAM/ROM gain switching, low-noise RF signal
generator (differential output)

■

ROM tracking DPD signal output

■

Variable-gain RAM tracking push-pull signal out­put

■

Address signal, high-speed push-pull signal output

■

Variable-gain focus error signal output

■

Tracking PD sum signal output

■

Focus PD sum signal output

■

Offset correction timing output (logic)

■

Temperature monitor function

■

Serial interface to control internal parameter set­tings

■

Sleep-mode function

■

Single 5 V supply

■

36-pin plastic SSOP

TYPICAL APPLICATIONS

■

Double-speed DVDROM equipment

■

Double-speed DVDRAM equipment

ORDERING INFORMATION

PINOUT

36-pin SSOP

(Top view)

Device Package

SM9103M 36-pin SSOP

1MODE
2WRITE
3DGND
4DVCC
5TEMPO
6TEMPI
7T1
8T2

9T3
10T4
11F1
12F2
13AGND
14VREF
15FSUBB
16FSUB
17FADDB
18FADD 19 AGND

20 AVCC

21 DPDD

22 DPDC

23 DPDB

24 DPDA

25 DATAN

26 DATAP

27 TSUBB

28 TSUB

29 CAPAN

30 CAPAP

31 TADDB

32 TADD

33 CALREQ

34 SENB

35 SDATA

36 SCLK

SM9103M

NPC

SM9103M

NIPPON PRECISION CIRCUITS—2

PACKAGE DIMENSIONS

(Unit: mm)

BLOCK DIAGRAM

2.44 to 2.64

0.85

15.20 to 15.40

7.40 to 7.60

0.29 to 0.39

0.80

0.10 to 0.30

0.51 to 1.01

10.11 to 10.51

0.63 ± 0.10

7°

0 to 8°

0.23 to 0.32

7°

0.51 ± 0.20 45°

R0.63 to 0.89

A
B
C
D

A+B+C+D
(A+B)-(C+D)

DATAP
DATAN

TADDB
TADD

CAPAP
CAPAN
TSUBB
TSUB

DPDA
DPDB
DPDC
DPDD

CALREQ
FSUB
FSUBB

FADDB
FADD

F2

F1

AGND

AVCC

TEMPO

TEMPI

T4

T3

T2

T1

WRITE

MODE

SDATA

SENB

SCLK

VREF

to each block

Serial interface

Gain switching

amplifier

(RAM read/write,

ROM read)

Analog

Signal

processor

Offset canceller

Thermal sensor

Canceller control

Offset canceller

Gain switching

amplifier

Differential
output buffer

Amplifier

Gain switch
(2dB step)

Buffer
Buffer
Buffer
Buffer

Differential
output buffer

Gain switch
(2dB step)

Amplifier

Analog

Signal

processor

+5V

+5V

DGND

DVCC

SM9103M

NIPPON PRECISION CIRCUITS—3

PIN DESCRIPTION

Number Name I/O

1

1. I = input, Ipd = Input with built-in pull-down resistor, I/O = input/output, O = output

Function

1 MODE Ipd Mode switching/offset correction control input 1
2 WRITE Ipd Mode switching/offset correction control input 2
3 DGND – Logic circuit ground. Connect to the analog ground if there is no dedicated pickup or logic ground.
4 DVCC – Logic circuit supply. Connect to the analog supply if there is no dedicated pickup or logic supply.
5 TEMPO O Thermal sensor test output. Leave open for normal operation
6 TEMPI I Thermal sensor test input. Leave open for normal operation
7 T1 I Tracking PD input A
8 T2 I Tracking PD input B

9 T3 I Tracking PD input C
10 T4 I Tracking PD input D
11 F1 I Focus PD input E
12 F2 I Focus PD input F
13 AGND – Analog circuit ground
14 VREF I 2.0 V reference voltage input
15 FSUBB I Focus error signal feedback in put
16 FSUB O Focus error signal output
17 FADDB I Focus sum signal feedback input
18 FADD O Focus sum signal output
19 AGND – Analog circuit ground
20 AVCC – Analog circuit supply
21 DPDD O Buffered tracking signal output D for DPD servo
22 DPDC O Buffered tracking signal output C for DPD servo
23 DPDB O Buffered tracking signal output B for DPD servo
24 DPDA O Buffered tracking signal output A for DPD servo
25 DATAN O Phase-modulated data signal differential inverting output
26 DATAP O Phase-modulated data signal differential non-inverting output
27 TSUBB I Tracking push-pull signal feedback input
28 TSUB O Tracking push-pull signal output
29 CAPAN O ID data signal differential inverting output
30 CAPAP O ID data signal differential non-inverting output
31 TADDB I Tracking PD sum signal feedback input
32 TADD O Tracking PD sum signal output
33 CALREQ O Offset correction status/request output
34 SENB I Serial interface enable input
35 SDATA I/O Serial interface data input/acknowledge output
36 SCLK I Serial interface clock input

SM9103M

NIPPON PRECISION CIRCUITS—4

SPECIFICATIONS

Absolute Maximum Ratings

GND = 0 V

Recommended Operating Conditions

GND = 0 V

Parameter Symbol Condition Rating Unit

Supply voltage range V

CC

−

0.5 to 7.0 V

Input voltage range V

IN

−

0.5 to VCC + 0.5 V

Input current range I

IN

−

3.0 to +3.0 mA

Operating temperature range T

opr

0 to 70

°

C

Storage temperature range T

stg

−

40 to 125

°

C

Power dissipation P

D

250 mW

Soldering temperature T

sld

260

°

C

Soldering time t

sld

10 s

Parameter Symbol Condition Rating Unit

Specs-guaranteed supply voltage
range

V

CC

4.75 to 5.25 V

Operating supply voltage range V

CC

4.5 to 5.5 V

Reference voltage input V

REF

1.89 to 2.11 V

Operating temperature range T

opr

0 to 70

°

C

SM9103M

NIPPON PRECISION CIRCUITS—5

DC Electrical Characteristics

VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C

Tracking PD Input Characteristics (T1, T2, T3, T4)

VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C

Parameter Symbol Condition

Rating

Unit

min typ max

Current consumption

1

1. 18 kΩ resistor connected between TSUB and TSUBB
47 kΩ resistor connected between TADD and TADDB
22 kΩ resistor connected between FSUB and FSUBB
27 kΩ resistor connected between FADD and FADDB
SENB, SDATA, SCLK connected to GND; All other pins (excluding supply and ground pins) open circuit.

I

CC1

Operating mode – 2 4 30

mA

I

CC2

Sleep mode – – 1

MODE, WRITE, SENB, SDA TA, SCLK HIGH-level
input voltage

V

IH

0.8V

CC

––V

MODE, WRITE, SENB, SDATA, SCLK LOW-le v el
input voltage

V

IL

– – 0.2V

CC

V

MODE, WRITE HIGH-level input current I

IH1

VIN = V

CC

50 100 200 µA

SENB, SDATA, SCLK HIGH-level input current I

IH2

VIN = V

CC

––3µA

MODE, WRITE, SENB, SDATA, SCLK LOW-le v el
input current

I

IL

VIN = 0 V

−

3– –µA

CALREQ HIGH-level output voltage V

OH

IOH = −0.2 mA VCC − 0.2 – – V

CALREQ LOW-level output voltage V

OL1

IOL = 0.8 mA – – 0.4 V

SDATA LOW-level output voltage V

OL2

IOL = 7 mA – – 1.0 V

VREF input current I

REF

V

REF

= 2.0 V – – 250 µA

Parameter Condition

Rating

Unit

min typ max

Input impedance No signal – – 25 0

Ω

Input conversion noise current 100 kHz to 10 MHz

RAM read

1

1. DATAP − DATAN output difference operation when 10 pF capacitors are connected to T1, T2, T3, T4

– 0.035 –

µA

rms

ROM read

1

– 0.27 –

Pin voltage No signal – – 1.5 V

SM9103M

NIPPON PRECISION CIRCUITS—6

Data Signal Processor Characteristics

VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C

Parameter Condition

Rating

Unit

min typ max

DATAP−DATAN current-to-voltage
converter coefficient

1

1. [DATAP − DATAN] = K × [IT1 + IT2 + IT3 + IT4]

RAM read 10.0 12.5 15.0

k

Ω

ROM read 2.50 3.12 3.74

CAPAP−CAPAN current-to-voltage
converter coefficient

2

2. [CAPAP − CAPAN] = K × {[IT1 + IT2] − [IT3 + IT4]}

RAM read 11.3 14.1 16.9 k

Ω

DATAP, DATAN, CAPAP, CAPAN output
impedance

– – 100

Ω

DATAP, DATAN, CAPAP, CAPAN output
center voltage

3

3. 5 kΩ load connected to ground to prevent abnormal operation

No signal 0.9V

REF

– 1.1V

REF

V

CAPAP, CAPAN output center voltage
difference

3

No signal – – ±50 mV

DATAP, DATAN, CAPAP, CAPAN output
operating output voltage

10 kΩ load, output center voltage reference

−

0.7 – +0.7 V

Variable coefficient switching time RAM ↔ ROM read – – 10 ms
Saturation output reset time

4

4. Converging to within final value ± 10%

RAM write → RAM read – – 500 ns

DATAP, DATAN signal bandwidth

5

5. 10 pF input load capacitors connected to T1, T2, T3, T4. DATAP, DATAN, CAPAP, CAPAN output load conditions shown below.

f = 100 kHz −3 dB frequency 19 – – MHz

CAPAP, CAPAN signal bandwidth

5

f = 100 kHz −3 dB frequency 20 – – MHz

DATAP−DATAN, CAPAP−CAPAN gain
peaking

5

f = 100 kHz −3 dB frequency

−

3 – +0.5 dB

DATAP−DATAN, CAPAP−CAPAN group
delay time

5

f = 1 to 10 MHz – – ±1.0 ns

0.01µF

0.01µF

5pF 5pF

5pF

5pF

10kΩ

DATAP

DATAN

0.01µF

0.01µF

10pF 5pF

10pF 5pF

10kΩ

CAPAP

CAPAN

SM9103M

NIPPON PRECISION CIRCUITS—7

Tracking Signal Processor Characteristics

VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C

Parameter Condition

Rating

Unit

min typ max

TSUB current-to-voltage converter
coefficient

1

RAM read

Rf = 18 kΩ,
V

OUT

= V

REF

± 0.8 V

10.64 11.95 13.26
k

Ω

ROM read 2.67 2.99 9.92
RAM write 1.78 1.99 2.20

TADD current-to-voltage converter
coefficient

2

RAM read

R

f

= 47 kΩ

27.82 31.25 34.68
kΩROM read 6.95 7.80 8.65

RAM write 4.63 5.20 5.77

DPDA, DPDB, DPDC, DPDD
current-to-voltage converter coefficient

3

RAM read 40.0 50.0 60.0

kΩ

ROM read 10.0 12.5 15.0

T1, T2, T3, T4 converter coefficient
relative error

TSUB output, RAM/ROM read – – ±2 %

TSUB, T ADD, DPDA, DPDB, DPDC,
DPDD output impedance

– – 100 Ω

TSUB operating output voltage 10 kΩ load connected to VREF 1 – 3 V
TAD D, DPDA, DPDB, DPDC, DPDD

operating output voltage

10 kΩ load connected to VREF V

REF

–3V

Converter coefficient switching time

RAM read ↔ ROM read – – 10 ms
RAM write ↔ RAM read – – 3 µs

TSUB, T ADD signal bandwidth

4

DC to −3 dB frequency 1 – – MHz

DPDA, DPDB, DPDC, DPDD signal
bandwidth

4

f = 100 kHz to −3 dB frequency 5 – – MHz

TSUB, T ADD gain peaking

4

f = 10 kHz to −3 dB frequency −3 – +0.5 dB

DPDA, DPDB, DPDC, DPDD gain
peaking

4

f = 100 kHz to −3 dB frequency −3 – +4.0 dB

TSUB phase response

4

@ f = 100 kHz – – 10 °

DPDA, DPDB, DPDC, DPDD group
delay

4

f = 1 to 5 MHz group delay differential
absolute value

––5

ns

Relative error between 4 pins – – 1.0

TSUB offset voltage

No input signal,
V

REF

reference,
post-correction,
Ta = 25°C,
Rf = 18 kΩ

RAM read/write max
gain

– – ±10.0

mV

RAM read, min to max
gain

– – ±26

RAM read/write
differential gain max.

––±4

ROM read,
gain min/max

– – ±100

TADD offset voltage

No input signal,
V

REF

reference

RAM read – – ±30

mV

ROM read – – ±300

DPDA, DPDB, DPDC, DPDD offset
voltage

No input signal,
V

REF

reference

RAM/ROM read −550 – +50 mV

TSUB offset voltage temperature
coefficient

R

f

= 18 kΩ – – ±0.4 mV/°C

TSUB variable gain range −16 – +14 dB
TSUB variable gain step width – 2 – dB

SM9103M

NIPPON PRECISION CIRCUITS—8

Focus PD Input Characteristics (F1, F2)

V

CC

= 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C

Focus Signal Processor Characteristics

V

CC

= 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C

TSUB gain switching absolute accuracy

V

OUT

= V

REF

±

0.8 V

−16 to +8 dB – – ±0.5
dB

+10 to +14 dB – – ±1.0

1. TSUB = K × {[I

T1

+ IT2] − [IT3 + IT4]}, gain = 0 dB

2. TADD = K × [IT1 + IT2 + IT3 + IT4]

3. DPDA = K × IT1, DPDB = K × IT2, DPDC = K × IT3, DPDD = K × I

T4

4. T1, T2, T3, T4: 10 pF input load capacitance
TSUB, T ADD, DPDA, DPDB, DPDC, DPDD: 10 pF output load capacitance
TSUB, T ADD: 10 kΩ load resistance
DPDA, DPDB, DPDC, DPDD: 100 kΩ load resistance

Parameter Condition

Rating

Unit

min typ max

Input impedance No signal – – 25 0 Ω

Input conversion noise current DC to 10 kHz

RAM read

1

1. Conversion from FSUB output noise value when 14 pF capacitors connected to F1 and F2

––24

nA

rms

ROM read

1

––96

RAM write

1

– – 150

Pin voltage No signal, V

REF

reference – – ±50 mV

Parameter Condition

Rating

Unit

min typ max

FSUB current-to-voltage converter
coefficient

1

RAM read

R

f

= 22 kΩ,

V

OUT

= V

REF

± 0.35 V

370 415 460

kΩROM read 94 105 116

RAM write 58 65 72

FADD current-to-voltage converter
coefficient

2

RAM read

Rf = 27 kΩ

223 250 277

kΩROM read 56.1 63 69.9

RAM write 35.6 40 44.1
F1, F2 converter coefficient relative error FSUB output, RAM/ROM read – – ±2 %
FSUB, FADD output impedance – – 100 Ω
FSUB operating output voltage 10 kΩ load connected to VREF 1 – 3 V
FADD operating output v oltage 10 kΩ load connected to VREF V

REF

–3V

Converter coefficient switching time

RAM read ↔ ROM read – – 10 ms

RAM write ↔ RAM read – – 3 µs
FSUB, FADD signal bandwidth

3

DC to −3 dB frequency 200 – – kH z
FSUB, FADD gain peaking

3

f = 10 kHz to −3 dB frequency −3 – +0.5 dB
FSUB, FADD phase response

3

@ f = 10 kHz – – 5 °

Parameter Condition

Rating

Unit

min typ max

SM9103M

NIPPON PRECISION CIRCUITS—9

Mode Control Logic

Offset Correction Characteristics

VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C

FSUB offset voltage

No input signal,

V

REF

reference,
post-correction,
Ta = 25°C

RAM read/write, ROM
read max gain

– – ±7.0

mV

RAM read, min to max
gain

– – ±21

RAM read/write
differential gain max.

––±4

FADD offset voltage No input signal, V

REF

reference – – ±50 mV

FSUB offset voltage temperature
coefficient

– – ±0.22 mV/°C

FSUB variable gain range −16 – +14 dB
FSUB variable gain step width – 2 – dB

FSUB gain switching absolute accuracy

V

OUT

= V

REF

±

0.35 V

−16 to +8 dB – – ±0.5
dB

+10 to +14 dB – – ±1.0

1. FSUB = K × [I

F1

− IF2], gain = 0 dB

2. FADD = K × [IF1 + IF2]

3. F1, F2: 14 pF input load capacitance
FSUB, FADD: 10 pF output load capacitance, 10 kΩ load resistance

Control input

Operating mode Offset correction

WRITE MODE

LOW or open LOW or open RAM read

ActiveLOW or open HIGH ROM read

HIGH LOW or open

RAM write

HIGH HIGH Inactive

Parameter Symbol Condition

Rating

Unit

min typ max

TSUB offset residual V

REF

reference, Ta = 25 °C – – ±8.5 mV

FSUB offset residual V

REF

reference, Ta = 25 °C – – ±5.5 mV

Supply voltage droop detect level V

1

1.9 2.8 3.7 V

Correction circuit startup supply voltage V

2

3.2 3.8 4.4 V

V1 and V2 difference V2 − V

1

0.7 1.0 1.3 V

Correction thermal sensor detect
temperature

15 20 25 °C

Offset correction time – – 150 ms

Parameter Condition

Rating

Unit

min typ max

SM9103M

NIPPON PRECISION CIRCUITS—10

Serial Interface Characteristics

VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C

Parameter Symbol Condition

Rating

Unit

min typ max

SCLK pulse cycle t

cySCK

100 – – ns

SCLK HIGH-level pulsewidth t

whSCK

40 – – ns

SCLK LOW-level pulsewidth t

wlSCK

40 – – ns

SENB setup time t

sSEN

20 – – ns

SENB hold time t

hSEN

40 – – ns

SDATA setup time t

sSDA

15 – – ns

SDATA hold time t

hSDA

15 – – ns

ACK setup time

1

t

sACK

0–20ns

ACK hold time

1

t

hACK

––50ns

SENB interval t

inSEN

100 – – ns

1. ACK is the acknowledge output (n-channel open-drain). LOW-level output when the data received is valid.
SDATA load capacitance is 15 pF.

SENB

SCLOCK

SDATA

Controller

SDATA

Port

tsSEN twhSCK twlSCK

tcySCK

tsSDA

thSDA

tsACK

thACK

tinSEN

thSEN

bit 0

bit 1

bit 15

LSB MSB

ACK

High Impedance

SM9103M

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FUNCTIONAL DESCRIPTION

Serial Interface

The SM9103M uses a serial interface comprising 2
ports to control and set TSUB/FSUB output gain
switching, sleep mode to reduce current consump-

tion, and TSUB/FSUB offset correction. The address
and bit configuration of each port is shown in table 1.

Serial data is input on SDATA with the LSB first in
sync with the falling edge of the SCLK clock. After
the 16th SCLK falling edge and 16 bits of valid data
has been input, the SDATA n-channel open-drain
output goes LOW to perform the function of an
acknowledge signal.

If the number of SCLK cycles which occur when
SENB (serial interface enable) is HIGH is less than

16, the received data is ignored and the internal port
is not updated. If the number of SCLK cycles is
greater than 16, the data is still considered value up
to the 16th SCLK falling edge, the data is latched
into the internal port, and the acknowledge signal is
output. The acknowledge signal is held until SENB
goes LOW again.

Data Signal Processor

This stage creates the data signal and ID signal for
output. The weak current from the tracking PD cells
(T1, T2, T3, T4) are input to the front-end amplifier
where the signals are current-to-voltage converted at
fixed gain.

The gain setting is controlled by pins WRITE and
MODE. WRITE switches between read/write, and
MODE switches the gain between values corre­sponding to high-reflectivity and low-reflectivity
discs. These signals control the settings for RAM
(low-reflectivity disc) read/write and ROM
(high-reflectivity disc) read.

The front-end amplifier outputs are processed by the
signal processor block to generate intermediate sig­nals. The data signal, (A + B + C + D), is converted
to a difference signal by a differential output buffer
and output on DATAP and DATAN. The ID signal,
generated from the difference between 2 signals, (A
+ B) and (C + D), is converted to a difference signal
by a differential output buffer and output on CAPAP
and CAPAN. The data signal (DATAP, DATAN) and
ID signal (CAPAP, CAPAN) DC components are
removed using output stage capacitive networks.

T1, T2, T3 and T4 have a hold function to provide
the appropriate reverse bias required by the tracking
PD to ensure the data read bandwidth.

Table 1. Port address and bit configuration

1

Bit number

1514131211109876543210

Data Address

MSB LSB

TG3 TG2 TG1 TG0 FG3 FG2 FG1 FG0 × LOW LOW LOW LOW LOW ××
SL1CS1––––––× LOW LOW LOW LOW HIGH ××

1. × = don’t care, – = unassigned
TG3 to TG0: TSUB gain set bits. Default = 0111 (0 dB)
FG3 to FG0: FSUB gain set bits. Default = 0111 (0 dB)
SL1: sleep mode set bit. Sleep mode when 1, normal operation when 0. Default = 0.
CS1: offset correction control. Offset correction when 1, normal operation when 0. Default = 0.

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NIPPON PRECISION CIRCUITS—12

Tracking Signal Processor

The tracking stage generates the push-pull tracking
error signal and output signal for DPD servo, as well
as a push-pull sum signal used as an auxiliary signal.

The [(A + B) − (C + D)] signal from the com­mon-data front-end amplifier and signal processor
block is sent to the gain switching block. The gain
switching block amplifies the difference signal using
one of 16 preset gain settings in 2 dB steps to form a
push-pull signal output on TSUB. A feedback resis­tor connected to TSUBB is used to ensure gain set­ting stability. The gain of the gain switching block is
controlled by serial interface control bits as shown in
table 2.

Each signal from T1, T2, T3, T4 is buffered and then
output on DPDA, DPDB, DPDC, DPDD, respec­tively, for DPD servos.

The auxiliary signal is generated from the push-pull
sum signal (A + B + C + D). This signal is buffered
(TAB) and output on TADD. A feedback resistor
connected to TADDB is used to ensure gain setting
stability.

Focus Signal Processor

The focus stage generates the focus error signal from
the focus PD, and a sum signal. The weak focus PD
current signals (F1, F2) are input to the front-end
amplifier and then current-to-voltage converted at
fixed gain.

The front-end amplifier output is sent to the signal
processor block where the focus error signal (F1 −
F2) and the sum signal (F1 + F2) are generated.

The focus error signal is sent to the gain switching
block. The gain switching block amplifies the differ­ence signal using one of 16 preset gain settings in 2
dB steps with output on FSUB. A feedback resistor
connected to FSUBB is used to ensure gain setting
stability. The gain of the gain switching block is con­trolled by serial interface control bits as shown in
table 3.

The sum is buffered and output on FADD. A feed­back resistor connected to FADDB is used to ensure
gain setting stability.

Table 2. TSUB gain setting

TG3 TG2 TG1 TG0 Gain (dB)

1

0000 +14
0001 +12
0010 +10
0011 +8
0100 +6
0101 +4
0110 +2
0111 0
1000 −2
1001 −4
1010 −6
1011 −8
1100 −10
1101 −12
1110 −14
1111 −16

1. Default is 0 dB

Table 3. FSUB gain setting

FG3 FG2 FG1 FG0 Gain (dB)

1

0000 +14
0001 +12
0010 +10
0011 +8
0100 +6
0101 +4
0110 +2
0111 0
1000 −2
1001 −4
1010 −6
1011 −8
1100 −10
1101 −12
1110 −14
1111 −16

1. Default is 0 dB

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NIPPON PRECISION CIRCUITS—13

Offset Correction

The SM9103M has built-in offset correction circuits
for tracking and focus. During offset correction, the
internal the device operates in RAM read mode, and
FSUB and TSUB operate at maximum gain
(+14 dB). The outputs on FSUB, FADD and TSUB
are indeterminate. Also, inputs T1, T2, T3, T4 and
F1, F2 may be ignored. After correction is complete,
the FSUB and TSUB gain settings return to their
default values (0 dB).

Offset correction is performed under the following
conditions:

■ When power is applied.

■ When the supply drops below 2.8 ± 0.9 V and then

rises to above 3.8 ± 0.6 V.

■ When sleep mode operation is cancelled.

■ When the serial interface bit CS1 is 1. Note that if

SL1 is also 1, then SL1 has priority.

If the voltage falls below 2.8 ± 0.9 V during offset
correction, then correction stops and does not restart
until the supply recovers to above 3.8 ± 0.6 V.

During offset correction, the CALREQ output is held
HIGH. CALREQ goes LOW after correction stops.

The SM9103M also incorporates a temperature
detect function which detects temperature changes of
20 ± 5 °C from the time the initial correction is per­formed. If a temperature change is detected, CAL­REQ goes HIGH and the device waits for an offset
correction instruction.

Note that when both WRITE and MODE are HIGH,
offset correction is inactive and the output appears
uncorrected. However, if a correction start condition
occurs when correction is inactive, such as the cor­rection flag CS1 set to 1, then correction operation is
initiated internally but does not appear at the output
unless correction is activated prior to correction
operation finishing.

Once correction has been made inactive, the output
remains uncorrected even if correction is subse­quently reactivated. In this case, the output remains
uncorrected until a valid correction start condition is
detected.

Sleep Mode

The SM9103M features a sleep mode which can be
used when the device is not operating to significantly
reduce current consumption. The sleep mode is con­trolled by serial interface bit SL1.

Preset Function

When power is applied or after offset correction, all
serial interface flags are reset to their default values.

Flags TG3 to TG0 and FG3 to FG0 are also set to
their default values in sleep mode.

Table 4. Offset correction setting

CS1 Offset correction

1

1. Default is No correction

0 No correction
1 Correction

Table 5. Sleep mode settings

SL1 Sleep mode

1

Mode description

LOW OFF Normal operation

HIGH ON Sleep condition

1. Default is OFF

SM9103M

NIPPON PRECISION CIRCUITS—14

NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warr anty that such applications will be suitab le for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
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NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome

Koto-ku, Tokyo 135-8430, Japan
Telephone: [phone]
Facsimile: 03-3642-6698

NC9806AE 1998.12

NIPPON PRECISION CIRCUITS INC.