The SM1126 Series are melody ICs for use in mobile
telecommunications equipment. A maximum of 15
melodies can be stored in programmable ROM and
one in built-in read/write SRAM.
FEATURES
■
2.0 to 3.6 V supply voltage
■
Maximum of 16 melody selections (15 in ROM +
1 in SRAM)
■
Level hold playback mode
■
External reference clock input versions and builtin RC oscillator versions available, set by masterslice option (RC oscillator versions require an
external resistor and capacitor).
■
Selectable clock frequencies (fixed for all melodies)
• External clock input versions (6 frequencies)
- 32.768 kHz system: 32.768, 65.536 and
131.072 kHz
- 38.4 kHz system: 38.4, 76.8 and 153.6 kHz
• Built-in RC oscillator versions (1 frequency)
- 131.072 kHz
■
2-pin serial data melody selection and 1-pin melody playback control
■
Parity check function
■
Delivery pattern alarm
■
Power save function
• External clock input versions
Clock gating in non-play modes
• Built-in RC oscillator versions
Oscillator stopped in non-play modes
Melody IC with Built-in SRAM
PINOUT
(T op V iew)
8-pin VSOP
OSC
SIO
SC
ST
PACKAGE DIMENSIONS
(Unit: mm)
0.575 TYP
1
2
3
4
3.1 0.3
1126××
4.4 0.2
1.15 0.05
8
7
6
5
6.4 0.3
0.15
+ 0.1
− 0.05
VSS
VDD
MTO
TEST
0.5 0.2
ORDERING INFORMATION
De vicePack ag e
SM1126××V8-pin VSOP
0.65
0.10
0.22 0.1
0.1 0.05
0.12
+
NIPPON PRECISION CIRCUITS—1
M
BLOCK DIAGRAM
OSC
OSC
SM1126 Series
Frequency
Master sliceMaster slice
SW1
Multiplier
SW2
VSS
SIO
SC
ST
Gate
Divider
Control
Circuit
Tempo Latch
Tempo Counter
Rhythm
Counter
Divider
Main
RAM
Scale
Counter
Scale
ROM
Main
ROM
MultiPlexer
Address
Counter
Start
Address
Latch
VDD
MTO
TEST
(Pull-down resistance
built-in)
PIN DESCRIPTION
NumberNameFunction
1OSC
2SIOPlayback control serial interface data input. During parity check, the G flag is output while ST is HIGH.
3SCPlayback control serial interface clock input
4ST
5TESTTest input. Pull-down resistor built-in. Leave open or connect to VSS.
6MTOPlayback melody signal output
7VDDSupply
8VSSGround
SM1126 Series devices are available in external clock input versions and built-in RC oscillator versions, set
by master-slice option. In the case of the built-in RC oscillator option, an external resistor and capacitor is
required for the oscillator function.
SM1126 Series devices can operate at 6 selectable reference clock frequencies. All melodies playback at the
fixed speed set by the reference clock frequency. External clock input versions operate at one of 6 selectable
clock frequencies, as shown in table 1. Built-in RC oscillator versions operate at only one oscillator frequencies—131.072 kHz.
In external clock input versions, the external reference clock input is used during playback mode only and is
otherwise ignored. If a clock signal is input when not in playback mode (when ST is LOW), the gate circuit
switches to cutoff the external reference clock signal from entering the device, preventing unwanted current
flow.
In built-in RC oscillator versions, the oscillator is stopped when not in playback mode (when ST is LOW),
preventing unwanted current flow.
ST
OSC
Figure 1. External clock input version: OSC input during playback mode only
Serial data is input on SIO in sync with the SC clock in 8-bit units when ST is LOW. Data is not accepted
when ST is HIGH. When ST goes HIGH, the 8-bit data is latched. Note that if the input data exceeds 8 bits in
length, the most recent 8 bits are used and any preceding bits are ignored. Data is in MSB first format.
Input data is interpreted as a command or as a data word (in write mode), depending on the current operating
mode of the device. There are 3 types of commands:
■
Playback start command
■
SRAM write command
■
End-of-write command
The SRAM write command is used to invoke write mode operation, and end-of-write command is used to
return to play mode operation. In write mode, however, data is interpreted as data words to be written to
SRAM.
Note that pin SIO is an output pin only when the parity check command is executed. At all other times, SIO
is an input pin.
SIO
Invalid
Data
??
B7B6B5
Valid
Data
B3 B2 B1 B0
B4
Invalid
Data
?
?
?
?
?
?
?
?
?
?
SC
ST
Pin SC should be LOW when either a LOW-to-HIGH or HIGH-to-LOW transition occurs on pin ST.
Figure 4. Serial input timing
Playback control
The ST pin controls the start of playback. While ST is HIGH, the melody is played repeatedly, and when ST
goes LOW, playback stops. Melodies are selected by input serial data on pins SIO and SC, as shown in table 2.
The melody select command comprises a fixed code (1000) followed by 4 melody select data bits (B3 to B0).
The 8 bits of data are retained even after playback. If serial data is input during playback, the data is ignored
and playback continues.
Invalid
Data
Valid
Data
Invalid
Data
SIO
SC
ST
MTO
B3 B2 B1 B0HL
??
Pin SC should be LOW when either a LOW-to-HIGH or HIGH-to-LOW transition occurs on pin ST.
Melody plays repeatedly when ST is HIGH, and stops immediately when ST goes LOW.
Figure 6. Melody repetition timing
NIPPON PRECISION CIRCUITS—8
SM1126 Series
,
,
Playback timing diagrams
Playback start
Playback starts after an interval tST after ST goes HIGH.
When the reference clock frequency is 32.768 kHz, tST = (256 ± 1 oscillator cycles) + 1/128 seconds.
When the reference clock frequency is 38.4 kHz, tST = (300 ± 1 oscillator cycles) + 1/128 seconds.
Play Start Command
MSBLSB
SIO
SC
ST
OSC
*Internal
Clock
256(300) 1 Clock
1/128 sec
MTO
,,,
Figure 7. Playback start timing
Playback stop
Playback stops immediately when ST goes LOW. In external clock input versions, the IC internal clock also
stops when ST goes LOW, regardless of whether or not there is a clock input signal on pin OSC. In built-in RC
oscillator versions, the oscillator also stops when ST goes LOW.
ST
OSC
*Internal
Clock
MTO
,,,,,,,,,,,,,,,
Figure 8. Stop timing
NIPPON PRECISION CIRCUITS—9
SM1126 Series
Write Mode Control
Write sequence
The SM1126 Series devices can accept data words written to the built-in SRAM to play any melody. The
SRAM write sequence is described below.
1. Write the SRAM write command (11011111) to invoke write mode.
2. Write the tempo word (parity check ON/OFF selectable).
3. Write all necessary melody data words (parity check ON/OFF selectable).
4. Write the melody end word (parity check ON/OFF selectable).
5. Optionally, write extra data words (these are ignored).
6. Write the end-of-write command (10111111) to return to play mode.
7. If parity check was ON, write the parity check command (01111111) to perform an error check.
The built-in SRAM can store 64 words, so all melody and end words must fit within this limit. Note that the
tempo word is not stored in SRAM, but in a separate register. Playback of melodies stored in SRAM begins
from the SRAM leading address and continues until the end word is detected, at which point playback continues again from the SRAM leading address. All data in SRAM after the end word is ignored.
Input write command (11011111)
Write tempo word
Write melody word (s)
Write end word
Write optional invalid data
Input end-of-write command (10111111)
Play mode
Write mode
Input write command (11011111)
Write tempo word
Write melody word (s)
Write end word
Write optional invalid data
Input end-of-write command (10111111)
Input parity check command (01111111)
Example 1. Parity check selected
Figure 9. Write control sequence
Play mode
Example 2. Parity check not selected
NIPPON PRECISION CIRCUITS—10
SM1126 Series
Write command
The SRAM write command (11011111), shown below, is used to invoke write mode.
PLAY mode changed to WRITE mode
Address set to tempo-word register
SIO
SC
ST
1111
10
11
Figure 10. Write command timing
Tempo word
The tempo word controls the melody playback speed. The tempo word comprises a fixed code (000) followed by the tempo code (T4 to T0), as shown below. The tempo word is always the first word written after
invoking write mode, and all subsequent words are melody data words.
SIO
SC
ST
ADDRESS
WRITE command
No Address
0T4
Changed to WRITE mode
00T3T2T1T0
write Tempo-word
Tempo Register Address
RAM Address
Figure 11. Tempo word timing
NIPPON PRECISION CIRCUITS—11
SM1126 Series
Melody words
Melody words contain all the information needed for playback of a single note, including the note duration
and type (name or rest). Each melody word comprises a 3-bit length code (R2 to R0) followed by a 5-bit type
code (S4 to S0).
SIO
SC
ST
ADDRESS
(n-1)th data
write (n-1)th Data
(n)th data
write (n)th data
nn-1
n+1
Figure 12. Melody word timing
End word
The end word (01011111) indicates the end of the melody. When the end word is detected during melody
playback, operation returns to the SRAM leading address. All data in SRAM after the end word is ignored.
SIO
SC
01
011111
write END-WORD
next word
write next word
ST
ADDRESS
m+1m
m+2
Figure 13. End word timing
End-of-write command
The end-of-write command (10111111) is used to return to play mode from write mode. This command
should be executed when power is first applied to set play mode.
WRITE mode changed to PLAY mode
SIO
SC
ST
1111
01
11
Figure 14. End-of-write command timing
NIPPON PRECISION CIRCUITS—12
SM1126 Series
Parity check command
Data words (tempo word, melody words, end word) can have an optional parity bit added, forming 9-bit data
words, for a parity check function. The parity check command is executed in play mode, immediately after the
end-of-write command is executed.
The parity bit is added at the beginning of the data word. Note that the last 8 bits are always the valid data
bits. The parity check function performs an odd parity check (an odd number of 1s within the 9-bit data). If the
parity check command is not executed, play mode operation continues using the valid 8 bits of data in each
data word.
The parity check sequence is described below.
1. The internal G flag (Good flag) is set to 1 when the write command is executed.
2. When writing data words, the G flag remains set to 1 for odd parity , but is set to 0 if even parity is detected.
3. The G flag remains set to 1 only if all data words have odd parity.
4. Write the end-of-write command to return to play mode.
5. Write the parity check command.
6. When ST is HIGH, the SIO pin functions as the G flag output.
7. When ST goes LOW, the G flag output is released.
SIO
SC
ST
MODE
SIO Condition
G Flag
END-WRITE mode command
011111
WRITE mode
11
Parity Check Command
110111
PLAY mode
Input
Figure 15. Parity check timing
When G Flag = 1
When G Flag = 0
11
Output
Input
NIPPON PRECISION CIRCUITS—13
SM1126 Series
Command summary
CommandMSBBit 6Bit 5Bit 4Bit 3Bit 2Bit 1L S B
Melody start command1000B3B2B1B0
Write command11011111
Tempo word000T4T3T2T1T0
Melody wordR2R1R0S4S3S2S1S 0
End word01011111
End-of-write command10111111
Parity check command01111111
Musical Specifications
Maximum program steps
A maximum of 256 steps can be programmed into mask-programmable ROM, and a maximum of 64 steps
(including one end word) can be stored in built-in SRAM. Each step represents either a note (sound pitch and
length) a rest, or a tie.
Note length (including rests)
Eight rhythm values for notes and rests can be programmed. Also, 2 or more notes can be musically tied.
Table 3. Rhythm values
Type
Note
Rest
01234567
xee .qeq .hh .
Åää . .gäg ..
Code
!
!
Pitch and scale
SM1126 Series devices support 27 pitches from F4 to G6. The pitch varies with the clock frequency, as
shown in the frequency listing in table 4. The reference clock selected at master-slice does not affect the pitch
range.
Also, two pitches higher than G6 can be set as alarm pitches in mask ROM. Note that an alarm pitch option
cannot be specified in SRAM.
The frequency error calculation for a given pitch is shown below.
Error calculation: (A4 pitch with 32.768 kHz clock)
The measurement circuit below shows a SM1126 ×× V with built-in RC oscillator circuit and external RC
oscillator components capacitor C
When ST is switched to V
of the RC oscillator. The output pulse is counted using a frequency counter.
and resistor R
O
, the oscillator starts and outputs a pulse on MTO with a frequency double that
DD
.
O
RO
CO
Switch
Note that the board mounting and wiring will marginally affect the output frequency, even for equivalent values for R
SM1126 V
OSC
SIO
SC
ST
MTO
TEST
V
VSS
DD
Frequency Counter
and C
O
.
O
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warr anty that such applications will be suitab le for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
NIPPON PRECISION CIRCUITS INC.
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9722BE 1998.12
NIPPON PRECISION CIRCUITS—18
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