The SM1124 Series are melody pager multi-melody
ICs fabricated in NPC’s Molybdenum-gate CMOS.
A maximum of 16 tunes can be stored in
programmable ROM, and the Molybdenum-gate
CMOS process realizes small-sized packages and
low power dissipation.
FEATURES
■
Maximum of 16 tune selections (with up to 512
steps)
■
Level hold playback mode
■
External reference clock input. The frequency can
be selected from the following 12 settings.
• Playback frequency of each song varies (8
frequencies)
- 32.768 kHz system: 32.768 and 65.536 kHz
- 37.5 kHz system: 37.5 and 75.0 kHz
- 38.4 kHz system: 38.4 and 76.8 kHz
- 48.0 kHz system: 48.0 and 96.0 kHz
• Playback frequency of all songs is fixed (4
frequencies)
- 32.768 kHz system: 131.072 kHz
- 37.5 kHz system: 150.0 kHz
- 38.4 kHz system: 153.6 kHz
- 48.0 kHz system: 192.0 kHz
■
2-pin serial data tune selection
■
Power save function
■
External clock gating in non-play mode.
■
2.4 to 3.6 V supply voltage
■
8-pin plastic SOP package
■
Molybdenum-gate CMOS process
Multimelody IC for Pagers
PINOUT
8-pin SOP
SI
SC
ST
0.4 0.1
1.27
1
4
4.4 0.2
6.2 0.3
1.5 0.1
0.05 0.05
124
CLK
PACKAGE DIMENSIONS
Unit: mm
5.2 0.3
0.695TYP
8
VSS
VDD
MTO
5
TEST
+ 0.10
0.15
− 0.05
010
0.4 0.2
NIPPON PRECISION CIRCUITS—1
Page 2
−
−
−
°
°
BLOCK DIAGRAM
SM1124 Series
CLK*
SI*
SC*
ST*
PIN DESCRIPTION
Gate
1/2 or 1/4SW
Divider
1/128
Control
Circuit
Tempo
Latch
Tempo
Counter
*: Built-in Schmmit-Triger Circuit.
Rhythm
Counter
Scale
Counter
Scale
ROM
Main
ROM
Multi-
plexer
Address
Counter
Start
Address
Latch
VSS
VDD
MTO
TEST
NumberNameI/OFunction
1CLKIExternal reference clock input (Schmitt-trigger circuit and gate circuit built-in)
2SIIPlayback control serial interface data input pin
3SCIPlayback control serial interface clock input pin
4STIPlayback start/stop control signal input pin
1
1
1
5TESTITest input pin. Leave open or tie to VSS. (Pull-down resistance built-in)
6MTOOPlayback signal output pin
7VDD–Supply pin (+)
8VSS–Ground pin
1. Pins SI, SC and ST have a built-in Schmitt-trigger circuit.
SPECIFICATIONS
Absolute Maximum Ratings
ParameterSymbolConditionRatingUnit
Supply voltage rangeV
Input voltage rangeV
Power dissipationP
Storage temperature rangeT
Soldering temperatureT
Soldering timet
DD
IN
D
stg
sld
sld
V
0.3 to 5.0V
SS
0.2 to V
+ 0.2V
DD
150mW
40 to 125
255
10s
C
C
NIPPON PRECISION CIRCUITS—2
Page 3
−
°C
−
Recommended Operating Conditions
V
= 0 V unless otherwise specified
SS
−
SM1124 Series
ParameterSymbolCondition
Supply voltageV
Operating temperatureT
DC Characteristics
T
= −20 to 70 °C, V
a
ParameterSymbolCondition
Supply voltageV
Current consumption (1)I
Current consumption (2)I
Input voltage
Hysteresis widthV
Input current
Open voltageV
Output voltage
= 0 V, V
SS
DD
mintypmax
DD
opr
2.4–3.6V
20–70
= 2.4 to 3.6 V unless otherwise specified
mintypmax
2.43.03.6V
–25200µA
V
0.2–V
DD
V
SS
0.21.0–V
––0.5µA
––0.5µA
––200µA
0.4–V
DD
SS
V
V
V
DD
DD1
DD2
V
I
IH1
I
IL1
I
IH2
OPN
OH
OL
Non-playback mode, 25°C––0.5µA
Playback mode, MTO pin
The SM1124 can operate at 12 selectable external
reference clock frequencies. Of these, 8 are
selectable for each tune. When multiple external
clock frequencies are input to a single IC, the clock
must be switched during playback mode. Note that
when the frequency in parentheses is selected, all
tunes can only be played using that single fixed
frequency.
V
IH
0.5V
DD
V
IL
t
DH
V
IH
0.5V
DD
V
IL
The external reference clock input is used at any time
as well as during playback mode. If a clock signal is
input when not in playback mode (when ST is
LOW), the gate circuit switches to cutoff the e xternal
reference clock signal from entering the device,
preventing unwanted current flow.
The ST pin controls the start of playback. While ST
is HIGH (VDD), the tune is played repeatedly, and
when ST goes LOW (VSS), playback stops. Tunes
are selected by the input serial data on pins SI and
Invalid
Data
SI
SC
ST
MTO
Valid
Data
B3 B2 B1 B0
SC. The final 4 bits form the valid selection data, and
this data is retained even after playback.
If serial data is input during playback, the SM1124
ignores this data and playback continues.
Invalid
Data
,,,,,,,,,,,,,,,,,
* Pin SC should be LOW when either a LOW-to-HIGH or HIGH-to-LOW transition occurs on pin ST.
*: Tune plays repeatedly when ST is HIGH, and stops immediately when ST goes LOW.
Playback timing diagrams
Playback start
Playback starts 128 ± 1 SCK clock cycles after ST
goes HIGH.
Invalid
Data
SI
SC
Valid
Data
MSBLSB
#n2 Play
ST
CLK
Internal
Clock
MTO
Playback stop
Playback stops immediately when ST goes LOW.
The IC internal clock also stops, regardless of
whether or not there is a clock input signal on pin
CLK.
ST
CLK
Internal
Clock
128 1 Clock
MTO
,,,,,,,,,,,,,,,
NIPPON PRECISION CIRCUITS—6
Page 7
SM1124 Series
Musical Specifications
Maximum program steps
The mask for the built-in ROM can be programmed
with up to a maximum of 512 steps, where each step
represents either a note (sound pitch and length) or a
rest.
Note length (including rests)
Eight rhythm values for notes (rests) can be
programmed. Also, 2 or more notes can be
programmed as tied notes using a tie.
01234567
Note
Rest
xee.qeq .qh
Åää .ÎäÎÎî
Pitch and scale
The SM1124 performs uniform interval length
processing to reduce the error at high pitches. This
maintains the relative phase when the frequency
varies from the input value.
The pitch varies with the external reference clock
frequency, as shown in the frequency on the
following page.
The frequency variation from the input frequency is
the sum of the relative error, shown in the frequency
table, plus the pitch error.
Quarter note ( q ) length = 1536 × tempo counter frequency divider ÷ CLK frequency
(Ex) Tempo code = 1F (divider = 32), CLK frequency = 32.768 kHz
1536 × 32 ÷ 32768 = 1.5 (seconds)
q
q
q
q =
NIPPON PRECISION CIRCUITS—9
Page 10
TYPICAL APPLICATION
Speaker drive with switching circuit
SM1124 Series
VDD
DC-DC
Converter
CPU
VSS
For example
Q1: hfe 100 MIN SP: Impedance 16 Ω MIN
R1: 1.2k Ω
R2, R3: to be decided by sound volume
Speaker drive with Linear amplifier
VDD
DC-DC
Converter
CPU
VSS
1.5V
2.4 to 3.6V
CLK
SI
SC
ST
1.5V
2.4 to 3.6V
CLK
SI
SC
ST
SM1124
VDD
MTO
TEST
SM1124
VDD
MTO
TEST
VSS
VSS
VR1
SP
R2
R3
SW1
R1
Q1
VCC
C1
IN OUT
GND
C2
SP
+
For example
VR1: 10k Ω MIN
(As the output impedance of MTO terminal
is up to 1k Ω MAX, the value above is gi ven
under the condition that output shall be over
C1: to be decided by Input impedance of
amplifier.
C2, SP: to be decided by Output impedance
of amplifier.
90% of supply voltage amplitude. If it is set
below 10k Ω , output amplitude becomes
smaller.)
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warr anty that such applications will be suitab le for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
NC9503AE 1996.01
NIPPON PRECISION CIRCUITS INC.
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NIPPON PRECISION CIRCUITS—10
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