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Semiconductor
查询HCT240供应商
SL74HCT240
Octal 3-State Inverting Buffer/Line
Driver/Line Receiver
High-Performance Silicon-Gate CMOS
The SL74HCT240 is identical in pinout to the LS/ALS240. The
SL74HCT240 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
This octal inverting buffer/line driver/line receiver is designed to be
used with 3-state memory address drivers, clock drivers, and other busoriented systems. The device has inverting outputs and two active-low
output enables.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
SL74HCT240N Plastic
SL74HCT240D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Enable A,
Enable B
L L H
L H L
H X Z
A,B YA,YB
X = don’t care
Z = high impedance
System Logic
SLS
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SL74HCT240
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±35 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Pack age)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
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SL74HCT240
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VIN=VIL
VOL Maximum Low -Level
Output Voltage
VIN= VIH
IIN Maximum Input
V
=0.1 V
OUT
I
≤ 20 µA
OUT
V
= VCC-0.1 V
OUT
I
≤ 20 µA
OUT
VIN= VIL
I
≤ 20 µA
OUT
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
I
≤ 6.0 mA
OUT
VIN=VIH
I
≤ 20 µA
OUT
4.5 3.98 3.84 3.7
4.5
5.5
0.1
0.1
I
≤ 6.0 mA
OUT
4.5 0.26 0.33 0.4
VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
Leakage Current
IOZ Maximum three State
Leakage Current
ICC Maximum Quiescent
Supply Current
Output in High-Impedance
State
VIN = VIL or V
V
OUT=VCC
IH
or GND
VIN=VCC or GND
I
=0µA
OUT
5.5 ±0.5 ±5.0 ±10.0 µA
5.5 4.0 40 160 µA
(per Package)
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
Unit
V
V
V
V
∆ICC Additional Quiescent
Supply Current
I
NOTE: Total Supply Current = I
VIN = 2.4 V, Any One Input
VIN=VCC or GND, Other Inputs
=0µA 5.5 2.9 2.4
OUT
+ ∑∆ICC
CC
≥-55°C 25°C to
125°C
System Logic
SLS
mA
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SL74HCT240
Semiconductor
AC ELECTRICAL CHARACTERISTICS(V
=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
CC
Guaranteed Lim it
Symbol Parameter 25 °C to
≤85°C ≤125°C Unit
-55°C
t
, t
PLH
Maximum Propagation Delay, A to YA or B to YB
PHL
20 25 30 ns
(Figures 1 and 3)
t
, t
PLZ
Maximum Propagation Delay, Output Enable to
PHZ
28 35 42 ns
YA or YB (Figures 2 and 4)
t
, t
PZH
Maxim um Propagation Delay, Output Enable to
PZL
25 31 38 ns
YA or YB (Figures 2 and 4)
t
, t
TLH
Maximum Output Transition Time, Any Output
THL
12 15 18 ns
(Figures 1 and 3)
CIN Maximum Input Capacitance 10 10 10 pF
C
Maximum Three-State Output Capacitance
OUT
15 15 15 pF
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enable
Typical @25°C,VCC=5.0 V
Output)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDV
2
f+ICCVCC
CC
55 pF
SLS
Figure 1. Switching Waveforms Figure 2. Swit ching Waveforms
System Logic
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SL74HCT240
Semiconductor
Figure 3. Test Circuit Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/8 of the Device)
SLS
System Logic
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