Datasheet SL74HC75D, SL74HC75N Datasheet (SLS)

Semiconductor

Dual 2-Bit Transparent Latch

High-Performance Silicon-Gate CMOS

The SL74HC75 is identical in pinout to the LS/ALS75. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.

This device consists of two independent 2-bit transparent latches
and can be used as temporary storage for binary information between
processing units and input/output or indicator units. Each latch stores
the input data while Latch Enable is at a logic low. The outputs follow
the data inputs when Latch Enable is at a logic high.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

SL74HC75

ORDERING INFORMATION

SL74HC75N Plastic

SL74HC75D SOIC

TA = -55° to 125° C for all packages

LOGIC DIAGRAM

PIN 5=VCC

PIN 12 = GND

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Outputs

D Latch

Enable

L H L H

H H H L

Q Q

SLS

X L Q0 Q0

X = Don’t Care
Q0 = latched data

System Logic

SL74HC75

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±25 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750
500

Tstg Storage Tem perature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input V oltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V
V

=6.0 V

CC

0
0
0

1000

500
400

mW

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic

SLS

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

SL74HC75

Symbol Parameter Test Conditions V 25 °C

to

-55°C

VIH Minimum High-Level

Input Voltage

VIL Maximum Low -Level

Input Voltage

VOH Minimum High-Level

Output Voltage

VIN=VIH or VIL

VOL Maximum Low -Level

Output Voltage

VIN= VIL or VIH

IIN Maximum Input

V

=0.1 V or VCC-0.1 V

OUT

I

≤ 20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT

I

 ≤ 20 µA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 4.0 mA

OUT

I

 ≤ 5.2 mA

OUT

VIN= VIL or VIH

I

 ≤ 20 µA

OUT

I

 ≤ 4.0 mA

OUT

I

 ≤ 5.2 mA

OUT

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.98

5.48

0.1

0.1

0.1

0.26

0.26

VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

Leakage Current

≤85

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.84

5.34

0.1

0.1

0.1

0.33

0.33

≤125

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.7

5.2

0.1

0.1

0.1

0.4

0.4

Unit

V

V

V

V

ICC Maximum Quiescent

Supply Current
(per Package)

System Logic

SLS

VIN=VCC or GND
I

=0µA

OUT

6.0 4.0 40 80 µA

SL74HC75

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

t

, t

t

t

t

t

PLH

PLH

PLH

PLH

TLH

Maximum Propagation Delay, D to Q (Figures 1

PHL

and 5)

, t

Maximum Propagation Delay , D to Q

PHL

(Figures 1 and 5)

, t

Maximum Propagation Delay ,Latch Enable to Q

PHL

(Figures 2 and 5)

, t

Maximum Propagation Delay ,Latch Enable to Q

PHL

(Figures 2 and 5)

, t

Maximum Output Transition Time, Any Output

THL

(Figures 3 and 5)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

125

25
21

110

22
19

145

29
25

125

25
21

75
15
13

155

31
26

140

28
24

180

36
31

155

31
26

95
19
16

190

38
32

165

33
28

220

44
38

190

38
32

110

22
19

CIN Maximum Input Capacitance - 10 10 10 pF

Power Dissipation Capacitance (Per Latch) Typical @25°C,VCC=5.0 V

ns

ns

ns

ns

ns

CPD Used to determine the no-load dynamic power

consumption:
PD=CPDV

2

f+ICCVCC

CC

35 pF

TIMING REQUIREMENTS (C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

tSU Minimum Setup Time,

Input D to Latch Enable
(Figure 4)

th Minimum Hold Time,Latch

Enable to D (Figure 4)

tw Minimum Pulse Width, Latch

Enable Input
(Figure 2)

t

Maximum Input Rise and Fall

r, tf

Times (Figure 1)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

100

20
17

25

5
5

80
16
14

1000

500
400

125

25
21

30

6
6

100

20
17

1000

500
400

150

30
26

40

8
7

120

24
20

1000

500
400

ns

ns

ns

ns

SLS

System Logic

SL74HC75

Semiconductor

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms Figure 4. Switching Waveforms

Figure 5. Test Circuit

EXPANDED LOGIC DIAGRAM

SLS

System Logic