Datasheet SI4435DDY-T1-E3 Specification

New Product

P-Channel 30-V (D-S) MOSFET

Si4435DDY

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

- 30

0.024 at V

0.035 at V

(Ω)

DS(on)

= - 10 V - 11.4

GS

= - 4.5 V - 9.4

GS

d

I

(A)

D

Qg (Typ.)

15 nC

• Halogen-free According to IEC 61249-2-21

Definition

• TrenchFET® Power MOSFET

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

FEATURES

• Load Switches

• Battery Switch

SO-8

S

1

S

2

S

3

G

4

Top View

Ordering Information: Si4435DDY-T1-E3 (Lead (Pb)-free)

Si4435DDY-T1-GE3 (Lead (Pb)-free and Halogen-free)

8

D

D

7

6

D

D

5

G

S

D

P-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol Limit Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

Pulsed Drain Current

= 150 °C)

J

Continuous Source-Drain Diode Current

Avalanche Current

Single-Pulse Avalanche Energy

Maximum Power Dissipation

Operating Junction and Storage Temperature Range

T

= 25 °C

C

= 70 °C

T

C

T

= 25 °C

A

TA = 70 °C

T

= 25 °C

C

T

= 25 °C

A

L = 0.1 mH

T

= 25 °C

C

T

= 70 °C 3.2

C

T

= 25 °C

A

TA = 70 °C

V

DS

V

GS

- 30

± 20

V

- 11.4

I

D

I

DM

I

S

I

AS

E

AS

- 9.1

a, b

- 8.1

a, b

- 6.5

- 50

- 4.1

a, b

- 2.0

- 20

20 mJ

A

5.0

P

D

, T

T

J

stg

a, b

2.5

a, b

1.6

- 55 to 150 °C

W

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

Maximum Junction-to-Foot

Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. Maximum under Steady State conditions is 85 °C/W.
d. Based on T

= 25 °C.

C

Document Number: 68841
S09-0863-Rev. C, 18-May-09

a, c

t ≤ 10 s

Steady State

R

thJA

R

thJF

38 50

20 25

°C/W

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New Product

Si4435DDY

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

V

Drain-Source Breakdown Voltage
V

Temperature Coefficient ΔVDS/T

DS

Temperature Coefficient ΔV

V

GS(th)

Gate-Source Threshold Voltage

Gate-Source Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

b

a

a

a

Input Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

Tur n - O n D e l ay Time

Rise Time

Turn-Off DelayTime

Fall Ti me

Tur n - O n D e l ay Time

Rise Time

Turn-Off DelayTime

Fall Ti me

V

DS

GS(th)/TJ

V

GS(th)

I

GSS

I

DSS

I

D(on)

R

DS(on)

g

fs

C

iss

C

oss

C

rss

Q

g

Q

gs

Q

gd

R

g

t

d(on)

t

r

t

d(off)

t

f

t

d(on)

t

r

t

d(off)

t

f

J

Drain-Source Body Diode Characteristics

Continous Source-Drain Diode Current I

Pulse Diode Forward Current I

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Reverse Recovery Fall Time t

Reverse Recovery Rise Time t

S

SM

SD

rr

rr

a

b

Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

V

DS

V

V

DS

V

DS

I

D

I

D

IF = - 2 A, dI/dt = 100 A/µs, TJ = 25 °C

= 0 V, ID = - 250 µA

GS

ID = - 250 µA

V

= VGS, ID = - 250 µA

DS

VDS = 0 V, VGS = ± 20 V

V

= - 30 V, VGS = 0 V

DS

= - 30 V, V

V

≥ - 10 V, V

DS

V

= - 10 V, ID = - 9.1 A

GS

V

= - 4.5 V, ID = - 6.9 A

GS

V

= - 10 V, ID = - 9.1 A

DS

= - 15 V, V

DS

= - 15 V, V

= - 15 V, V

= 0 V, TJ = 55 °C

GS

GS

= 0 V, f = 1 MHz

GS

= - 10 V, ID = - 9.1 A

GS

= - 4.5 V, ID = - 9.1 A

GS

f = 1 MHz 5.8 Ω

V

= - 15 V, RL = 15 Ω

DD

≅ - 1 A, V

V

DD

≅ - 1 A, V

= - 10 V, Rg = 1 Ω

GEN

= - 15 V, RL = 15 Ω

= - 4.5 V, Rg = 1 Ω

GEN

TC = 25 °C - 4.1

IS = - 2 A, V

GS

- 30 V

- 31

4.5

mV/°C

- 1.0 - 3.0 V

± 100 nA

- 1

- 5

= - 10 V - 30 A

0.0195 0.024

0.028 0.035

23 S

1350

215

185

32 50

15 25

4

7.5

10 15

815

45 70

12 25

42 70

35 60

40 70

16 30

- 50

= 0 V - 0.75 - 1.2 V

34 60 ns

22 40 nC

11

23

µA

Ω

pFOutput Capacitance

nC

ns

A

ns

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

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2

Document Number: 68841

S09-0863-Rev. C, 18-May-09

New Product

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Si4435DDY

Vishay Siliconix

50

VGS=10V thru 5 V

40

30

20

- Drain Current (A)I

D

10

0

0.0 0.5 1.0 1.5 2.0

- Drain-to-Source Voltage (V)

V

DS

Output Characteristics

0.05

0.04

VGS=4.5V

0.03

- On-Resistance (Ω)R

0.02

DS(on)

0.01

0

0 1020304050

ID- Drain Current (A)

VGS=10V

On-Resistance vs. Drain Current

V

=4V

GS

VGS=3V

1.0

0.8

0.6

0.4

- Drain Current (A)I

D

0.2

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VGS- Gate-to-Source Voltage (V)

TC= - 55 °C

TC= 25 °C

TC= 125 °C

Transfer Characteristics

2400

1800

C

iss

1200

C - Capacitance (pF)

600

C

C

rss

0

0 6 12 18 24 30

oss

VDS- Drain-to-Source Voltage (V)

Capacitance

10

I

=9.1A

D

8

6

VDS=7.5V

4

- Gate-to-Source Voltage (V)

GS

2

V

0

0918 27 36

Document Number: 68841
S09-0863-Rev. C, 18-May-09

VDS=15V

VDS=22.5V

Qg- Total Gate Charge (nC)

Gate Charge

1.8

ID=9.1A

1.5

1.2

- On-ResistanceR
(Normalized)

DS(on)

0.9

VGS=4.5V

0.6

- 50 - 25 0 25 50 75 100 125 150

-Junction Temperature (°C)

T

J

On-Resistance vs. Junction Temperature

VGS=10V

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New Product

Si4435DDY

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

100

10

TJ= 150 °C

1

0.1

- Source Current (A)

S

I

0.01

0.001

0.0 0.2 0.4 0.6 0.8 1.0 1.2

-Source-to-Drain Voltage (V)

V

SD

Source-Drain Diode Forward Voltage

0.6

0.4

ID= 250 µA

0.2

Variance (V)V

GS(th)

0.0

TJ= 25 °C

TJ= - 50 °C

ID=1mA

0.06

0.05

0.04

0.03

- On-Resistance (Ω)

0.02

DS(on)

R

0.01

0

012345678 910

VGS- Gate-to-Source Voltage (V)

TJ= 125 °C

TJ= 25 °C

On-Resistance vs. Gate-to-Source Voltage

100

80

60

Power (W)

40

20

ID=9.1A

- 0.2

- 50 - 25 0 25 50 75 100 125 150

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4

TJ- Temperature (°C)

Threshold Voltage

- Drain Current (A)

D

I

0.01

0

Single Pulse Power, Junction-to-Ambient

100

Limited byR

10

1

0.1
TA= 25 °C

Single Pulse

0.1 1 10 100

> minimum VGSat which R

* V

GS

*

DS(on)

BVDSS Limited

V

- Drain-to-Source Voltage (V)

DS

DS(on)

100 µs

1ms

10 ms

100 ms

1s
10 s

100 s, DC

is specified

Safe Operating Area

0.1

Time (s)

Document Number: 68841

S09-0863-Rev. C, 18-May-09

011100.00.01

New Product

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

15

12

9

6

- Drain Current (A)

D

I

3

0

0 25 50 75 100 125 150

- Case Temperature (°C)

T

C

Current Derating*

Si4435DDY

Vishay Siliconix

6.0

4.8

3.6

Power (W)

2.4

1.2

0.0
0255075100125150

- Case Temperature (°C)

T

C

Power, Junction-to-Foot

* The power dissipation PD is based on T
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

J(max)

2.0

1.6

1.2

Power (W)

0.8

0.4

0.0
0 25 50 75 100 125 150

-Ambient Temperature (°C)

T

A

Power Derating, Junction-to-Ambient

limit.

Document Number: 68841
S09-0863-Rev. C, 18-May-09

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5

New Product

Si4435DDY

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

1

Duty Cycle = 0.5

0.2

Normalized Effective Transient

Normalized Effective Transient

0.1

0.1

0.05

Thermal Impedance

0.02

Single Pulse

0.01

-4

10

-3

10

-2

10

-1

Notes:

P

DM

t

1

t

- TA=PDMZ

JM

2

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

4. Surface M ounted

100

thJA

thJA

t

1

t

2

= 85 °C/W

(t)

000110110

Square WavePulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

1

Duty Cycle = 0.5

0.2

0.1

0.1

Thermal Impedance

0.05

0.02

Single Pulse

0.01

-4

10

-3

10

-2

10

-1

01110

Square WavePulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?68841

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6

.

Document Number: 68841

S09-0863-Rev. C, 18-May-09

SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

Package Information

Vishay Siliconix

D

e

BA

1

DIM

A 1.35 1.75 0.053 0.069

A

1

B 0.35 0.51 0.014 0.020

C 0.19 0.25 0.0075 0.010

D 4.80 5.00 0.189 0.196

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.50 0.93 0.020 0.037

q0°8°0°8°

S 0.44 0.64 0.018 0.026

ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498

8

1

0.25 mm (Gage Plane)

A

6

7

2

5

HE

3

4

S

h x 45

C

L

MILLIMETERS INCHES

Min Max Min Max

0.10 0.20 0.004 0.008

All Leads

q

0.101 mm

0.004"

Document Number: 71192
11-Sep-06

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1

VISHAY SILICONIX

Trench FET® Power MOSFETs

Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use

integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and

0.050

1.27

design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the

0.027

0.69

0.07

1.98

Figure 2. Dual MOSFET SO-8 Pad Pattern

basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.

In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The

The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.

total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.

Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder

0.288

7.3

connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the

0.050

1.27

0.027

0.69

0.078

1.98

0.2

5.07

0.196

5.0

Figure 1. Single MOSFET SO-8 Pad

Pattern With Copper Spreading

Document Number: 70740 www.vishay.com
Revision: 18-Jun-07 1

drain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least

0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.

0.288

7.3

8

0.2

5.07

With Copper Spreading

0.088

2.25

0.088

2.25

APPLICATION NOTE

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172

(4.369)

0.028

(0.711)

Return to Index

Return to Index

0.022

(0.559)

0.246
(6.248)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.270)

0.152

0.047

(3.861)

(1.194)

APPLICATION NOTE

www.vishay.com Document Number: 72606
22 Revision: 21-Jan-08

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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12

1

Document Number: 91000