Page 1
PROTECTION PRODUCTS
PROTECTION PRODUCTS
SFC05-4
CSP TVS
Flip Chip TVS Diode Array
PRELIMINARY
PRELIMINARY
Description
The SFC05-4 is a quad flip chip CSP TVS diode array.
They are state-of-the-art devices that utilize solid-state
silicon-avalanche technology for superior clamping
performance and DC electrical characteristics. The
SFC series TVS diodes are designed to protect sensitive semiconductor components from damage or latchup due to electrostatic discharge (ESD) and other
voltage induced transient events.
The SFC05-4 is a 6-bump, 0.5mm pitch flip chip array
with a 3x2 bump grid. It measures 1.5 x 1.0 x
0.65mm. This small outline makes the SFC05-4
especially well suited for portable applications. CSP
TVS devices are compatible with current pick and place
equipment and assembly methods.
Each device will protect up to four data or I/O lines.
The CSP design results in lower inductance, virtually
eliminating voltage overshoot due to leads and interconnecting bond wires. They may be used to meet the
ESD immunity requirements of IEC 61000-4-2, Level 4
(15kV air, 8kV contact discharge).
Features
u 300 Watts peak pulse power (tp = 8/20µs)
u Transient protection for data lines to
IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 24A (8/20µs)
u Small chip scale package requires less board space
u Low profile (< 0.65mm)
u No need for underfill material
u Protects four I/O or data lines
u Low clamping voltage
u Working voltage: 5V
u Solid-state silicon-avalanche technology
Mechanical Characteristics
u JEDEC MO-211, Variation BB, 0.50 mm Pitch Chip
Scale Package (CSP)
u Marking : Marking Code
u Packaging : Tape and Reel
Applications
u Cell Phone Handsets and Accessories
u Personal Digital Assistants (PDAs)
u Notebook & Hand Held Computers
u Portable Instrumentation
u Pagers
u Smart Cards
u MP3 Players
u GPS
Device Dimensions Schematic & PIN Configuration
1.50
B
1.00
0.50
TYP
SFC05-4 Maximum Dimensions (mm) 3 x 2 Grid CSP TVS (Bottom View)
Revision 12/18/2000
0.50
0.150
0.65
A
1
1
23
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SFC05-4
PROTECTION PRODUCTS
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PRELIMINARY
PRELIMINARY
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2ã 2000 Semtech Corp.
www.semtech.com
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SFC05-4
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve
10
(kW)
PP
1
0.1
Peak Pulse Power - P
0.01
0.1 1 10 100 1000
Pulse Duration - tp (µs)
Pulse Waveform
110
100
90
80
70
PP
60
50
40
Percent of I
30
20
10
0
0 5 10 15 20 25 30
-t
e
Time (µs)
td = IPP/2
Waveform
Parameters:
tr = 8µs
td = 20µs
110
100
90
PP
80
70
60
50
40
30
% of Rated Power or I
20
10
0
0 25 50 75 100 125 150
Ambient Temperature - T
Clamping Voltage vs. Peak Pulse Current
10.00
9.00
8.00
7.00
6.00
5.00
4.00
3.00
Clamping Voltage - Vc (V)
2.00
1.00
0.00
0 5 10 15 20 25 30
Peak Pulse Current - Ipp (A)
PRELIMINARY
PRELIMINARY
(oC)
A
Waveform
Parameters:
tr = 8µs
td = 20µs
ESD Clamping (8kV Contact Discharge)
ã 2000 Semtech Corp.
3
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Page 4
SFC05-4
PROTECTION PRODUCTS
Applications Information
Device Connection Options
The SFC05-4 has solder bumps located in a 3 x 2
matrix layout on the active side of the device. The
bumps are designated by the numbers 1 - 3 along the
horizontal axis and letters A - B along the vertical axis.
The lines to be protected are connected at bumps A1,
B1, A3, and B3. Bumps A2 & B2 are connected to
ground. All path lengths should be kept as short as
possible to minimize the effects of parasitic inductance
in the board traces.
Wafer Level CSP TVS
CSP TVS devices are wafer level chip scale packages.
They eliminate external plastic packages and leads and
thus result in a significant board space savings. Manufacturing costs are minimized since they do not require
an intermediate level interconnect or interposer layer
for reliable operation. They are compatible with current pick and place equipment further reducing manufacturing costs. Certain precautions and design
considerations have to be observed however for
maximum solder joint reliability. These include solder
pad definition, board finish, and assembly parameters.
PRELIMINARY
PRELIMINARY
Device Schematic & Pin Configuration
B
A
1
23
Layout Example
To Protected IC To Protected IC
Ground
Printed Circuit Board Mounting
Non-solder mask defined (NSMD) land patterns are
recommended for mounting the SFC05-4. Solder
mask defined (SMD) pads produce stress points near
the solder mask on the PCB side that can result in
solder joint cracking when exposed to extreme fatigue
conditions. The recommended pad size is 0.200 ± 10
mm with a solder mask opening of 0.350 ± 0.025 mm.
Grid Courtyard
The recommended grid placement courtyard is 1.3 x
1.8 mm. The grid courtyard is intended to encompass
the land pattern and the component body that is
centered in the land pattern. When placing parts on a
PCB, the highest recommended density is when one
courtyard touches another.
To Connector
NSMD Package Footprint
4ã 2000 Semtech Corp.
www.semtech.com
Page 5
SFC05-4
PROTECTION PRODUCTS
Applications Information (Continued)
Printed Circuit Board Finish
A uniform board finish is critical for good assembly
yield. Two finishes that provide uniform surface coatings are immersion nickel gold and organic surface
protectant (OSP). A non-uniform finish such as hot air
solder leveling (HASL) can lead to mounting problems
and should be avoided.
Stencil Design
A properly designed stencil is key to achieving adequate solder volume without compromising assembly
yields. A 0.100mm thick, laser cut, electro-polished
stencil with 0.275mm square apertures and rounded
corners is recommended.
Reflow Profile
The flip chip TVS can be assembled using standard
SMT reflow processes. As with any component, thermal profiles at specific board locations can vary & must
be determined by the manufacturer. The flip chip TVS
peak reflow temperature is 230 ± 10 °C, but the
device can withstand up to 260 °C peak reflow temperature. Time above eutectic temperature (183 °C)
should be 50 ± 10 seconds. During reflow, the component self-aligns itself on the pad.
Stencil Design
Reflow Profile
PRELIMINARY
PRELIMINARY
Circuit Board Layout Recommendations for Suppression of ESD
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
l Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
l Minimize the path length between the TVS and the
protected line.
l Minimize all conductive loops including power and
ground loops.
l The ESD transient return path to ground should be
kept as short as possible.
l Never run critical signals near board edges.
l Use ground planes whenever possible.
ã 2000 Semtech Corp.
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Page 6
SFC05-4
PROTECTION PRODUCTS
Outline Drawing - SFC05-4
PRELIMINARY
PRELIMINARY
Land Pattern - SFC05-4
6ã 2000 Semtech Corp.
www.semtech.com
Page 7
SFC05-4
PROTECTION PRODUCTS
Marking Codes
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4-50CFSU54F
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Ordering Information
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MT.4-50CFSV5000,6hcnI7
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PRELIMINARY
PRELIMINARY
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Contact Information
ã 2000 Semtech Corp.
Semtech Corporation
Protection Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
7
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