Page 1
INTEGRATED CIRCUITS
SC68C562
CMOS dual universal serial
communications controller (CDUSCC)
Product specification
Supersedes data of 1994 Apr 27
IC19 Data Handbook
1998 Sep 04
Page 2
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
DESCRIPTION
The Philips Semiconductors SC68C562 Dual Universal Serial
Communications Controller (CDUSCC) is a single-chip CMOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SC68C562 interfaces to the 68000
MPUs via asynchronous bus control signals and is capable of
program-polled, interrupt driven, block-move or DMA data transfers.
The SC68C562 is hardware (pin) and software (Register)
compatible with SCN68562 (NMOS version). It will automatically
configure to NMOS DUSCC register map on power-up or reset.
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides 16 common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock.
This makes the CDUSCC well suited for dual speed channel
applications. Data rates up to 10Mb/s are supported.
Each transmitter and each receiver is serviced by a 16 byte FIFO.
The receiver FIFO also stores 9 status bits for each character
received; the transmit FIFO is able to store transmitter commands
with each byte. This permits reading and writing of up to 16 bytes at
a time, thus minimizing the
potential for transmitter underrun, receiver overrun and reducing
interrupt or DMA overhead.
In addition, a flow control capability is provided to disable a remote
transmitter when the FIFO of the local receiving device is full. Two
modem control inputs (DCD and CTS) and three modem control
outputs (RTS and two general purpose) are provided. Because the
modem control inputs are general purpose in nature, they can be
optionally programmed for other functions. This document contains
the electrical specifications for the SC68C562. Refer to the CMOS
Dual Universal Serial Communications Controller (CDUSCC) User
Manual for a complete operational description of this product.
FEA TURES
•Full hardware and software upward compatibility with previous
NMOS device
General Features
•Dual full-duplex synchronous/ asynchronous receiver and
transmitter
•Low power CMOS process
•Multiprotocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
– COP: BISYNC, DDCMP
– ASYNC: 5–8 bits plus optional parity
•Sixteen character receiver and transmitter FIFOs
•0 to 10MHz data rate
•Programmable bit rate for each receiver and transmitter selectable
from:
– 19 fixed rates: 50 to 64k baud
– One user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
– Digital phase-locked loop
•Parity and FCS (frame check sequence LRC or CRC) generation
and checking
•Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
•Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
•Programmable data transfer mode: polled, interrupt, DMA, wait
•DMA interface
– Compatible with the Philips Semiconductors SCB68430 Direct
Memory Access Interface (DMAI) and other DMA controllers
– Single- or dual-address dual transfers
– Half- or full-duplex operation
– Automatic frame termination on counter/timer terminal count or
DMA DONE
•Transmit path clear status
•Interrupt capabilities
– Daisy chain option
– Vector output (fixed or modified by status)
– Programmable internal priorities
– Interrupt at any FIFO fill level
– Maskable interrupt conditions
•FIFO’d status bits
•Watchdog timer
•Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
•Modem controls
– RTS, CTS, DCD, and up to four general I/O pins per channel
– CTS and DCD programmable auto-enables for Tx and Rx
– Programmable interrupt on change of CTS or DCD
•On-chip oscillator for crystal
•TTL compatible
•Single +5V power supply
Asynchronous Mode Features
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•Up to two stop bits programmable in 1/16-bit increments
SC68C562
1998 Sep 04 853-1682 19973
2
Page 3
Philips Semiconductors Product specification
DESCRIPTION
DWG #
SYMBOL
PARAMETER
UNIT
CMOS Dual universal serial communications controller
(CDUSCC)
•1X or 16X Rx and Tx clock factors
•Parity, overrun, and framing error detection
•False start bit detection
•Start bit search 1/2-bit time after framing error detection
•Break generation with handshake for counting break characters
•Detection of start and end of received break
•Character compare with optional interrupt on match
•Transmits up to 10Mb/s at 1X and receive up to 1Mb/s at 16X
data rates
Character-Oriented Protocol Features
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•LRC or CRC generation and checking
•Optional opening PAD transmission
•One or two SYN characters
•External sync capability
•SYN detection and optional stripping
•SYN or MARK line fill on underrun
•Idle in MARK or SYNs
•Parity, FCS, overrun, and underrun error detection
BISYNC Features
•EBCDIC or ASCII header, text and control messages
•SYN, DLE stripping
•EOM (end of message) detection and transmission
•Auto transparent mode switching
•Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
•Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
•Character length: 5 to 8 bits
•Detection and transmission of residual character: 0–7 bits
•Automatic switch to programmed character length for I field
•Zero insertion and deletion
•Optional opening PAD transmission
•Detection and generation of FLAG, ABORT, and IDLE bit patterns
•Detection and generation of shared (single) FLAG between
frames
•Detection of overlapping (shared zero) FLAGs
•ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun
•Idle in MARK or FLAGs
•Secondary address recognition including group and global
address
•Single- or dual-octet secondary address
•Extended address and control fields
•Short frame rejection for receiver
•Detection and notification of received end of message
•CRC generation and checking
•SDLC loop mode capability
SC68C562
ORDERING INFORMATION
VCC = +5V ±10%,
TA = 0 to +70°C
Serial Data Rate =
10Mbps Maximum
48-Pin Plastic Dual In-Line Package (DIP) SC68C562C1N Not available SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package SC68C562C1A SC68C562A8A SOT238-3
ABSOLUTE MAXIMUM RATINGS
T
A
T
STG
V
CC
V
S
1998 Sep 04
Operating ambient temperature
Storage temperature -65 to +150 -65 to +150 °C
Voltage from VCC to GND
Voltage from any pin to ground
1
RATING
COMMERCIAL INDUSTRIAL
2
3
3
0 to +70 -40 to +85 °C
–0.5 to +7.0 –0.5 to +7.0 V
–0.5 to VCC +0.5 –0.5 to VCC +0.5 V
3
VCC = +5V ±10%,
TA = –40 to +85°C
Serial Data Rate =
8Mbps Maximum
Page 4
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
PIN CONFIGURATIONS
INDEX
CORNER
Pin Function Pin Function
1 IACKN 27 CSN
2 A3 28 R/WN
3 A2 29 DONEN
4A1 30D3
5 RTxDAKBN/ 31 D2
6 IRQN 33 D0
7NC 34NC
8 RESETN 35 CTSAN/LCAN
9 RTSBN/ 36 TxDRQAN/
10 TRxCB 37 RTxDRQAN/
11 RTxCB GPO1AN
12 DCDBN/ 38 TxDAKAN/
13 NC 39 TxDA
14 RxDB 40 RxDA
15 TxDB 41 NC
16 TxDAKBN/ 42 DCDAN/
17 RTxDRQBN/ 43 RTxCA
18 TxDRQBN/ 45 RTSAN/
19 CTSBN/LCBN 46 X2/IDCN
20 D7 47 X1/CLK
21 D6 48 RTxDAKAN/
22 D5 GPI1AN
23 D4 49 A6
24 DTACKN 50 A5
25 DTCN 51 A4
26 GND 52 V
IACKN
RTxDAKBN/
GPI1BN
IRQN
RESETN
RTSBN/
SYNOUTBN
TRxCB
RTxCB
DCDBN/
SYNIBN
RxDB
TxDB
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO1BN
TxDRQBN/
GPO2BN/RTSBN
CTSBN/LCBN
DTACKN
DTCN
GND
1
2
A3
3
A2
4
A1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
D7
19
D6
20
D5
21
D4
22
23
24
N PACKAGE
DIP
48
V
DD
47
A4
46
A5
45
A6
RTxDAKAN/
44
GPI1AN
43
X1/CLK
42
X2/IDCN
RTSAN/
41
SYNOUTAN
40
TRxCA
39
RTxCA
DCDAN/
38
SYNIAN
37
Rxda
36
TxDA
TxDAKAN/
35
GPI2AN
RTxDRQAN/
34
GPO1AN
TxDRQAN/
33
GPO2AN/RTSAN
32
CTSAN/LCAN
31
D0
30
D1
29
D2
28
D3
27
DONEN
26
R/WN
25
CSN
SC68C562
A PACKAGE
7
8
PLCC
20
21
TOP VIEW
GPI1BN 32 D1
SYNOUTBN GPO2AN/RTSAN
SYNIBN GPI2AN
GPI2BN SYNIAN
GPO1BN 44 TRxCA
GPO2BN/RTSBN SYNOUTAN
47
1
46
34
33
DD
SD00222
1998 Sep 04
4
Page 5
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
BLOCK DIAGRAM
DTACKN
RWN
A1-A6
CSN
RESETN
RTxDRQAN/GPO1AN
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
DTCN
DONEN
TRxCA/B
RTxCA/B
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
CTSA/BN
DCDBN/SYNIBN
DCDAN/SYNIAN
D0-D7
DMA INTERFACE
BUS
BUFFER
A7 CONTROL
LOGIC
MPU
INTERFACE
SPECIAL
FUNCTION
PINS
INTERFACE/
OPERATION
CONTROL
ADDRESS
DECODE
R/W
DECODE
DMA
CONTROL
CCRA/B
PCRA/B
RSRA/B
TRSRA/B
ICTSRA/B
GSR
CMR1A/B
CMR2A/B
OMRA/B
TRCR A/B
FTLR A/B
TRMR A/B
CID
CONTROL
INTERNAL BUS
CHANNEL MODE
AND TIMING A/B
DPLL CLK
MUX A/B
DPLL A/B
BRG
COUNTER/
TIMER A/B
C/T CLK
MUX A/B
CTCRA/B
CTPRHA/B
CTPRLA/B
CTHA/B
CTLA/B
TRANSMIT A/B
TRANS CLK
MUX
TPRA/B
TTRA/B
TX SHIFT
REG
TRANSMIT
16 DEEP
FIFO
TELRA/B
CRC
GEN
SPEC CHAR
GEN LOGIC
SC68C562
TxD A/B
1998 Sep 04
IRQN
IACKN
X1/CLK
X2/IDCN
INTERRRUPT
CONTROL
ICRA/B
IERA/B
IVR
IVRM
IER1
IER2
IER3
OSCILLATOR
DUSCC
LOGIC
RECEIVER A/B
RCVR CLK
MUX
RPRA/B
RTRA/B
S1RA/B
S2RA/B
RCVR
SHIFT REG
RECEIVER
16 DEEP
FIFO
RFLRA/B
CRC
ACCUM
BISYNC
COMPARE
LOGIC
RxD A/B
SD00253
5
Page 6
Philips Semiconductors Product specification
MNEMONIC
TYPE
NAME AND FUNCTION
CMOS Dual universal serial communications controller
(CDUSCC)
PIN DESCRIPTION
PIN NO.
DIP PLCC
A1–A6 4-2,
D0–D7 31-28,
R/WN 26 28 I Read/Write: A high input indicates a read cycle and a low indicates a write cycle when
CSN 25 27 I Chip Select: Active-low input. When active, data transfers between the CPU and the
IRQN 6 6 O Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
IACKN 1 1 I Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
X1/CLK 43 47 I Crystal or External Clock: When using the crystal oscillator, the crystal is connected
X2/IDCN 42 46 O Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal
RESETN 7 8 I Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
RxDA, RxDB 37, 12 40, 14 I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
TxDA, TxDB 36, 13 39, 15 O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
RTxCA, RTxCB 39, 10 43, 11 I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
TRxCA, TRxCB 40, 9 44, 10 I/O Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
CTSA/BN,
LCA/BN
47-45
21-18
32, 17 35, 19 I/O Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal
4-2,
51-49
33-30,
23-20
I Address Lines: Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.
I/O Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and R/WN or during interrupt acknowledge
cycles and single address DMA acknowledge cycles.
CEN is active.
CDUSCC are enabled on D0–D7 as controlled by R/WN and A1–A6 inputs. When CSN is
high, the data lines are placed in the 3-State condition (except during interrupt
acknowledge cycles and single address DMA transfers).
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the CDUSCC to output an interrupt vector on the data bus.
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.
between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.
This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.
is connected between pins X1 and X2. This pin can be programmed to provide an
interrupt daisy chain active-low output which propagates the IACKN signal to lower priority
devices, if no active interrupt is pending. This pin should be left floating when an external
clock is used on X1 and X2 is not used as an interrupt daisy chain output. When a crystal
is used, a capacitor must be connected from this pin to ground.
resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is
asynchronous, i.e., no clock is required.
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.
first. This output is in the marking (high) condition when the transmitter is disabled or when
the channel is operating in local loopback mode. If external transmitter clock is specified
for the channel, the data is shifted on the falling edge of the clock.
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1 ÷ 2).
can be programmed to act as an enable for the transmitter when not in loop mode. The
CDUSCC detects logic level transitions on this input and can be programmed to generate
an interrupt when a transition occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is asserted and negated by CDUSCC commands. This
output provides the means of controlling external loop interface hardware to go on-line and
off-line without disturbing operation of the loop.
SC68C562
1998 Sep 04
6
Page 7
Philips Semiconductors Product specification
MNEMONIC
TYPE
NAME AND FUNCTION
CMOS Dual universal serial communications controller
(CDUSCC)
PIN DESCRIPTION (Continued)
PIN NO.
DIP PLCC
DCDA/BN,
SYNIA/BN
RTxDRQA/BN,
GPO1A/BN
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
RTxDAKA/BN,
GPI1A/BN
TxDAKA/BN,
GPI2A/BN
DONEN 27 29 I/O Done: Active-low, open-drain. DONEN can be used and is active in both DMA and
RTSA/BN,
SYNOUTA/BN
DTACKN 22 24 O Data T ransfer Acknowledge: Active-low, 3-state. DTACKN is asserted on a write cycle to
DTC 23 25 I Device Transfer Complete: Active-low. DTCN is asserted by the DMA controller to
V
CC
GND 24 26, 13,
38, 11 42, 12 I Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be
used as a general purpose input. For the DCD function, the CDUSCC detects logic level
transitions on this pin and can be programmed to generate an interrupt when a transition
occurs. As an active-low external sync input, it is used in COP mode to obtain character
synchronization for the receiver without receipt of a SYN character. This mode can be
used in disc or tape controller applications or for the optional byte timing lead in X.21.
34, 15 37, 17 O Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.
33, 16 36, 18 O Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a
Request-to-Send output, which can be asserted and negated under program control.
44, 5 48, 5 I Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC
that the DMA controller has acquired the bus and that the requested bus cycle (read
receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter
is enabled) is beginning. For full-duplex single address DMA operation, this input indicates
to the CDUSCC that the DMA controller has acquired the bus and that the requested read
receiver FIFO bus cycle is beginning. Because the state of this input can be read under
program control, it can be used as a general purpose input when not in single address
DMA mode.
35, 14 38, 16 I Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.
non-DMA modes. As an input, DONEN indicates the last DMA transfer cycle to the
TxFIFO. As an output, DONEN indicates either the last DMA transfer from the RxFIFO or
that the transmitted character count has reached terminal count.
41, 8 45, 9 O Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
indicate that the data on the bus has been latched, and on a read cycle or interrupt
acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is
latched by the assertion (falling edge) of DTACKN or by the negation (rising edge) of CSN,
whichever occurs first. The signal is negated when completion of the cycle is indicated by
negation of CSN or IACKN input, and returns to the inactive state (3-state) a short period
after it is negated. In single address DMA mode, input data is latched by the assertion
(falling edge) of DTCN or by the negation (rising edge) of the DMA acknowledge input,
whichever occurs first. DTACK is negated when completion of the cycle is indicated by the
assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and
returns to the inactive state (3-state) a short period after it is negated. When inactive,
DTACKN requires an external pull-up resistor.
indicate that the requested data transfer is complete.
48 34, 52 I +5V Power Input
I Signal and Power Ground Input
41, 7
SC68C562
1998 Sep 04
7
Page 8
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
CMOS Dual universal serial communications controller
(CDUSCC)
DC ELECTRICAL CHARACTERISTICS
V
IL
V
IH
V
OL
V
OH
I
ILX1
I
IHX1
I
SCX2
I
IL
I
L
I
OZH
I
OZL
I
ODL
I
ODH
I
CC
C
IN
C
OUT
C
I/O
NOTES:
1. Stresses above those listed under Abs. Max Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
2. Clock may be stopped (DC) for testing purposes or when the CDUSCC is in non-operational modes. Operation down to 0 rate clocks is
implied by a full static CMOS design, but is not verified in testing or characterization.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature and voltage range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V . All time measurements are referenced at input volta ges of
0.2V and 3.0V and output voltages of 0.8V and 2.0V , as appropriate.
6. See Figure 18 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. To include noise margin this response is measured
from the switching signal midpoint to 0.2 V above the required output level.
8. Execution of the valid command (after it is latched) requires a minimum of three rising edges of X1 (see Figure 19).
9. These values were no explicitly tested; they are guaranteed by design and characterization data.
10.X1/CLK and X2 are not tested with a crystal installed.
11.X1/CLK frequency must be at least as fast as the faster of the receiver or transmitter data rate.
12.The X1 clock drives DTACKN, Baud Rate Generator, command register and the update of the FIFO fill level encoders. The Command
Register requires three X1 clocks between two commands; FIFO fill level encoding requires 2.5 to 3.5 X1 cycles.
13.The 68562 bus interface may be operated in two modes; a 68000 compatible mode with automatic DTACK generation and a short chip
select mode. DTACKN should not be used externally in the short chip select mode. The DTACKN signal is generated by the assertion of
the chip select, and data is latched by assertion of DTACKN or by de-assertion of the chip select, whichever comes first. In single address
DMA, the DTACK signal will be de-asserted by the assertion of the DTCN or from the de-assertion of the TxDAKN, whichever occurs first.
14.Also includes X2/IDCN pin in IDC mode.
15.In case of 3-state output, output levels V
16.V
Input low voltage:
All except X1/CLK
X1/CLK
Input high voltage:
All except X1/CLK
X1/CLK
Output low voltage:
All except IRQN
IRQN
Output high voltage:
14
7
14
(Except open drain outputs)
X1/CLK input low current
X1/CLK input high current
10
10
X2 short circuit current (X2 mode) X1 open VIN = 0
Input low current
RESETN, DTCN, TxDAKA/BN,
RTxDAKA/BN
Input leakage current
Output off current high, 3-State data bus
Output off current low , 3-State data bus
Open drain output low current in off
state: DONEN, DTACKN (3-state)
6
Open drain output high current in off state:
IRQN
DONEN, IRQN, DTACKN (3-state)
Power supply current
16
(See Figure 17 for graphs)
Input capacitance
Output capacitance
Input/output capacitance
= 0 to VCC, Rx/Tx at 10MHz and X1 at 10MHz
O
9
9
9
4, 5
TA = 0 to +70°C, –40 to +85C, VCC = 5.0V 10%
0 to 70C
–40 to 85C
IOL = 5.3mA (Comm), 4.8mA
I
OL
(Indus)
= 8.8mA (Comm), 7.8mA
(Indus)
I
= -400µA
OH
VIN = 0, X2 = GND
VIN = VCC, X2 = GND
VIN = V
CC
VIN = 0 -15 –0.5 µA
VIN = 0 to V
–40 to 85C
VIN = V
–40 to 85C
VIN = 0
–40 to 85C
CC,
0 to 70C
CC,
0 to 70C
,
0 to 70C
VIN = 0
VIN = V
CC
0 to 70C
–40 to 85C
VCC = GND = 0
VCC = GND = 0
V
= GND = 0
CC
+ 0.2 are considered float or high impedance.
OL
LIMITS
Min Typ Max
2.0
2.3
0.8xV
CC
VCC–0.5
–150 0.0
-1
–10
-1
–10
-15
-1
–1
SC68C562
0.8
0.8
V
0.5
0.5
150
–15
+15
+1
+10
+1
+10
-0.5
+1
25 80
95
10
15
20
CC
V
V
V
V
V
V
V
V
µA
µA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
mA
pF
pF
pF
1998 Sep 04
8
Page 9
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
RESETN
t
RELREH
SD00205
Figure 1. Reset Timing
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
RELREH
RESETN low to RESETN high 200 200 ns
t
ADVCSL
A1–A6
R/WN
CSN
t
RWHCSL
t
CSLADI
t
CSLCSH
t
CSHRWL
t
CSHCSL
SC68C562
t
CSHDDF
t
CSHDDI
t
CSHDAH
t
CSHDAZ
SD00254
D0–D7
DTACKN
t
CSLDDV
INVALID DATA VALID INVALID
t
12
CSLDDA
t
CSLDAL
t
DDVDAL
t
DALCSH
Figure 2. Read Cycle Bus Timing
Times represent an X1 clock frequency of 14.745MHz
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
ADVCSL
t
RWHCSL
t
CSHRWL
t
CSHCSL
t
CSLDDV
t
CSHDDF
t
DDVDAL
t
DALCSH
t
CSLDAL
t
CSHDAH
t
CSHDAZ
t
CSLADI
t
CSLCSH
t
CSLDDA
t
CSHDDI
A0-A6 valid to CSN low 10 5 ns
RWN high to CSN low 10 5 ns
CSN high to RWN low 20 10 ns
CSN high to CSN low
8
50 30 ns
CSN low to read data valid 150 130 ns
CSN high to data bus float 50 40 ns
Read data valid to DTACKN low
DTACKN low to CSN high
13
CSN low to DTACKN low
9
9
9
20 20 ns
0 0 ns
30 )
140 )
1.5
f
CL
40 )
1
f
CL
1
f
CL
130 )
1.5
f
CSN high to DTACKN high 60 60 ns
CSN high to DTACKN high impedance 90 90 ns
CSN low to address invalid 60 50 ns
CSN low to CSN high 150 130 ns
CSN low to data bus driver active
9
5 10 ns
CSN high to data invalid 5 5 ns
CL
ns
1998 Sep 04
9
Page 10
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
t
ADVCSL
A1–A6
t
t
R/WN
D0–D7
DTACKN
CSN
t
RWLCSL
12
CSLADI
t
CSLWDV
t
CSLDAL
t
CSLCSH
Figure 3. Write Cycle Bus Timing
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
ADVCSL
t
CSLADI
t
RWLCSL
t
CSHRWH
t
CSHCSL
t
DALCSH
t
DALWDI
t
CSLDAL
t
CSHDAH
t
CSHDAZ
t
CSLCSH
t
CSLWDV
t
CSHWDI
A0-A6 valid to CSN low 10 5 ns
CSN low to A0-A6 invalid 60 50 ns
RWN low to CSN low 0 0 ns
CSN high to RWN high 0 0 ns
CSN high to CSN low
DTACKN low to CSN high
DTACKN low to write data invalid
13
CSN low to DTACKN low
8
9
9
9
50 30 ns
0 0 ns
0 0 ns
1
30 )
f
CL
CSN high to DTACKN high 60 60 ns
CSN high to DTACKN high impedance 90 90 ns
CSN low to CSN high 150 130 ns
CSN low to write data valid 30 35 ns
CSN high to write data invalid 10 5 ns
CSHRWH
t
140 )
DALCSH
t
DALWDI
t
CSHDAH
1.5
f
CL
LIMITS
40 )
t
CSHWDI
1
f
CL
SC68C562
t
CSHCSL
t
CSHDAZ
SD00255
1.5
130 )
f
CL
ns
1998 Sep 04
10
Page 11
Philips Semiconductors Product specification
12
CMOS Dual universal serial communications controller
(CDUSCC)
IRQN
t
IALIAH
IACKN
D0-D7
t
IALDDA
12
DTACHN
SYMBOL PARAMETER
t
IALIAH
t
IALDDA
t
IALDDV
t
IAHDDF
t
DDVDAL
t
IAHDAH
t
IAHDAZ
t
IALDAL
t
IAHDDI
t
DALIAH
IACKN low to IACKN high 140 130 ns
IACKN low to data bus drivers active
IACKN low to read data valid 140 130 ns
IACKN high to data bus floating 60 60 ns
Read data valid to DTACKN low
IACKN high to DTACKN high 80 70 ns
IACKN high to DTACKN high impedance 110 100 ns
IACKN low to DTACKN low
9
IACKN high to data bus invalid 5 5 ns
DTACKN low to IACKN high
9
t
IALDDV
INVALID DATA VALID INVALID
t
DDVDAL
t
IALDAL
t
DALIAH
Figure 4. Interrupt Cycle Timing
INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
9
9
5 10 ns
20 20 ns
30 )
f
0 0 ns
t
IAHDDI
140 )
1.5
f
CL
1
CL
LIMITS
t
IAHDDF
t
IAHDAZ
40 )
1
f
CL
t
IAHDAH
130 )
SC68C562
SD00256
1.5
f
CL
ns
IACKN
t
IALDCL
IDCN
SD00257
Figure 5. Interrupt Daisy Chain Timing
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
IALDCL
IACKN low to IDCN (daisy chain) low 70 60 ns
RWN
CSN
GPI1_N
AND/OR
GPI2_N
t
GIVCSL
t
CSLGII
SD00258
Figure 6. Input Port Timing
1998 Sep 04
11
Page 12
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
GIVCSL
t
CSLGII
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
t
DALGOV
t
CSLDAL
t
CSHGOV
GPI input valid to CSN low 20 20 ns
CSN low to GPI input invalid 40 40 ns
RWN
t
CSN
GPO1_N
AND/OR
GPO2_N
DTACKN
t
DALGOV
OLD DATA NEW DATA
12
t
CSLDAL
CSHGOV
SD00259
Figure 7. Output Port Timing
LIMITS
Min Max Min Max
DTACKN low to GPO output data valid
13
CSN low to DTACKN low
9
9
1
30 )
f
CL
40 40 ns
140 )
1.5
f
CL
40 )
1
f
CL
CSN high to GPO output data valid 100 100 ns
SC68C562
1.5
130 )
f
CL
ns
1998 Sep 04
12
Page 13
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
CSN
t
CSHIRH
DTACKN
t
DALIRH
IRQN
Figure 8. Interrupt Timing, Write Cycle
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
DALIRH
t
CSHIRH
DTACKN low to IRQN high, write cycle
Write TxFIFO (TxRDY interrupt)
Write RSR (Rx condition interrupt)
Write TRSR (Rx/Tx interrupt)
9
Write ICTSR (port change and CT interrupt)
Write TRMSR (Tx Path, Patt recognition)
CSN high to IRQN high, write cycle
9
9
9
9
9
Write TxFIFO (TxRDY interrupt) 100 90 ns
Write RSR (Rx condition interrupt) 100 90 ns
Write TRSR (Rx/Tx interrupt) 100 90 ns
Write ICTSR (port change and CT interrupt) 100 90 ns
Write TRMSR (Tx Path, Patt recognition)
9
SD00260
LIMITS
40 40 ns
40 40 ns
40 40 ns
40 40 ns
40 40 ns
100 90 ns
SC68C562
CSN
IRQN
V
OL
t
CSHIRH
+.5V
SD00261
Figure 9. Interrupt Timing, Read Cycle
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
CSHIRH
CSN high to IRQN high, read cycle
Read RxFIFO (RxRDY interrupt) 100 90 ns
1998 Sep 04
13
Page 14
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
t
CLHCLL
t
CCHCCL
t
RCHRCL
X1/CLK
CTCLK
RxC
TxC
t
TCHTCL
t
CLLCLH
t
CCLCCH
t
RCLRCH
t
TCLTCH
a. Driving X1 from an External Source
CRYSTAL SERIES RESISTANCE SHOULD
BE LESS THAN 180Ω
C1
Y1
C2
X1
X2
Figure 10. Receive, Dual Address DMA
CP1
360k
1.5M
CP2
CLK
TO
TTL
TO DTACKN
BLOCK
÷2
ALL OTHER BLOCKS
CDUSCC
+5V
470Ω
*
OPEN X2
SC68C562
*PULL-UP RESISTOR IS NOT REQUIRED
WHEN USING CMOS LEVELS
X1
SD00262
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Typ Max Min Typ Max
t
CLHCLL
t
CLLCLH
t
CCHCCL
t
CCLCCH
t
RCHRCL
t
RCLRCH
t
TCHTCL
t
TCLTCH
f
CL
f
CC
f
RC
f
TC
f
RTC
X1/CLK high to low time 25 25 ns
X1/CLK low to high time 25 25 ns
CT and DPLL CLK high to low time 50 45 ns
CT and DPLL CLK low to high time 50 45 ns
RxC high to low time 55 50 ns
RxC low to high time 55 50 ns
TxC high to low time 55 50 ns
TxC low to high time 55 50 ns
X1/CLK frequency
11, 2
0 14.7456 16.0 0 14.7456 16.0 MHz
CT CLK frequency 0 8 0 10 MHz
RxC frequency (16X or 1X) 0 8 0 10 MHz
TxC frequency (16X or 1X) 0 8 0 10 MHz
Tx/Rx frequency for FM/Manchester encoding 4 5 MHz
1998 Sep 04
14
Page 15
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
t
CILTXV
TxD
t
TxC
(1X OUTPUT)
COLTXV
a. Transmit Timing NRZ b. Transmit Timing FM0/1, Manchester Encoding
Figure 11.
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
CILTXV
TxC input low (1X) to TxD output 120 120 ns
TxC input low (16X) to TxD output 125 120 ns
t
* TxC output low to TxD output (NRZ, NRZI)
COLTXV
(FM, Manchester)
9
9
NOTE: Characterized with no loads on TxD and TxC outputs.* Tester load approximately 50pF.
TxC
(INPUT)
TxD
TxC
(1X OUTPUT)
t
CILTXV
t
COLTXV
t
t
COLTXV
LIMITS
25 20 ns
35 30 ns
SC68C562
CILTXV
SD00263
t
RCHSOL
RXC
SYNOUTN
SYNIN
RXC (1X)
INPUT
RxD
t
t
RXVRCH
SILRCH
t
RCHSIH
t
RCHRXI
(INPUT)
RxD
t
RXVRCH
t
RCHRXI
t
RXVRCH
t
RCHRXI
a. Receive Timing NRZ b. Receive Timing FM0/1, Manchester Encoding
SD00264
Figure 12.
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
RXVRCH
RxD data valid to RxC high:
For NRZ data 25 20 ns
For NRZI, Manchester, FM0, FM1 data 30 30 ns
t
RCHRXI
RxC high to RxD data invalid:
For NRZ data 25 20 ns
For NRZI, Manchester, FM0, FM1 data 30 30 ns
t
SILRCH
t
RCHSIH
t
RCHSOL
SYNIN low to RxC high 50 50 ns
RxC high to SYNIN high 20 20 ns
RxC high to SYNOUT low 110 100 ns
1998 Sep 04
15
Page 16
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
t
CSN
12
DTACKN
DONEN (OUTPUT)
(EOM)
RTxDRQ_N
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
t
CSLROL
t
CSLRRH
t
CSHROH
t
ROLDAL
t
RRHDAL
t
CSLDAL
CSN low to Rx DONEN output low 110 100 ns
CSN low to Rx DMA REQN high 110 100 ns
CSN high to Rx DONEN output high 70 60 ns
Rx DONEN output low to DTACKN low
Rx DMA REQN high to DTACKN low
13
CSN low to DTACKN low
9
CSLDAL
t
ROLDAL
t
CSLROL
t
RRHDAL
t
CSLRRH
Figure 13. Receive, Dual Address DMA
Min Max Min Max
9
9
40 40 ns
40 40 ns
1
30 )
140 )
f
CL
1.5
f
CL
LIMITS
40 )
t
CSHROH
1
f
CL
SC68C562
SD00265
1.5
130 )
f
CL
ns
1998 Sep 04
16
Page 17
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
t
DONEN
(OUTPUT)
CSN
12
DTACKN
t
CSLDIL
DONEN
(INPUT)
TxDRQ_N OR
RTxDRQ_N
SYMBOL PARAMETER
t
CSLTOL
t
CSLTRH
t
DALDIH
t
DALTOH
t
TOLDAL
t
TRHDAL
t
CSLDAL
t
CSLDIL
t
CSHTOH
t
CSHDIH
CSN low to Tx DONEN output low 110 100 ns
CSN low to Tx DMA REQN high 110 100 ns
DTACKN low to Tx DONEN input high
DTACKN low to Tx DONEN output high
Tx DONEN output low to DTACKN low
Tx DMA REQN high to DTACKN low
13
CSN low to DTACKN low
9
CSN low to Tx DONEN input low 35 40 ns
CSN high to Tx DONEN output high 70 60 ns
CSN high to Tx DONEN input high 30 25 ns
TOLDAL
t
CSLTOL
t
CSLDAL
t
CSLTRH
t
TRHDAL
Figure 14. Transmit, Dual Address DMA
LIMITS LIMITS
INDUSTRIAL SC68C562 COMMERCIAL SC68C562
Min Max Min Max
9
9
9
9
0 0 ns
40 40 ns
40 40 ns
1
30 )
f
CL
t
DALTOH
t
DALDIH
20 20 ns
1.5
140 )
f
CL
t
40 )
t
CSHTOH
CSHDIH
1
f
CL
SC68C562
SD00266
1.5
130 )
f
CL
UNIT
ns
1998 Sep 04
17
Page 18
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
RAHROH
t
RAHRAL
t
RRHDAL
t
ROLDAL
t
DTLROH
t
RALROL
t
RALRRH
t
SC68C562
RAHDDF
t
RALRAH
t
RxDAK_N
RAHDDI
t
t
DTLDDF
t
RALDDV
INVALID DATA VALID INVALID
D0-D7
DTLDAZ
t
DTLDDI
t
RALDDA
t
RALDAL
t
12
DTACKN
DTLDAH
t
DDVDAL
t
DTCN
DTLDTH
t
RALDTL
t
DALDTL
t
DONEN
(OUTPUT)
RAHDAZ
t
t
RAHDAH
RTxDRQ_N
1998 Sep 04
SD00267
Figure 15. DMA Rx Read Timing—Single Address DMA
18
Page 19
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
DMA Rx Read Timing — Single Address DMA
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
RALDDV
t
DTLDTH
t
DALDTL
t
DTLDDF
t
RALDAL
t
DDVDAL
t
DTLDAH
t
DTLDAZ
t
RRHDAL
t
ROLDAL
t
RALRRH
t
RAHRAL
t
RALROL
t
DTLROH
t
RALRAH
t
RAHDDF
t
RALDDA
t
RAHDDI
t
DTLDDI
t
RALDTL
t
RAHDAH
t
RAHDAZ
t
RAHROH
Receive DMA ACKN low to read data valid 140 130 ns
DTCN low to DTCN high 50 40 ns
DTACKN low to DTCN low
9
0 0 ns
DTCN low to data bus float 70 60 ns
Rx DMA ACK low to DTACKN low
Read data valid to DTACKN low
9
9
1
30 )
f
CL
20 20 ns
140 )
1.5
f
CL
40 )
1
f
CL
DTCN low to DTACKN high 80 80 ns
DTCN low to DTACKN high impedance 110 110 ns
Rx DMA REQN high to DTACKN low
Rx DONEN output low to DTACKN low
9
9
40 40 ns
40 40 ns
Rx DMA ACKN low to receive DMA REQN high 100 100 ns
Receive DMA ACKN high to low time 50 30 ns
Rx DMA ACK low to Rx DONEN output low 100 100 ns
DTCN low to Rx DONEN output high 80 70 ns
Rx DMA ACKN low to Rx DMA ACKN high 140 130 ns
Rx DMA ACKN high to data bus float 60 60 ns
Rx DMA ACKN low to data bus drivers active
9
5 10 ns
Rx DMA ACKN high to data bus invalid 5 5 ns
DTCN low to data bus invalid 5 5 ns
Rx DMA ACKN low to DTCN low 140 130 ns
Rx DMA ACKN high to DTACKN high 80 70 ns
Rx DMA ACKN high to DTACKN high impedance 110 100 ns
Rx DMA ACKN high to DONEN output high 70 60 ns
SC68C562
1.5
130 )
f
CL
ns
1998 Sep 04
19
Page 20
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
DMA Tx Write Timing — Single Address DMA
LIMITS
SYMBOL PARAMETER INDUSTRIAL SC68C562 COMMERCIAL SC68C562 UNIT
Min Max Min Max
t
DTLDTH
t
DALDTL
t
TALDAL
t
DTLDAH
t
DTLDAZ
t
TRHDAL
t
TOLDAL
t
DTLTOH
t
WDVDTL
t
DTLWDI
t
TALTRH
t
TAHTAL
t
TALTOL
t
DILDTL
t
DTLDIH
t
TALTAH
t
TAHWDI
t
WDVTAH
t
TAHDAH
t
TAHDAZ
t
TAHTOH
t
DILTAH
t
TAHDIH
t
TALDTL
DTCN low to DTCN high 50 40 ns
DTACKN low to DTCN low
Tx DMA ACK low to DTACKN low
9
9
0 0 ns
30 )
1
f
CL
140 )
1.5
f
CL
40 )
1
f
CL
DTCN low to DTACKN high 80 80 ns
DTCN low to DTACKN high impedance 110 110 ns
Tx DMA REQN high to DTACKN low
Tx DONEN output low to DTACKN low
9
9
40 40 ns
40 40 ns
DTCN low to Tx DONEN output high 80 70 ns
Write data valid to DTCN low 40 40 ns
DTCN low to write data invalid 30 20 ns
Tx DMA ACKN low to transmit DMA REQN high 110 100 ns
Transmit DMA ACKN high to low time 40 30 ns
Tx DMA ACKN low to Tx DONEN output low 100 90 ns
Transmit DONEN input low to DTCN low 40 30 ns
DTCN low to transmit DONEN input high 40 30 ns
Tx ACKN low to Tx ACKN high 110 100 ns
Tx ACKN high to write data invalid 15 10 ns
Write data valid to Tx DAKN high 60 40 ns
Tx DAKN high to DTACKN high 80 70 ns
Tx DAKN high to DTACKN high impedance 110 100 ns
Tx DAKN high to DONEN output high 70 60 ns
DONEN input low to Tx DAKN high 40 30 ns
Tx DAKN high to DONEN input high 30 25 ns
Tx DAKN low to DTCN low 110 100 ns
SC68C562
1.5
130 )
f
CL
ns
1998 Sep 04
20
Page 21
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
DTLDIH
t
TAHDIH
t
t
TAHTAL
t
DILDTL
DILTAH
TRHDAL
t
TOLDAL
t
t
DTLTOH
t
TALTRH
t
SC68C562
TAHTOH
t
TALTOL
t
DTLDAZ
TAHDAZ
t
t
WDVTAH
TAHDAH
t
TAHWDI
t
TALTAH
t
WDVDTL t
t
TxDAKN
t
DTLWDI
D0-D7
TALDAL
t
12
DTACKN
DTLDAH
t
TALDTL
t
DTCN
DTLDTH
t
DALDTL
t
DONEN
(input)
Figure 16. DMA Tx Write Timing—SIngle Address DMA
TxDRQN
DONEN
(output)
SD00269
1998 Sep 04
21
Page 22
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
50
40
30
I
CC
20
10
0
4 4.5 5 5.5 6
V
CC
0°C
25°C
70°C
Test Condition: Tx/Rx and X1 Frequency @ 10MHz
IRQN
50pF
Figure 17.
2.7k
50
40
30
I
CC
20
10
0
46810
Tx/Rx Clk and X1 Frequency
Test Condition: VCC = 5V @ 25°C
V
CC
TRxC
RTxC
SC68C562
SD00250
50pF
DTACKN
DONEN
ALL OTHER
OUTPUTS
NOTE:
All C
includes 50pF stray capacitance, i.e., CL = 150pF = (100pF discrete + 50pF stray).
L
150pF
150pF
50pF
6.0k
Figure 18. Test Conditions for Outputs
X1/CLK
WRN
820Ω
1k
+5.0V
V
CC
710
+5.0V
SD00270
1998 Sep 04
COMMAND
VALID
SD00219
Figure 19. Command Timing
22
Page 23
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
RxC
RxD
LCN
a. Loop Control Output Assertion
RxC
RxD
LCN
b. Loop Control Output Negation
12345678
12345678
Figure 20. Relationship Between Received Data and the Loop Control Output
SC68C562
9
SD00220
1998 Sep 04
23
Page 24
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
DIP48: plastic dual in-line package; 48 leads (600 mil) SOT240-1
SC68C562
1998 Sep 04
24
Page 25
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
PLCC52: plastic leaded chip carrier; 52 leads; pedestal SOT238-3
SC68C562
1998 Sep 04
25
Page 26
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller
(CDUSCC)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
SC68C562
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 08-98
Document order number: 9397 750 04356
1998 Sep 04
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