Datasheet SAB-C517A-4R24M, SAB-C517A-4RM, SAB-C517A-L24M, SAB-C517A-LM, SAF-C517A-4R24M Datasheet (Siemens)

Microcomputer Components

8-Bit CMOS Microcontroller

C517A

Data Sheet 10.97

C517A Data Sheet

Revision History: Current Version: 10.97

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Edition 10.97
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

© Siemens AG 1997.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in­curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

8-Bit CMOS Microcontroller

Advance Information

• Full upward compatibility with SAB 80C517A/83C517A-5

• Up to 24 MHz external operating frequency

– 500 ns instruction cycle at 24 MHz operation

• Superset of the 8051 architecture with 8 datapointers

• On-chip emulation support logic (Enhanced Hooks Technology

• 32K byte on-chip ROM (with optional ROM protection)

– alternatively up to 64K byte external program memory

• Up to 64K byte external data memory

• 256 byte on-chip RAM

• Additional 2K byte on-chip RAM (XRAM)

• Seven 8-bit parallel I/O ports

• Two input ports for analog/digital input

(further features are on next page)

TM

C517A

)

Oscillator

Watchdog

Power
Saving
Modes

On-Chip Emulation Support Module

8 Bit

USART UART

Figure 1
C517A Functional Units

Watchdog

Timer

Compare

Timer

10-Bit

A/D Converter

8 Bit

T2CCU

XRAM RAM

T0

(8 Datapointer)

T1

Port 8

Analog/

Digital

Input

256 x 82K x 8

CPU

ROM

32k x 8

Port 7 Port 6 Port 5 Port 4

Digital

Input

MDU

I/O

Port 0

Port 1

Port 2

Port 3

I/OAnalog/

I/O

I/O

I/O

I/O

I/O

MCA03317

Semiconductor Group 3 1997-10-01

C517A

Features (cont’d):

• Two full duplex serial interfaces (USART)

– 4 operating modes, fixed or variable baud rates
– programmable baud rate generators

• Four 16-bit timer/counters

– Timer 0 / 1 (C501 compatible)
– Timer 2 for 16-bit reload, compare, or capture functions
– Compare timer for compare/capture functions

• Powerful 16-bit compare/capture unit (CCU) with up to 21 high-speed or PWM output channels

and 5 capture inputs

• 10-bit A/D converter

– 12 multiplexed analog inputs
– Built-in self calibration

• Extended watchdog facilities

– 15-bit programmable watchdog timer
– Oscillator watchdog

• Power saving modes

– Slow down mode
– Idle mode (can be combined with slow down mode)
– Software power-down mode
– Hardware power-down mode

• 17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels

• P-MQFP-100 packages

• Temperature Ranges: SAB-C517A T

SAF-C517A TA= -40 to 85 °C
SAH-C517A TA= -40 to 110 °C

= 0 to 70 °C

A

Table 1
Ordering Information

Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

SAB-C517A-4RM Q67120-DXXXX P-MQFP-100-2 with mask programmable ROM

(18 MHz)

SAF-C517A-4RM Q67120-DXXXX P-MQFP-100-2 with mask programmable ROM

(18 MHz) ext. temp. – 40 °C to 85 °C

SAB-C517A-4R24M Q67120-DXXXX P-MQFP-100-2 with mask programmable ROM

(24 MHz)

SAF-C517A-4R24M Q67120-DXXXX P-MQFP-100-2 with mask programmable ROM

(24 MHz) ext. temp. – 40 °C to 85 °C
SAB-C517A-LM Q67127-C1071 P-MQFP-100-2 for external memory (18 MHz)
SAF-C517A-LM Q67127-C1063 P-MQFP-100-2 for external memory (18 MHz)

ext. temp. – 40 °C to 85 °C
SAB-C517A-L24M Q67127-C1072 P-MQFP-100-2 for external memory (24 MHz)

Semiconductor Group 4 1997-10-01

C517A

Note: Versions for extended temperature ranges – 40 °C to 110 °C (SAH-C517A) are available on

request. The ordering number of ROM types (DXXXX extensions) is defined after program
release (verification) of the customer.

VV

CC

SS

Port 7

8-bit Analog/

Digital Input

Port 8

4-bit Analog/

Digital Input

XTAL1

XTAL2

ALE

PSEN

EA

RESET

PE/SWD

OWE

RO

HWPD

V

AREF

V

AGND

C517A

MCL03318

Port 0
8-Bit Digital I/O

Port 1
8-Bit Digital I/O

Port 2
8-Bit Digital I/O

Port 3
8-Bit Digital I/O

Port 4
8-Bit Digital I/O

Port 5
8-Bit Digital I/O

Port 6
8-Bit Digital I/O

Figure 2
Logic Symbol

Additional Literature

For further information about the C517A the following literature is available:

Title Ordering Number

C517A 8-Bit CMOS Microcontroller User’s Manual B158-H7053-X-X-7600
C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

Semiconductor Group 5 1997-10-01

P1.6/CLKOUT

P1.7/T2

P3.7/RD

P3.6/WR

P3.5/T1

P3.4/T0

P3.3/INT1

P3.2/INT0

P3.1/TxD0

P3.0/RxD0

N.C.

N.C.

P7.0/AIN0

P7.1/AIN1

P7.2/AIN2

P7.3/AIN3

P7.4/AIN4

P7.5/AIN5

P7.6/AIN6

C517A

CC4/INT2/P1.4

N.C.
N.C.
N.C.

N.C.
CC3/INT6/P1.3
CC2/INT5/P1.2

CC1/INT4/P1.1

CC0/INT3/P1.0

V

SS

V

CC

XTAL2

XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15

PSEN

ALE

EA

N.C.
P0.0/AD0
P0.1/AD1

N.C.

N.C.
P0.2/AD2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

10031

9932

9833

9734

9635

9536

9437

9338

9239

9140

9041

C517A

8942

8843

8744

8645

8546

8447

8348

8249

8150

80
79
78
77
76
75
74
73
72

71
70
69
68
67
66
65
64
63
62

61
60
59
58
57
56
55
54
53
52

51

P7.7/AIN7

V

AGND

V

AREF

N.C.
N.C.
N.C.
N.C.
RESET
P4.7/CM7
P4.6/CM6
P4.5/CM5
P4.4/CM4
P4.3/CM3
PE/SWD
P4.2/CM2
P4.1/CM1
P4.0/CM0

V

CC

V

SS

RO
P8.3/AIN11
P8.2/AIN10
P8.1/AIN9
P8.0/AIN8
P6.7
P6.6
P6.5
N.C.
N.C.
N.C.

P6.3

P6.4

TxD1/P6.2

MCP03319

P0.5/AD5

P0.3/AD3 P1.5/T2EX

P0.4/AD4

HWPD

P0.6/AD6

P0.7/AD7

CCM5/P5.5

CCM6/P5.6

CCM7/P5.7

CCM4/P5.4

CCM2/P5.2

CCM3/P5.3

CCM0/P5.0

CCM1/P5.1

OWE

RxD1/P6.1

ADST/P6.0

Figure 3
Pin Configuration P-MQFP-100 Package (Top View)

Semiconductor Group 6 1997-10-01

Table 2
Pin Definitions and Functions

Symbol Pin Number I/O*) Function

P-MQFP-100

C517A

P1.0 - P1.7 9 - 6, 1,

100 - 98

9

8

7

6

1
100
99
98

I/O Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current (IIL, in the DC
characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the compare
functions). The secondary functions are assigned to the
port 1 pins as follows:
P1.0 INT3 CC0 Interrupt 3 input / compare 0 output /

capture 0 input

P1.1 INT4 CC1 Interrupt 4 input / compare 1 output /

capture 1 input

P1.2 INT5 CC2 Interrupt 5 input / compare 2 output /

capture 2 input

P1.3 INT6 CC3 Interrupt 6 input / compare 3 output /

capture 3 input
P1.4 INT2 Interrupt 2 input
P1.5 T2EX Timer 2 external reload / trigger input
P1.6 CLKOUT System clock output
P1.7 T2 Counter 2 input

V

SS

10, 62 – Ground (0V)

during normal, idle, and power down operation.

V

CC

11, 63 – Supply voltage

during normal, idle, and power down mode.

*) I = Input

O = Output

Semiconductor Group 7 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

XTAL2 12 – XTAL2

is the input to the inverting oscillator amplifier and input to
the internal clock generator circuits.
To drive the device from an external clock source, XTAL2
should be driven, while XTAL1 is left unconnected.
Minimum and maximum high and low times as well as rise/
fall times specified in the AC characteristics must be
observed.

XTAL1 13 – XTAL1

is the output of the inverting oscillator amplifier. This pin is
used for the oscillator operation with crystal or ceramic
resonator.

C517A

P2.0 - P2.7 14 - 21 I/O Port 2

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong internal
pullup resistors when issuing 1's. During accesses to
external data memory that use 8-bit addresses
(MOVX @Ri), port 2 issues the contents of the P2 special
function register.

PSEN 22 O The Program Store Enable

output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every six oscillator periods except during
external data memory accesses. The signal remains high
during internal program execution.

, in the DC

IL

ALE 23 O The Address Latch enable

output is used for latching the address into external
memory during normal operation. It is activated every six
oscillator periods except during an external data memory
access.

*) I = Input

O = Output

Semiconductor Group 8 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

EA 24 I External Access Enable

When held high, the C517A executes instructions from the
internal ROM as long as the PC is less than 8000H. When
held low, the C517A fetches all instructions from external
program memory. For the C517A-L this pin must be tied
low.

C517A

P0.0 - P0.7 26, 27,

30 - 35

I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1's written to them float, and in that state can be used
as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to
external program and data memory. In this application it
uses strong internal pullup resistors when issuing 1's. Port
0 also outputs the code bytes during program verification
in the C517A. External pullup resistors are required during
program verification.

HWPD 36 I Hardware Power Down

A low level on this pin for the duration of one machine cycle
while the oscillator is running resets the C517A. A low level
for a longer period will force the part into hardware power
down mode with the pins floating. There is no internal
pullup resistor connected to this pin.

P5.0 - P5.7 44 - 37 I/O Port 5

is a quasi-bidirectional I/O port with internal pull-up
resistors. Port 5 pins that have 1 s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (I
characteristics) because of the internal pull-up resistors.
This port also serves the alternate function “Concurrent
Compare” and “Set/Reset Compare”. The secondary
functions are assigned to the port 5 pins as follows:
CCM0 to CCM7 P5.0 to P5.7:

concurrent compare or Set/Reset lines

, in the DC

IL

*) I = Input

O = Output

Semiconductor Group 9 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

OWE 45 I Oscillator Watchdog Enable

A high level on this pin enables the oscillator watchdog.
When left unconnected this pin is pulled high by a weak
internal pull-up resistor. The logic level at OWE should not
be changed during normal operation. When held at low
level the oscillator watchdog function is turned off. During
hardware power down the pullup resistor is switched off.

C517A

P6.0 - P6.7 46 - 50,

54 - 56

I/O Port 6

is a quasi-bidirectional I/O port with internal pull-up
resistors. Port 6 pins that have 1 s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 6 pins being
externally pulled low will source current (I
DC characteristics) because of the internal pull-up
resistors.
Port 6 also contains the external A/D converter control pin
and the transmit and receive pins for the serial interface 1.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to
operate.
The secondary functions are assigned to the pins of port 6,
as follows:

46
47
48

P6.0 ADST external A/D converter start pin
P6.1 RxD1 receiver data input of serial interface 1
P6.2 TxD1 transmitter data input of serial interface 1

P8.0 - P8.3 57 - 60 I Port 8

is a 4-bit unidirectional input port. Port pins can be used for
digital input, if voltage levels meet the specified input high/
low voltages, and for the higher 4-bit of the multiplexed
analog inputs of the A/D converter, simultaneously.
P8.0 - P8.3 AIN8 - AIN11 analog input 8 - 14

, in the

IL

RO 61 O Reset Output

This pin outputs the internally synchronized reset request
signal. This signal may be generated by an external
hardware reset, a watchdog timer reset or an oscillator
watchdog reset. The RO is active low.

*) I = Input

O = Output

Semiconductor Group 10 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

C517A

P4.0 - P4.7 64 - 66,

68 - 72

I/O Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull-up
resistors. Port 4 pins that have 1’s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (IIL, in the DC
characteristics) because of the internal pull-up resistors.

PE/SWD 67 I Power saving mode enable / Start watchdog timer

A low level at this pin allows the software to enter the power
saving modes (idle mode, slow down mode, and power
down mode). In case the low level is also seen during
reset, the watchdog timer function is off on default.
Usage of the software controlled power saving modes is
blocked, when this pin is held at high level. A high level
during reset performs an automatic start of the watchdog
timer immediately after reset.
When left unconnected this pin is pulled high by a weak
internal pull-up resistor. During hardware power down the
pullup resistor is switched off.

RESET 73 I RESET

A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C517A. A
small internal pullup resistor permits power-on reset using
only a capacitor connected to VSS.

V

AREF

V

AGND

78 – Reference voltage for the A/D converter
79 – Reference ground for the A/D converter

P7.0 - P7.7 87 - 80 Port 7

is an 8-bit unidirectional input port. Port pins can be used
for digital input, if voltage levels meet the specified input
high/low voltages, and for the lower 8-bit of the multiplexed
analog inputs of the A/D converter, simultaneously.
P7.0 - P7.7 AIN0 - AIN7 analog input 8 - 14

*) I = Input

O = Output

Semiconductor Group 11 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

C517A

P3.0 - P3.7 90 - 97

90

91

92

93

94
95
96

97

I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (IIL, in the DC
characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that function
to operate. The secondary functions are assigned to the
pins of port 3, as follows:
P3.0 RxD0 Receiver data input (asynch.) or data

input/output (synch.)of serial interface 0

P3.1 TxD0 Transmitter data output (asynch.) or

clock output (synch.) of serial interface 0

P3.2 INT0 External interrupt 0 input /

timer 0 gate control input

P3.3 INT1 External interrupt 1 input /

timer 1 gate control input
P3.4 T0 Timer 0 counter input
P3.5 T1 Timer 1 counter input
P3.6 WR WR control output; latches the data byte

from port 0 into the external data

memory
P3.7 RD RD control output; enables the external

data memory

N.C. 2 - 5, 25,

28, 29, 32,
43, 44,

– Not connected

These pins of the P-MQFP-100 package need not be
connected.

51 - 53,
74 - 77
88, 89

*) I = Input

O = Output

Semiconductor Group 12 1997-10-01

XTAL1

XTAL2

Oscillator Watchdog

OSC & Timing

256 x 8

XRAMRAM

2k x 8

C517A

ROM

32k x 8

ALE

PSEN

EA

PE/SWD

RESET

HWPD

RO

OWE

CPU

8 Datapointer

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

Capture

Compare Unit

Compare Timer

Serial Channel 0

Programmable

Baud Rate Generator

Serial Channel 1

Programmable

Baud Rate Generator

Interrupt Unit

Emulation

Support

Logic

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 0
8-Bit Digital I/O

Port 1
8-Bit Digital I/O

Port 2
8-Bit Digital I/O

Port 3
8-Bit Digital I/O

Port 4
8-Bit Digital I/O

Port 5
8-Bit Digital I/O

Port 6
8-Bit Digital I/O

V

V

AGND

AREF

A/D Converter

S & H

10 Bit

Analog

MUX

Port 7

Port 8

Port 7
8-Bit Analog/
Digital Input

Port 8
4-Bit Analog/
Digital Input

C517A

MCB03320

Figure 4
Block Diagram of the C517A

Semiconductor Group 13 1997-10-01

C517A

CPU

The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1µs (24 MHz:
500 ns).

Special Function Register PSW (Address D0H) Reset Value : 00

Bit No. MSB LSB

D7

H

Bit Function

CY Carry Flag

AC Auxiliary Carry Flag

F0 General Purpose Flag
RS1

RS0

CY AC

D6

H

Used by arithmetic instruction.

Used by instructions which execute BCD operations.

Register Bank select control bits
These bits are used to select one of the four register banks.

RS1 RS0 Function

H

D5

F0

H

D4
RS1 RS0 OV F1 PD0

H

D3

H

D2

H

D1

H

D0

H

PSW

H

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

OV Overflow Flag

Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of “one” bits in the accumulator, i.e. even parity.

Semiconductor Group 14 1997-10-01

H
H
H
H

Memory Organization

The C517A CPU manipulates operands in the following five address spaces:

– up to 64 Kbyte of program memory (32K on-chip program memory for C517A-4R)
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– 2K bytes of internal XRAM data memory
– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C517A.

FFFF

H

ext.

FFFF

H

int.

(XMAP0 = 0) (XMAP0 = 1)

ext.

C517A

int.

"Code Space"

ext.

(EA = 0)(EA = 1)

Figure 5
C517A Memory Map

8000

H

7FFF

0000

F800

H

F7FF

H

H

ext.

H

"Data Space" "Internal Data Space"

0000

H

Indirect

Address Address

FF

Internal

RAM

80

Internal

RAM

H

H

Direct

Special

Function

Regs.

7F

H

00

H

FF

H

80

H

MCB03321

Semiconductor Group 15 1997-10-01

C517A

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.

b)a)

&

Figure 6
Reset Circuitries

+

RESET

C517A

c)

+

RESET

RESET

C517A

C517A

MCS03323

Semiconductor Group 16 1997-10-01

C517A

Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation.

Crystal Oscillator Mode Driving from External Source

C

3.5 - 24
MHz

C

Crystal Mode: C = 20 pF 10 pF

(Incl. Stray Capacitance)

Figure 7
Recommended Oscillator Circuitries

XTAL1

XTAL2

N.C.

External Oscillator
Signal

XTAL1

XTAL2

MCS03245

Semiconductor Group 17 1997-10-01

C517A

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

1)

The Enhanced Hooks Technology
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

TM

, which requires embedded logic in the C500 allows the C500

SYSCON

PCON

TCON

opt.

I/O Ports

C500
MCU

RESET

EA

ALE

PSEN
Port 0

Port 2

Port 1Port 3

Target System Interface

RPORT RPORT

ICE-System interface

to emulation hardware

RSYSCON

RPCON
RTCON

Enhanced Hooks

Interface Circuit

2

0

EH-IC

TEA TALE TPSEN

MCS03254

Figure 8
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the program execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1 “Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 18 1997-10-01

C517A

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.

The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. All
SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, …, F8H, FFH) are
bitaddressable. The SFRs of the C517A are listed in table 3 and table 4. In table 3 they are
organized in groups which refer to the functional blocks of the C517A. Table 4 illustrates the
contents of the SFRs in numeric order of their addresses.

Semiconductor Group 19 1997-10-01

C517A

Table 3
Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B
DPH
DPL
DPSEL
PSW
SP

A/D­Converter

ADCON0

ADCON1
ADDATH
ADDATL

Interrupt
System

IEN0
IEN1

2)

2)

IEN2

2)

IP0
IP1
IRCON0
IRCON1
TCON
T2CON
S0CON
CTCON

MUL/DIV
Unit

ARCON
MD0
MD1
MD2
MD3
MD4
MD5

Timer 0 /
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) ‘X’ means that the value is undefined and the location is reserved

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer

2)

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register, High Byte
A/D Converter Data Register, Low Byte

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
Interrupt Priority Register 1

2)

Interrupt Request Control Register 0
Interrupt Request Control Register 1

2)

Timer 0/1 Control Register

2)

Timer 2 Control Register

2)

Serial Channel 0 Control Register

2)

Compare Timer Control Register
Arithmetic Control Register

Multiplication/Division Register 0
Multiplication/Division Register 1
Multiplication/Division Register 2
Multiplication/Division Register 3
Multiplication/Division Register 4
Multiplication/Division Register 5

2)

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

E0
F0

83
82
92

D0

81

D8

DC
D9
DA

A8
B8

9A
A9
B9

C0

D1

88
C8
98

E1
EF

E9
EA
EB
EC
ED
EE

88

8C
8D
8A
8B
89

H

H
H
H

H

H

H

H

H

H

H

H

H

H
H

H
H
H

H

H

H

H
H

H

H
H
H
H

H
H
H
H
H

H

H

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

00

H

00

H

00

H

00

H

XXXX X000
00

H

07

H

00

H

0XXX 0000
00

H

00XX XXXX
00

H

00

H

XX00 00X0
00

H

XX00 0000
00

H

00

H

00

H

00

H

00

H

0X00 0000
0XXXXXXX

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

00

H

00

H

00

H

00

H

00

H

00

H

3)

B

3)

B

3

B

3)

B

3)

B

3)

B

3)

B

Semiconductor Group 20 1997-10-01

C517A

Table 3
Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Compare/
Capture
Unit
(CCU)
Timer 2

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) ‘X’ means that the value is undefined and the location is reserved

CCEN
CC4EN
CCH1
CCH2
CCH3
CCH4
CCL1
CCL2
CCL3
CCL4
CMEN
CMH0
CMH1
CMH2
CMH3
CMH4
CMH5
CMH6
CMH7
CML0
CML1
CML2
CML3
CML4
CML5
CML6
CML7
CMSEL
CRCH
CRCL

COMSETL
COMSETH
COMCLRL
COMCLRH

SETMSK
CLRMSK
CTCON

2)

CTRELH
CTRELL
TH2
TL2
T2CON

2)

IRCON0

Compare/Capture Enable Register
Compare/Capture 4 Enable Register
Compare/Capture Register 1, High Byte
Compare/Capture Register 2, High Byte
Compare/Capture Register 3, High Byte
Compare/Capture Register 4, High Byte
Compare/Capture Register 1, Low Byte
Compare/Capture Register 2, Low Byte
Compare/Capture Register 3, Low Byte
Compare/Capture Register 4, Low Byte
Compare Enable Register
Compare Register 0, High Byte
Compare Register 1, High Byte
Compare Register 2, High Byte
Compare Register 3, High Byte
Compare Register 4, High Byte
Compare Register 5, High Byte
Compare Register 6, High Byte
Compare Register 7, High Byte
Compare Register 0, Low Byte
Compare Register 1, Low Byte
Compare Register 2, Low Byte
Compare Register 3, Low Byte
Compare Register 4, Low Byte
Compare Register 5, Low Byte
Compare Register 6, Low Byte
Compare Register 7, Low Byte
Compare Input Select
Comp./Rel./Capt. Register High Byte
Comp./Rel./Capt. Register Low Byte
Compare Set Register Low Byte
Compare Set Register, High Byte
Compare Clear Register, Low Byte
Compare Clear Register, High Byte
Compare Set Mask Register
Compare Clear Mask Register
Compare Timer Control Register
Compare Timer Rel. Register, High Byte
Compare Timer Rel. Register, Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register

2)

Interrupt Request Control Register 0

C1
C9
C3
C5
C7
CF
C2
C4
C6
CE
F6
D3
D5
D7
E3
E5
E7
F3
F5
D2
D4
D6
E2
E4
E6
F2
F4
F7
CB
CA
A1
A2
A3
A4
A5
A6
E1
DF
DE
CD
CC

C8
C0

H

H
H

H
H
H

H
H
H
H
H

H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H
H

H
H

H

H

H
H

H
H

H
H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

0X00 0000
00

H

00

H

00

H

00

1)

1)

00
00

H
H
H

B

3

)

Semiconductor Group 21 1997-10-01

C517A

Table 3
Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Ports P0

P1
P2
P3
P4
P5
P6
P7
P8

XRAM XPAGE

SYSCON

Serial
Channels

ADCON0
PCON
S0BUF
S0CON
S0RELL
S0RELH
S1BUF
S1CON
S1RELL
S1RELH

IEN1
IP0

2)

2)

2)

Watchdog IEN0

WDTREL

Pow. Sav.

PCON

Modes

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7, Analog/Digital Input
Port 8, Analog/Digital Input, 4-bit

Page Address Register for Extended
On-Chip RAM

2)

System/XRAM Control Register

2)

A/D Converter Control Register

2)

Power Control Register
Serial Channel 0 Buffer Register
Serial Channel 0 Control Register
Serial Channel 0 Reload Reg., Low Byte
Serial Channel 0 Reload Reg., High Byte
Serial Channel 1 Buffer Register
Serial Channel 1 Control Register
Serial Channel 1 Reload Reg., Low Byte
Serial Channel 1 Reload Reg., High Byte

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Watchdog Timer Reload Register

2)

Power Control Register 87

80
90
A0
B0
E8
F8

FA
DB
DD

91

B1

D8

87
99

98

AA
BA
9C
9B
9D
BB

A8
B8

A9
86

H
H

H

H

H
H

H

H
H

H
H
H

H

H

H

H
H
H

H
H

H

H

H
H

H

H

1)

1)

1)

1)

1)

1)

FF
FF
FF
FF
FF
FF
FF

H
H
H
H
H
H
H

–
–

00

H

XXXX XX01

1)

1)

00

00
XX

00

D9

H

H

H

H

H

3

)

XXXX XX11

3

XX

)

H

0X00 0000
00

H

XXXX XX11

1)

1)

00
00
00
00

00

H
H
H
H

H

3)

B

B

3)

B

B

3)

3)

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) ‘X’ means that the value is undefined and the location is reserved.

Semiconductor Group 22 1997-10-01

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses

C517A

Addr Register Content

after
Reset

2)

80
81
82
83
83

87
88
89

P0 FF

H

SP 07

H

DPL 00

H

DPH 00

H

WDTREL 00

H

PCON 00

H

2)

TCON 00

H

TMOD 00

H

8AHTL0 00
8BHTL1 00
8CHTH0 00
8DHTH1 00

2)

90

P1 FF

H

1)

H
H
H
H
H

H
H
H
H
H
H
H

H

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
WDT-

.6 .5 .4 .3 .2 .1 .0

PSEL
SMOD PDS IDLS SD GF1 GF0 PDE IDLE
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
GATE C/

T M1 M0 GATE C/TM1 M0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
T2 CLK-

T2EX INT2 INT6 INT5 INT4 INT3

OUT
91
92

98
99
9AHIEN2 XX00-

9BHS1CON 0X00-

9CHS1BUF XX
9DHS1RELL 00
A0
A1
A2
A3

1) ‘X’ means that the value is undefined and the location is reserved

2) Shaded registers are bit-addressable special function registers

XPAGE 00

H

DPSEL XXXX-

H

2)

S0CON 00

H

S0BUF XX

H

2)

P2 FF

H

COMSETL

H

COMSETH

H

COMCLRL

H

H

X000

H

H

00X0

0000

H

H

H

00

H

00

H

00

H

.7 .6 .5 .4 .3 .2 .1 .0
–––––.2.1.0

B

SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0
.7 .6 .5 .4 .3 .2 .1 .0
– – ECR ECS ECT ECMP – ES1

B

SM – SM21 REN1 TB81 RB81 TI1 RI1

B

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 23 1997-10-01

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C517A

Addr Register Content

after
Reset

A4

COMCLRH

H

00
A5HSETMSK 00
A6HCLRMSK 00

2)

A8

IEN0 00

H

A9HIP0 00
AAHS0RELL D9

2)

B0

P3 FF

H

1)

H
H
H
H
H

H
H

B1HSYSCON XXXX-

XX01

B

2)

B8

IEN1 00

H

H

B9HIP1 XX00-

0000

B

BAHS0RELH XXXX-

XX11

B

BBHS1RELH XXXX-

XX11

B

2)

C0
C1HCCEN 00

IRCON0 00

H

H
H

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
EAL WDT ET2 ES0 ET1 EX1 ET0 EX0
OWDS WDTS .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
RD WR T1 T0 INT1 INT0 TxD0 RxD0
––––––

XMAP1 XMAP0

EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC
– – .5.4.3.2.1.0

––––––.1.0

––––––.1.0

EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC
COCAH3COCAL3COCAH2COCAL2COCAH1COCAL1COCAH0COCA

L0
C2HCCL1 00
C3HCCH1 00
C4HCCL2 00
C5HCCH2 00
C6HCCL3 00
C7HCCH3 00

2)

C8

T2CON 00

H

C9HCC4EN 00

1) ‘X’ means that the value is undefined and the location is reserved

2) Shaded registers are bit-addressable special function registers

H
H
H
H
H
H
H
H

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0

COCO

EN1

COCON2COCON1COCON0COCO

EN0

COCAH4COCAL4COMO

Semiconductor Group 24 1997-10-01

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C517A

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

1)

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
CY AC F0 RS1 RS0 OV F1 P
ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
BD CLK ADEX BSY ADM MX2 MX1 MX0
.9 .8 .7 .6 .5 .4 .3 .2
.1.0––––––

B

Reset

CAHCRCL 00
CBHCRCH 00
CCHTL2 00
CDHTH2 00
CEHCCL4 00
CFHCCH4 00

2)

D0

PSW 00

H

D1HIRCON1 00
D2HCML0 00
D3HCMH0 00
D4HCML1 00
D5HCMH1 00
D6HCML2 00
D7HCMH2 00

2)

D8

ADCON0 00

H

D9HADDATH 00
DAHADDATL 00XX-

XXXX
DBHP7 – .7.6.5.4.3.2.1.0
DCHADCON1 0XXX-

0000

ADCL – – – MX3 MX2 MX1 MX0

B

DDHP8 – ––––.3.2.1.0
DEHCTRELL 00
DFHCTRELH 00

2)

E0

ACC 00

H

H
H
H

E1HCTCON 0X00.

0000
E2HCML3 00

1) ‘X’ means that the value is undefined and the location is reserved

2) Shaded registers are bit-addressable special function registers

H

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
T2PS1 – ICR ICS CTF CLK2 CLK1 CLK0

B

.7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 25 1997-10-01

Table 4
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C517A

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H
H
H
H
H

H
H
H
H
H
H
H

H

H
H

H
H
H
H
H
H

1)

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
MDEF MDOV SLR SC.4 SC.3 SC.2 SC.1 SC.0

B

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
CCM7 CCM6 CCM5 CCM4 CCM3 CCM2 CCM1 CCM0
.7 .6 .5 .4 .3 TxD1 RxD1 ADST

Reset

E3HCMH3 00
E4HCML4 00
E5HCMH4 00
E6HCML5 00
E7HCMH5 00

2)

E8

P4 FF

H

E9HMD0 XX
EAHMD1 XX
EBHMD2 XX
ECHMD3 XX
EDHMD4 XX
EEHMD5 XX
EFHARCON 0XXX.

XXXX

2)

F0

B 00

H

F2HCML6 00
F3HCMH6 00
F4HCML7 00
F5HCMH7 00
F6HCMEN 00
F7HCMSEL 00

2)

F8

P5 FF

H

FAHP6 FF

1) ‘X’ means that the value is undefined and the location is reserved

2) Shaded registers are bit-addressable special function registers

Semiconductor Group 26 1997-10-01

C517A

Digital I/O Ports

The C517A allows for digital I/O on 56 lines grouped into 7 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P6 are performed via their corresponding special function registers P0 to P6.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time­multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.

Analog Input Ports

Ports 7 (8-bit) an 8 (4-bit) are input ports only and provide two functions. When used as digital
inputs, the corresponding SFR P7 and P8 contains the digital value applied to the port 7/8 lines.
When used for analog inputs the desired analog channel is selected by a four-bit field in SFR
ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the
SFR P7 or P8. This will have no effect.

If a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(VIL/VIH). Since P7 and P8 are not bit-addressable, all input lines of P7 and P8 are read at the same
time by byte instructions.

Nevertheless, it is possible to use port 7 and 8 simultaneously for analog and digital input. However,
care must be taken that all bits of P7 and P8 that have an undetermined value caused by their
analog function are masked.

Semiconductor Group 27 1997-10-01

Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 5:
Table 5

Timer/Counter 0 and 1 Operating Modes
Mode Description TMOD Input Clock

M1 M0 internal external (max)

C517A

0 8-bit timer/counter with a

00 f

/12x32 f

OSC

OSC

/24x32

divide-by-32 prescaler
1 16-bit timer/counter 1 1
2 8-bit timer/counter with

10

8-bit autoreload
3 Timer/counter 0 used as one

11

/12 f

OSC

OSC

/24

f

8-bit timer/counter and one

8-bit timer

Timer 1 stops

In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is f

OSC

/12.

In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is f

/24. External inputs INT0 and INT1 (P3.2, P3.3) can be

OSC

programmed to function as a gate to facilitate pulse width measurements. Figure 9 illustrates the
input clock logic.

f

/12

OSC

Timer 0/1
Input Clock

P3.4/T0
P3.5/T1
max

P3.2/INT0
P3.3/INT1

f

OSC

/24

f

OSC

TR 0/1

TCON

Gate

TMOD

=1

÷

12

C/T

TMOD

0

1

Control

&

_

<

1

MCS01768

Figure 9
Timer/Counter 0 and 1 Input Clock Logic

Semiconductor Group 28 1997-10-01

C517A

Compare / Capture Unit (CCU)

The compare/capture unit is one of the C517A’s most powerful peripheral units for use in all kinds
of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse
width measuring etc. The CCU consists of two 16-bit timer/counters with automatic reload feature
and an array of 13 compare or compare/capture registers. A set of six control registers is used for
flexible adapting of the CCU to a wide variety of user’s applications.

The block diagram in figure 10 shows the general configuration of the CCU. All CC1 to CC4
registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare
registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to
provide up to 8 PWM output channels. The assignment of the CMx registers - which can be done
individually for every single register - is combined with an automatic selection of one of the two
possible compare modes.

(CTREL)

16-bit Reload

Compare Timer

Prescaler

Max.Clock = /2

Timer 2

Prescaler

Max.Clock =

f

f

OSC

OSC

/12

(CM0)

8x

16-bit

Compare

(CM7)

Capt./Comp.

Capt./Comp. 3 (CC3)
Capt./Comp. 2 (CC2)

Capt./Comp.1 (CC1)
16-bit Rel.Capt. (CRC)

Comp.

4 (CC4)

"Internal Bus"

Shadow

Latch

Port

Control

Logik

CC4EN

Port

Control

Logik

P4­I/O-

Latch

P5­I/O-

Latch

P1­I/O-

Latch

MCB01577

Figure 10
Timer 2 Block Diagram

Semiconductor Group 29 1997-10-01

The main functional blocks of the CCU are:

C517A

– Timer 2 with f

/12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and

OSC

overflow interrupt request.

– Compare timer with f

/2 input clock, 3-bit prescaler, 16-bit reload and overflow interrupt

OSC

request.

– Compare/(reload/) capture register array consisting of four different kinds of registers:

one 16-bit compare/reload/capture register,
three 16-bit compare/capture registers,
one 16-bit compare/capture register with additional “concurrent compare” feature,
eight 16-bit compare registers with timer-overflow controlled loading.

Table 6 shows the possible configurations of the CCU and the corresponding compare modes
which can be selected. The following sections describe the function of these configurations.

Table 6
CCU Configurations

Assigned
Timer

Timer 2 CRCH/CRCL

Compare
Register

CCH1/CCL1
CCH2/CCL2
CCH3/CCL3
CCH4/CCL4

Compare Output at Possible Modes

P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2/CC4

Compare mode 0, 1 + Reload
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture

Compare
Timer

CCH4/CCL4 P1.4/INT2/CC4

P5.0/CCM0

to

P5.7/CCM7

CMH0/CML0

to

CMH7/CML7
COMSET

COMCLR

P4.0/CM0

to

P4.7/CM7
P5.0/CCM0

to

P5.7/CCM7

CMH0/CML0

to

CMH7/CML7

P4.0/CM0

to

P4.7/CM7

Compare mode 1
“Concurrent compare“

Compare mode 0

Compare mode 2

Compare mode 1

Semiconductor Group 30 1997-10-01

C517A

Timer 2 Operation

Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.

Gated Timer Mode: In gated timer function, the external input pin P1.7/T2 operates as a gate to the
input of timer 2. If T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting
procedure. The external gate signal is sampled once every machine cycle.

Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a
1-to-0 transition at its corresponding external input pin P1.7/T2. In this function, the external input is
sampled every machine cycle. The maximum count rate is 1/24 of the oscillator frequency.
Reload of Timer 2: Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the
timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the
corresponding input pin P1.5/T2EX.

P1.7/T2

OSC

TL2 TH2

(8 Bits) (8 Bits)

Programmable

Prescaler

T2PS T2PS1

T2I1

T2I0

00

01

10

11

SFR T2CON

No input selected

Timer stop

Timer function

Counter function

via ext. input P1.7/T2

Gated timer function

by ext. input P1.7/T2

TF2

Timer 2
Input Clock

_

<

1

Interrupt

P1.5/T2EX

Sync

EXEN2

EXF2

_

<

1

Reload

MCB03328

Figure 11
Block Diagram of Timer 2

Semiconductor Group 31 1997-10-01

C517A

Compare Timer Operation

The compare timer receives its input clock from a programmable prescaler which provides input
frequencies, ranging from f
16-bit timer, which on overflow is automatically reloaded by the contents of a 16-bit reload register.
The compare timer has - as any other timer in the C517A - their own interrupt request flags CTF.
These flags are set when the timer count rolls over from all ones to the reload value. Figure 12
shows the block diagram of compare timer and compare timer 1.

f

/2

OSC

/2 up to f

OSC

3-Bit Prescaler

/2 /4 /8 /16 /32 /64 /128

/256. The compare timer is, once started, a free-running

OSC

Compare Timer

16-Bit Compare Timer

16-Bit Reload (CTREL)

Figure 12
Compare Timer Block Diagram

Control (CTCON)

CTF

Overflow

16

To Compare
Circuitry

To Interrupt
Circuitry

MCB00783

Semiconductor Group 32 1997-10-01

C517A

Compare Modes

The compare function of a timer/register combination operates as follows: the 16-bit value stored in
a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.

Compare Mode 0
In compare mode 0, upon matching the timer and compare register contents, the output signal

changes from low to high. It goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 13 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Compare Register

Circuit

Compare Reg.

16 Bit

Comparator

Bit16

Timer Register

Timer Circuit

Compare
Match

Timer
Overflow

Figure 13
Port Latch in Compare Mode 0

Port Circuit

Internal
Bus

Write to
Latch

S
D

Latch

CLK
R

Read Latch

Q

Port

Q

Read Pin

V

CC

Port

Pin

MCS02661

Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the

new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.

In compare mode 1 (see figure 14) the port circuit consists of two separate latches. One latch
(which acts as a “shadow latch”) can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Semiconductor Group 33 1997-10-01

Port Circuit

C517A

Compare Register

Circuit

Compare Reg.

16 Bit

Comparator

16 Bit

Timer Register

Timer Circuit

Compare
Match

Internal
Bus

Write to
Latch

D

Shadow

Latch

CLK

Read Latch

Q

D

Q

Port

Latch

QCLK

Read Pin

V

CC

Port

Pin

MCS02662

Figure 14
Compare Function in Compare Mode 1

Compare Mode 2
In the compare mode 2 the port 5 pins are under control of compare/capture register CC4, but under

control of the compare registers COMSET and COMCLR. When a compare match occurs with
register COMSET, a high level appears at the pins of port 5 when the corresponding bits in the mask
register SETMSK are set. When a compare match occurs with register COMCLR, a low level
appears at the pins of port 5 when the corresponding bits in the mask register CLRMSK are set.

COMSET

16 Bit

Comparator

16 Bit

TH2

Comparator

TL2

Timer 2

COMCLR

Bit16

Bit16

Compare
Signal

Compare
Signal

SETMSK

Bits

CLRMSK

Bits

Figure 15
Compare Function of Compare Mode 2

Port Circuit

Internal
Bus

Write to
Latch

S
D

Latch

CLK
R

Read Latch

Q

Port

Q

Read Pin

V

CC

Port

Pin

MCS02663

Semiconductor Group 34 1997-10-01

C517A

Multiplication / Division Unit (MDU)

This on-chip arithmetic unit of the C517A provides fast 32-bit division, 16-bit multiplication as well
as shift and normalize features. All operations are unsigned integer operations. Table 7 describes
the five general operations the MDU is able to perform.

Table 7
MDU Operation Characteristics

Operation Result Remainder Execution Time

1)

32bit/16bit
16bit/16bit
16bit x 16bit
32-bit normalize
32-bit shift L/R

32bit
16bit
32bit
–
–

16bit
16bit
–
–
–

6
4 t
4 t
6 t
6 t

t

CY

1)

CY

1)

CY

2)

CY

2)

CY

1) 1 tCY = 12 t

2) The maximal shift speed is 6 shifts per machine cycle

= 1 machine cycle = 500 ns at 24 MHz oscillator frequency

CLCL

The MDU consists of seven special function registers (MD0-MD5, ARCON) which are used as
operand, result, and control registers. The three operation phases are shown in figure 16.

Figure 16
Operating Phases of the MDU

Semiconductor Group 35 1997-10-01

C517A

For starting an operation, registers MD0 to MD5 and ARCON must be written to in a certain
sequence according table 8 and 9. The order the registers are accessed determines the type of the
operation. A shift operation is started by a final write operation to SFR ARCON.

Table 8
Programming the MDU for Multiplication and Division

Operation 32Bit/16Bit 16Bit/16Bit 16Bit x 16Bit

First Write

MD0 D’endL
MD1 D’end

MD0 D’endL
MD1 D’endH

MD0 M’andL

MD4 M’orL
MD2 D’end
MD3 D’endH

MD4 D’orL

MD1 M’andH
MD4 D’orL

Last Write
First Read

MD5 D’orH
MD0 QuoL

MD1 Quo

MD5 D’orH
MD0 QuoL

MD1 QuoH

MD5 M’orH

MD0 PrL

MD1
MD2 Quo
MD3 QuoH

MD4 RemL

MD2
MD4 RemL

Last Read

Abbreviations:

D'end : Dividend, 1st operand of division
D'or : Divisor, 2nd operand of division
M'and : Multiplicand, 1st operand of multiplication
M'or : Multiplicator, 2nd operand of multiplication
Pr : Product, result of multiplication
Rem : Remainder
Quo : Quotient, result of division
...L : means, that this byte is the least significant of the 16-bit or 32-bit operand
...H : means, that this byte is the most significant of the 16-bit or 32-bit operand

MD5 RemH

MD5 RemH

MD3 PrH

Table 9
Programming of the MDU for a Shift or Normalize Operation

Operation Normalize, Shift Left, Shift Right

First write

MD0 least significant byte
MD1 .
MD2 .
MD3 most significant byte

Last write
First read

ARCON start of conversion
MD0 least significant byte

MD1 .
MD2 .

Last read

MD3 most significant byte

Semiconductor Group 36 1997-10-01

C517A

Serial Interfaces 0 and 1

The C517A has two serial interfaces which are functionally nearly identical concerning the
asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit
and receive simultaneously. The serial channel 0 is completely compatible with the serial channel
of the C501 (one synchronous mode, three asynchronous modes). Serial channel 1 has the same
functionality in its asynchronous modes, but the synchronous mode and the fixed baud rate UART
mode is missing.

The operating modes of the serial interfaces is illustrated in table 10. The possible baudrates can
be calculated using the formulas given in table 11.

Table 10
Operating Modes of Serial Interface 0 and 1

Serial
Interface

0 0 0 0 – Shift register mode

1 A – – 0 9-bit UART; variable baud rate

Mode S0CON S1CON Description

SM0 SM1 SM

Serial data enters and exits through R×D0;
T×D0 outputs the shift clock; 8-bit are
transmitted/received (LSB first); fixed baud rate

1 0 1 – 8-bit UART, variable baud rate

10 bits are transmitted (through T×D0) or
received (at R×D0)

2 1 0 – 9-bit UART, fixed baud rate

11 bits are transmitted (through T×D0) or
received (at R×D0)

3 1 1 – 9-bit UART, variable baud rate

Like mode 2

11 bits are transmitted (through T×D1) or
received (at R×D1)

B – – 1 8-bit UART; variable baud rate

10 bits are transmitted (through T×D1) or
received (at R×D1)

Semiconductor Group 37 1997-10-01

C517A

For clarification some terms regarding the difference between “baud rate clock” and “baud rate”
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a “baud rate clock” (output signal infigure 17and figure 18) to the serial interface which -

there divided by 16 - results in the actual “baud rate”. Further, the abbreviation f

oscillator frequency (crystal or external clock operation).
The variable baud rates for modes 1 and 3 of the serial interface 0 can be derived from either timer 1

or a dedicated baud rate generator (see figure 17). The variable baud rates for modes A and B of
the serial interface 1 are derived from a dedicated baud rate generator as shown in figure 18.

Timer 1 Overflow

S0CON.7
S0CON.6

(SM0/

SM1)

÷ 2

PCON.7
(SMOD)

0
1

f

OSC

/2

Baud

Rate

Generator

(S0RELH

S0RELL)

ADCON0.7

(BD)

0
1

Mode 1
Mode 3

Mode 2

Mode 0

refers to the

OSC

Baud
Rate
Clock

÷ 6

Note : The switch configuration shows the reset state.

Only one mode

can be selected

Figure 17
Serial Interface 0 : Baud Rate Generation Configuration

Baud Rate Generator

S1RELH .1 .0 S1RELL

f

/2

OSC

Input Clock

10-Bit Timer

Owerflow

MCS03331

MCS03329

Baud
Rate
Clock

Figure 18
Serial Interface 1 : Baud Rate Generator Configuration

The baud rate generator block in figure 17 has the same structure (10-bit auto-reload timer) as the
baud rate generator block which is shown in detail in figure 18.

Semiconductor Group 38 1997-10-01

C517A

Table 11 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with

its dependencies of the control bits BD and SMOD.

Table 11
Serial Interfaces - Baud Rate Dependencies

Serial Interface
Operating Modes

Active Control
Bits

Baud Rates

SMOD BD

Mode 0 (Shift Register) – – Fixed baud rate clock fosc/12
Mode 1 (8-bit UART)

Mode 3 (9-bit UART)

X 0 Timer 1 overflow is used for baud rate

generation; SMOD controls a divide-by-2 option.
Baud rate = 2

SMOD

x timer 1 overflow rate / 32

1 Baud rate generator is used for baud rate

generation; SMOD controls a divide-by-2 option
Baud rate = 2

SMOD

x oscillator frequency /

64 x (baud rate gen. overflow rate)

Mode 2 (9-bit UART) X – Fixed baud rate clock fosc/32 (SMOD=1) or fosc/

64 (SMOD=0)

Mode A (9-bit UART)
Mode B (8-bit UART)

– – Baud rate generator is used for baud rate

generation; SMOD controls a divide-by-2 option
Baud rate = oscillator frequency /

32 x (baud rate gen. overflow rate)

Semiconductor Group 39 1997-10-01

C517A

10-Bit A/D Converter

The C517A provides an A/D converter with the following features:

– 12 multiplexed input channels (port 7, 8), which can also be used as digital inputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal or external start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors

The A/D converter operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The externally applied
reference voltage range has to be held on a fixed value within the specifications. The main
functional blocks of the A/D converter are shown in figure 19.

Semiconductor Group 40 1997-10-01

C517A

IEN1 (B8 )

H

SWDTEXEN2 EX6

IRCON0 (C0 )

EXF2

P8 (DD )

P7 (DB )

H

TF2

H

_

__

H

IEX6

EX5

IEX5

EX4 EX3 EX2

IEX4

_

P8.3

IEX3

IEX2

P8.2 P8.1

P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0

ADCON1 (DC )

ADCL

ADCON0 (D8 )

BD

H

__

_

H

CLK

ADEX

BSY

MX3

ADM

MX2 MX1

MX2 MX1

internal

Bus

EADC

IADC

P8.0

MX0

MX0

Port 7

Port 8

MUX

S&H

f

OSC

/2

Clock

Prescaler

÷8, ÷4

Conversion
Clock

f

ADC

Input

V

AREF

V

AGND

Clock

f

IN

P6.0/ADST
Write to ADDATL

Shaded bit locations are not used in ADC-functions

Single/
Continuous Mode

A/D

Converter

Start of
Conversion

ADDATH ADDATL

)(D9 (DA )

HH

.2
.3
.4
.5
.6
.7
.8

MSB

_
_
_
_
_
_

LSB

.1

internal

MCB03332

Bus

Figure 19
A/D Converter Block Diagram

Semiconductor Group 41 1997-10-01

C517A

Interrupt System

The C517A provides 17 interrupt sources with four priority levels. Ten interrupts can be generated
by the on-chip peripherals (timer 0, timer 1, timer 2, compare timer, compare match/set/clear, A/D
converter, and serial interface 0 and 1) and seven interrupts may be triggered externally (P3.2/INT0,
P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6).

This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special
function registers. Figure 20 to 22 give a general overview of the interrupt sources and illustrate the
request and the control flags which are described in the next sections.

Semiconductor Group 42 1997-10-01

P3.2/
INT0

UART 1

IT0

TCON.0

RI1

S1CON.0

TI1

S1CON.1

IE0

TCON.1

_

<

1

EX0

IEN0.0

ES1

IEN2.0

0003

0083

C517A

Highest

Priority Level

H

Lowest

Priority Level

H

A/D Converter

Timer 0
Overflow

P1.4/
INT2/

CC4

I2FR

T2CON.5

Bit addressable
Request Flag is

cleared by hardware

IADC

IRCON0.0

TF0

TCON.5

IEX2

IRCON0.1

EADC

IEN1.0

ET0

IEN0.1

EX2

IEN1.1

0043

H

000B

H

004B

H

EAL

IEN0.7

IP1.0

IP0.0

Polling Sequence

IP0.1IP1.1

MCS03333

Figure 20
Interrupt Structure, Overview (Part 1)

Semiconductor Group 43 1997-10-01

P3.3/
INT1

IT1

TCON.2

IE1

TCON.3

EX1

IEN0.2

0013

C517A

Highest

Priority Level

H

Lowest

Priority Level

Match in CM0-CM7

P1.0/
INT3/

CC0

I3FR

T2CON.5

Timer 1
Overflow

Compare Timer
Overflow

P1.1/
INT4/

CC1

ICMP0-7

IRCON1.0-7

IEX3

IRCON0.2

TF1

TCON.7

CTF

CTCON.3

IEX4

IRCON0.3

ECMP

IEN2.2

EX3

IEN1.2

ET1

IEN0.3

ECT

IEN2.3

EX4

IEN1.3

0093

0053

001B

009B

005B

H

H

IP1.2

H

H

H

IP0.2

Polling Sequence

EAL

IEN0.7

Bit addressable
Request Flag is

cleared by hardware

IP0.3IP1.3

MCS03334

Figure 21
Interrupt Structure, Overview (Part 2)

Semiconductor Group 44 1997-10-01

C517A

USART 0

Match in COMSET

P1.2/
INT5/
CC2

Timer 2
Overflow

P1.5/
T2EX

EXEN2

IEN1.7

RI0

S0CON.0

TI0

S0CON.1

TF2

IRCON0.6

EXF2

IRCON0.7

_

<

1

ICS

CTCON.4

IEX5

IRCON0.4

_

<

1

ES0

IEN0.4

ECS

IEN2.4

EX5

IEN1.4

ET2

IEN0.5

0023

00A3

0063

002B

Highest

Priority Level

H

Lowest

Priority Level

H

H

IP1.4

H

IP0.4

Polling Sequence

Match in COMCLR

P1.3/
INT6/
CC3

Bit addressable
Request Flag is

cleared by hardware

ICR

CTCON.5

IEX6

IRCON0.5

Figure 22
Interrupt Structure, Overview (Part 3)

ECR

IEN2.5

EX6

IEN1.5

00AB

H

006B

H

EAL

IEN0.7

IP0.5IP1.5

MCS03335

Semiconductor Group 45 1997-10-01

C517A

Table 12
Interrupt Source and Vectors

Interrupt Source Interrupt Vector Address Interrupt Request Flags

External Interrupt 0 0003
Timer 0 Overflow 000B
External Interrupt 1 0013
Timer 1 Overflow 001B
Serial Channel 0 0023
Timer 2 Overflow / Ext. Reload 002B
A/D Converter 0043
External Interrupt 2 004B
External Interrupt 3 0053
External Interrupt 4 005B
External Interrupt 5 0063
External Interrupt 6 006B
Serial Channel 1 0083
Compare Match Interrupt of

Compare Registers CM0-CM7
assigned to Timer 2

0093

H

H

H

H

H

H

H
H

H

H

H

H

H

H

IE0
TF0
IE1
TF1
RI0 / TI0
TF2 / EXF2
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
RI1 / TI1
ICMP0 - ICMP7

Compare Timer Overflow 009B
Compare Match Interrupt of

Compare Register COMSET
Compare Match Interrupt of

Compare Register COMCLR

00A3

00AB

H
H

H

CTF
ICS

ICR

Semiconductor Group 46 1997-10-01

C517A

Fail Save Mechanisms

The C517A offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure:

– a programmable watchdog timer (WDT), with variable time-out period from 512 µs up to

approx. 1.1 s at 12 MHz. (256 µs up to approx. 0.65 s at 24 MHz)

– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.

The watchdog timer in the C517A is a 15-bit timer, which is incremented by a count rate of f
up to f

/384. The system clock of the C517A is divided by two prescalers, a divide-by-two and a

OSC

OSC

/24

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the
watchdog timer can be written. Figure 23 shows the block diagram of the watchdog timer unit.

07

f

/12

OSC

2

16

14

WDTL

8

WDT Reset-Request

WDTH

IP0 (A9 )

- ------

WDTS

H

WDTPSEL

External HW Reset
External HW Power-Down

PE/SWD

670

WDTREL (86 )

H

Control Logic

-

WDT

-

SWDT

-- -- --

-- -- --

IEN0 (A8 )
IEN1 (B8 )

H
H

MCB03250

Figure 23
Block Diagram of the Watchdog Timer

The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C517A. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consecutive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.

Semiconductor Group 47 1997-10-01

Oscillator Watchdog

The oscillator watchdog unit serves for four functions:

– Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on­chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset
phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset
is released and the part starts program execution again.

– Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.

– Restart from the hardware power down mode.

If the hardware power down mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete hardware power down sequence; however, the watchdog
works identically to the monitoring function.

C517A

XTAL1

XTAL2

RC

Oscillator

On-Chip

Oscillator

f

RC

3MHz

÷ 5

÷ 2

f

1

f

2

OWDS

Figure 24
Block Diagram of the Oscillator Watchdog

Frequency

Comparator

f

2<1

f

Delay

_

<

1

IP0 (A9 )

H

Internal Reset

Internal Clock

MCB03337

Semiconductor Group 48 1997-10-01

C517A

Power Saving Modes

The C517A provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate
in normal operating mode and it can be also used for further power reduction in idle mode.

– Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.

– Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,
to 1/8th of their normal operating frequency and also reduces power consumption.

– Software power down mode

The operation of the C517A is completely stopped and the oscillator is turned off. This mode
is used to save the contents of the internal RAM with a very low standby current. This power
down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/
INT0.

– Hardware Power down mode

If pin HWPD gets active (low level) the part enters the hardware power down mode and starts
a complete internal reset sequence. Thereafter, both oscillators of the chip are stopped and
the port pins and several control lines enter a floating state.

In the power down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that V

CC

is restored to its normal operating level, before the power down mode is terminated. Table 13 gives
a general overview of the entry and exit procedures of the power saving modes.

Semiconductor Group 49 1997-10-01

Table 13
Power Saving Modes Overview

C517A

Mode Entering

2-Instruction
Example

Idle mode ORL PCON, #01H

ORL PCON, #20H

Slow Down Mode In normal mode:

ORL PCON,#10H

With idle mode:
ORL PCON,#01H
ORL PCON, #30H

Software
Power Down Mode

Hardware
Power Down Mode

ORL PCON, #02H
ORL PCON, #40H

HWPD = 0 HWPD = 1 Oscillator is stopped; internal

Leaving by Remarks

Occurrence of an
interrupt from a
peripheral unit

Hardware Reset

ANL PCON,#0EFH
or
Hardware Reset

Occurrence of an
interrupt from a
peripheral unit

Hardware reset

Hardware Reset Oscillator is stopped;
Short low pulse at

pin P3.2/

INT0

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Internal clock rate is reduced
to 1/8 of its nominal frequency

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/8
of its nominal frequency

contents of on-chip RAM and
SFR’s are maintained;

reset is executed;

Semiconductor Group 50 1997-10-01

C517A

Absolute Maximum Ratings

Ambient temperature under bias (TA) ......................................................... – 40 to 125 °C

Storage temperature (T

Voltage on VCC pins with respect to ground (VSS) ....................................... – 0.5 V to 6.5 V

Voltage on any pin with respect to ground (VSS)......................................... – 0.5 V to VCC +0.5 V

Input current on any pin during overload condition..................................... – 10 mA to 10 mA

Absolute sum of all input currents during overload condition ..................... I 100 mA I

Power dissipation........................................................................................ TBD

Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (
Voltage on

V

absolute maximum ratings.

) .......................................................................... – 65 °C to 150 °C

stg

V

>

V

IN

pins with respect to ground (

CC

V

) must not exceed the values defined by the

SS

CC

or

V

<

V

SS

) the

IN

Semiconductor Group 51 1997-10-01

C517A

DC Characteristics

V

= 5 V + 10%, – 15%; VSS=0V TA= 0 to 70 °C for the SAB-C517A

CC

T

= – 40 to 85 °C for the SAF-C517A

A

T

= – 40 to 110 °C for the SAH-C517A

A

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltage
Pins except EA,RESET,HWPD
EA pin
HWPD and RESET pins

Input high voltage
pins except

RESET, XTAL2 and
HWPD
XTAL2 pin
RESET and HWPD pin

Output low voltage
Ports 1, 2, 3, 4, 5, 6
Port 0, ALE,

PSEN, RO

Output high voltage
Ports 1, 2, 3, 4, 5, 6

Port 0 in external bus mode,
ALE, PSEN, RO

Logic 0 input current
Ports 1, 2, 3, 4, 5, 6 I

Logical 0-to-1 transition current,
Ports 1, 2, 3, 4, 5, 6

Input leakage current
Port 0, 7 and 8,

EA, HWPD I

Input low current
to RESET for reset
XTAL2
PE/SWD, OWE

Pin capacitance

Overload current

V
V
V

V
V
V

V
V

V

V

I

I
I
I

C

I

LI

TL

LI

IL2
IL3
IL4

OV

IL
IL1
IL2

IH
IH1
IH2

OL
OL1

OH

OH1

IO

– 0.5
– 0.5
– 0.5

0.2 VCC + 0.9

0.7 V

CC

0.6 V

CC

–
–

2.4

0.9 V

CC

2.4

0.9 V

CC

– 10 – 70 µA V

– 65 – 650 µA V
– ± 1 µA 0.45 < V

– 10
–
–

–10pFf
– ± 5mA

0.2 VCC – 0.1

0.2 VCC – 0.3

0.2 VCC + 0.1

V

+ 0.5

CC

V

+ 0.5

CC

V

+ 0.5

CC

0.45

0.45

–
–
–
–

– 100
– 15
– 20

V
V
V

V
V
V

V
V

V
V
V
V

µA
µA
µA

–
–
–

–
–
–

I

= 1.6 mA

OL

I

= 3.2 mA

OL

I

= – 80 µA

OH

I

= – 10 µA

OH

I

= – 800 µA

OH

I

= – 80 µA

OH

= 0.45 V

I N

=2 V

I N

I N

V

= 0.45 V

IN

V

= 0.45 V

I N

V

= 0.45 V

I N

= 1 MHz,

C

T

=25°C

A

7) 8)

< V

1)

1)

2)

CC

Notes see next page

Semiconductor Group 52 1997-10-01

C517A

Power Supply Current
Parameter Symbol Limit Values Unit Test Condition

9)

typ.

Active mode 18 MHz

24 MHz

Idle mode 18 MHz

24 MHz

Active mode with
slow-down enabled

18 MHz
24 MHz

Power-down mode I

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

PD

21.3

27.3

11.6

14.6

9.5

10.7
15 50 µA VCC=2…5.5 V

Notes:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.

max.

29.2

37.6

16.2

20.4

13.1

14.9

10)

mA
mA

mA
mA

mA
mA

4)

5)

6)

V

of ALE

OL

3)

V

2) Capacitive loading on ports 0 and 2 may cause the

V

0.9

specification when the address lines are stabilizing.

CC

on ALE and PSEN to momentarily fall below the

OH

3) IPD (power-down mode) is measured under following conditions:

RESET = Port 0 = Port 7 = Port 8 = VCC; XTAL1 = N.C.; XTAL2 = VSS; PE/SWD = OWE = VSS;

EA =
HWPD = VCCfor software power-down mode; V

I

(hardware power-down mode) is independent of any particular pin connection.

PD

AGND

= VSS; V

= VCC; all other pins are disconnected.

AREF

4) ICC (active mode) is measured with:

t

, t

XTAL2 driven with

PE/SWD == VSS; Port 0 = Port 7 = Port 8 = VCC; HWPD = VCC; RESET = VCC; all other pins are

EA =

CLCH

= 5 ns , VIL= VSS+ 0.5 V, VIH= VCC– 0.5 V; XTAL1 = N.C.;

CHCL

disconnected.

I

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

5)

CC

XTAL2 driven with

t

CLCH

, t

= 5 ns, VIL= VSS+ 0.5 V, VIH= VCC– 0.5 V; XTAL1 = N.C.;

CHCL

RESET = VCC; HWPD = Port 0 = Port 7 = Port 8 = VCC;EA=PE/SWD = VSS;
all other pins are disconnected;

I

(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

6)

CC

disabled; XTAL2 driven with

t

CLCH

, t

= 5 ns , VIL= VSS+ 0.5 V, VIH= VCC– 0.5 V; XTAL1 = N.C.;

CHCL

HWPD = VCC;RESET = VCC; Port 7 = Port 8 = VCC;; EA = PE/SWD == VSS; all other pins are disconnected.

7) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

V

exceeds the specified range (i.e.

> VCC+ 0.5 V or VOV< VSS- 0.5 V). The supply voltage VCC and VSS must

OV

remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

8) Not 100% tested, guaranteed by design characterization

I

9) The typical

values are periodically measured at TA= +25 °C and VCC= 5 V but not 100% tested.

CC

10)The maximum ICC values are measured under worst case conditions (TA= 0 °C or -40 °C and VCC= 5.5 V)

Semiconductor Group 53 1997-10-01

C517A

40

Ι

CC max

mA

Ι

CC

30

Ι

CC typ

Active Mode

MCD03338

Active Mode

20

Idle Mode

10

Idle Mode

Active + Slow Down Mode

0

0

3.5 8 12 16 20 24MHz

f

OSC

Figure 25
ICC Diagram

Table 14
Power Supply Current Calculation Formulas

Parameter Symbol Formula

Active mode

Idle mode

Active mode with
slow-down enabled

Note: f

is the oscillator frequency in MHz. ICC values are given in mA.

osc

I

CC typ

I

CC max

I

CC typ

I

CC max

I

CC typ

I

CC max

1

*

1.4

0.5

0.7

0.25

0.3

f

*
*

*

*

OSC

f
f

f

*

f

+ 3.3

OSC

OSC
OSC

f

OSC

OSC

+ 4.0
+ 2.6

+ 3.6

+ 4.95

+ 7.7

Semiconductor Group 54 1997-10-01

A/D Converter Characteristics

V

= 5 V + 10%, – 15%; VSS=0V TA= 0 to 70 °C for the SAB-C517A

CC

T

= – 40 to 85 °C for the SAF-C517A

A

T

= – 40 to 110 °C for the SAH-C517A

A

C517A

4 V ≤ V

≤ VCC+0.1 V; VSS-0.1 V ≤ V

AREF

≤ VSS+0.2 V

AGND

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage

V

Sample time t

Conversion cycle time t

Total unadjusted error T
Internal resistance of

R

reference voltage source
Internal resistance of

R

analog source
ADC input capacitance C

Notes see next page.

AIN

S

ADCC

UE

AREF

ASRC

AIN

V

AGND

– 16 x t

– 96 x t

V

AREF

8 x t

48 x t

V
ns Prescaler ÷ 8

IN

IN

ns Prescaler ÷ 8

IN
IN

– ± 2 LSB VSS+0.5V ≤ VIN≤ VCC-0.5V
– t

ADC

/ 250

kΩ

- 0.25

– tS / 500

kΩ

- 0.25

–50pF

1)

Prescaler ÷ 4

Prescaler ÷ 4

t

ADC

t

in [ns]

S

6)

in [ns]

5) 6)

2) 6)

Clock calculation table:

2)

3)

4)

Clock Prescaler

ADCL t

ADC

Ratio

÷ 8 1 8 x t
÷ 4 0 4 x t

Further timing conditions: t

min = 500 ns

ADC

tIN = 2 / f

IN
IN

OSC

t

16 x t
8 x t

= 2 t

S

CLCL

IN

IN

t

ADCC

96 x t
48 x t

IN
IN

Semiconductor Group 55 1997-10-01

Notes:

1) V

2) During the sample time the input capacitance C

may exceed V

AIN

AGND

these cases will be X000

or V

or X3FFH, respectively.

H

up to the absolute maximum ratings. However, the conversion result in

AREF

can be charged/discharged by the external source. The

AIN

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t
After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion

S

result.

C517A

S

.

3) This parameter includes the sample time t

calibration. Values for the conversion clock t

, the time for determining the digital result and the time for the

S

depend on programming and can be taken from the table on

ADC

the previous page.

4) T

is tested at V

UE

AREF

= 5.0 V, V

= 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all

AGND

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Semiconductor Group 56 1997-10-01

C517A

AC Characteristics (18 MHz)

V

= 5 V + 10%, – 15%; VSS=0V TA= 0 to 70 °C for the SAB-C517A

CC

T

= – 40 to 85 °C for the SAF-C517A

A

T

= – 40 to 110 °C for the SAH-C517A

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

18 MHz

Clock

1/

Variable Clock

t

= 3.5 MHz to 18 MHz

CLCL

min. max. min. max.

ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN

*)

Interfacing the C517A to devices with float times up to 45 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

*)

71 – 2 t
26 – t
26 – t
– 122 – 4 t
31 – t
132 – 3 t
–92– 3t

– 40 – ns

CLCL

– 30 – ns

CLCL

– 30 – ns

CLCL

– 100 ns

CLCL

– 25 – ns

CLCL

– 35 – ns

CLCL

– 75 ns

CLCL

0–0–ns
–46– t

*)

48 – t

– 8 – ns

CLCL

– 180 – 5 t

– 10 ns

CLCL

– 98 ns

CLCL

0–0–ns

Semiconductor Group 57 1997-10-01

C517A

AC Characteristics (18 MHz, cont’d)
External Data Memory Characteristics

Parameter Symbol Limit Values Unit

RD pulse width t
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

18 MHz

Clock

1/

Variable Clock

t

= 3.5 MHz to 18 MHz

CLCL

min. max. min. max.

233 – 6 t
233 – 6 t
81 – 2 t
– 128 – 5 t

– 100 – ns

CLCL

– 100 – ns

CLCL

– 30 – ns

CLCL

– 150 ns

CLCL

0–0–ns
–51– 2t
– 294 – 8 t
– 335 – 9 t
117 217 3 t
92 – 4 t
16 96 t
11 – t
239 – 7 t
16 – t

– 50 3 t

CLCL

– 130 – ns

CLCL

– 40 t

CLCL

– 45 – ns

CLCL

– 150 – ns

CLCL

– 40 – ns

CLCL

– 60 ns

CLCL

– 150 ns

CLCL

– 165 ns

CLCL

+ 50 ns

CLCL

+ 40 ns

CLCL

–0–0ns

External Clock Drive Characteristics
Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 18 MHz

min. max.

Oscillator period
High time
Low time
Rise time
Fall time

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

55.6 285.7 ns
15 t
15 t

CLCL

CLCL

– t
– t

CLCX

CHCX

ns

ns
–15ns
–15ns

Semiconductor Group 58 1997-10-01

C517A

AC Characteristics (24 MHz)

V

= 5 V + 10%, – 15%; VSS=0V TA= 0 to 70 °C for the SAB-C517A

CC

T

= – 40 to 85 °C for the SAF-C517A

A

T

= – 40 to 110 °C for the SAH-C517A

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

24 MHz

Clock

1/

Variable Clock

t

= 3.5 MHz to 24 MHz

CLCL

min. max. min. max.

ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN

*)

Interfacing the C517A to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

*)

43 – 2 t
17 – t
17 – t
–80– 4t
22 – t
95 – 3t
–60– 3t

– 40 – ns

CLCL

– 25 – ns

CLCL

– 25 – ns

CLCL

– 87 ns

CLCL

– 20 – ns

CLCL

– 30 – ns

CLCL

– 65 ns

CLCL

0–0–ns
–32– t

*)

37 – t

– 5 – ns

CLCL

– 148 – 5 t

– 10 ns

CLCL

– 60 ns

CLCL

0–0–ns

Semiconductor Group 59 1997-10-01

C517A

AC Characteristics (24 MHz, cont’d)
External Data Memory Characteristics

Parameter Symbol Limit Values Unit

RD pulse width t
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

24 MHz

Clock

1/

Variable Clock

t

= 3.5 MHz to 24 MHz

CLCL

min. max. min. max.

180 – 6 t
180 – 6 t
53 – 2 t
– 118 – 5 t

– 70 – ns

CLCL

– 70 – ns

CLCL

– 30 – ns

CLCL

– 90 ns

CLCL

0–0–ns
–63– 2t
– 200 – 8 t
– 220 – 9 t
75 175 3 t
67 – 4 t
17 67 t
5–t
170 – 7 t
15 – t

– 50 3 t

CLCL

– 97 – ns

CLCL

– 25 t

CLCL

– 37 – ns

CLCL

– 122 – ns

CLCL

– 27 – ns

CLCL

– 20 ns

CLCL

– 133 ns

CLCL

– 155 ns

CLCL

+ 50 ns

CLCL

+ 25 ns

CLCL

–0–0ns

External Clock Drive Characteristics
Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 24 MHz

min. max.

Oscillator period
High time
Low time
Rise time
Fall time

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

41.7 285.7 ns
12 t
12 t

CLCL

CLCL

– t
– t

CLCX

CHCX

ns

ns
–12ns
–12ns

Semiconductor Group 60 1997-10-01

ALE

t

LHLL

C517A

PSEN

Port 0

Port 2

t

AVLL PLPH

t

LLIV

t

t

PLIV

t

AZPL

t

LLAX

t

LLPL

t

t

PXAV

t

PXIZ

PXIX

A0 - A7 Instr.IN A0 - A7

t

AVIV

A8 - A15 A8 - A15

MCT00096

Figure 26
Program Memory Read Cycle

Semiconductor Group 61 1997-10-01

ALE

PSEN

RD

t

LLWL

t

LLDV

t

RLDV

t

RLRH

t

WHLH

C517A

t

AVLL

Port 0

A0 - A7 from

Ri or DPL from PCL

Port 2

Figure 27
Data Memory Read Cycle

t

AVWL

t

LLAX2

t

AVDV

t

RLAZ

Data IN

t

RHDZ

t

RHDX

A0 - A7 Instr.

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

IN

MCT00097

Semiconductor Group 62 1997-10-01

ALE

PSEN

t

WHLH

C517A

WR

t

AVLL

Port 0

A0 - A7 from

Ri or DPL from PCL

t

AVWL

Port 2

Figure 28
Data Memory Write Cycle

t

t

LLAX2

LLWL

t

QVWX

t

WLWH

t

QVWH

Data OUT

t

WHQX

A0 - A7

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

Instr.IN

MCT00098

t

CLCL

V

- 0.5V

CC

0.45V

0.2

0.7

V

CC

V

CC

- 0.1

t

CHCL

t

CLCX

t

CLCH

t

CHCX

MCT00033

Figure 29
External Clock Drive on XTAL2

Semiconductor Group 63 1997-10-01

C517A

ROM Verification Characteristics for the C517A-1RM
ROM Verification Mode 1

Parameter Symbol Limit Values Unit

min. max.

Address to valid data

P1.0-P1.7
P2.0-P2.6

Port 0

Data:
Addresses:

Figure 30
ROM Verification Mode 1

t

AVQV

Address New Address

Data Out

P0.0-P0.7
P1.0-P1.7
P2.0-P2.6

=

D0-D7

=

A0-A7

=

A8-A14

–10t

t

AVQV

CLCL

ns

New Data Out

PSENInputs:
ALE, EA
RESET =

=

V

SS

=

V

IH

V

IL2

MCS03253

Semiconductor Group 64 1997-10-01

C517A

ROM Verification Mode 2
Parameter Symbol Limit Values Unit

min. typ max.

ALE pulse width
ALE period
Data valid after ALE
Data stable after ALE
P3.5 setup to ALE low
Oscillator frequency

ALE

Port 0

t

AWD

t

AS

t

DVA

t

AWD

t

ACY

t

DVA

t

DSA

t

AS

1/

t

CLCL

t

DSA

–2t
–12t

CLCL

CLCL

––4t
8 t

CLCL

– t

––ns

CLCL

–ns
–ns

CLCL

–ns

3.5 – 24 MHz

t

ACY

Data Valid

ns

P3.5

Figure 31
ROM Verification Mode 2

MCT02613

Semiconductor Group 65 1997-10-01

V

-0.5 V

CC

V

+0.90.2

CC

Test Points

V

0.2 -0.1

CC

0.45 V

MCT00039

AC Inputs during testing are driven at VCC- 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at V

for a logic ’1’ and V

IHmin

for a logic ’0’.

ILmax

Figure 32
AC Testing: Input, Output Waveforms

C517A

-0.1 V

V

OH

V

+0.1 V

OL

MCT00038

V

Load

V

V

Load

Load

+0.1 V

Timing Reference

Points

-0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.

I

OL/IOH

≥±20 mA

Figure 33
AC Testing: Float Waveforms

Crystal Oscillator Mode

C

XTAL1

Driving from External Source

N.C.

XTAL1

3.5-24 MHz

C

Crystal Mode :

C

(incl. stray capacitance)

= 20 pF

±

10 pF

XTAL2

External Oscillator
Signal

XTAL2

MCS03339

Figure 34
Recommended Oscillator Circuits for Crystal Oscillator

Semiconductor Group 66 1997-10-01

Plastic Package, P-MQFP-100-2 (SMD)

(Plastic Metric Quad Flat Package)

C517A

Figure 35
P-MQFP-100-2 Package Outlines

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”

SMD = Surface Mounted Device

Semiconductor Group 67 1997-10-01

Dimensions in mm

GPM05623