Datasheet SAB-C515-1R24M, SAB-C515-1RM, SAB-C515-L24M, SAB-C515-LM, SAF-C515-1R24M Datasheet (Siemens)

Microcomputer Components

8-Bit CMOS Microcontroller

C515

Data Sheet 08.97

C515 Data Sheet
Revision History: Current Version: 1997-08-01

Previous Version: none (Original Version)
Page

(in previous
Version)

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(in current
Version)

Subjects (major changes since last revision)

Edition 1997-08-01
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

©

Siemens AG 1997.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

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For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in­curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

8-Bit CMOS Microcontroller

Advance Information

Data Sheet

Full upward compatibility with SAB 80C515

•

Up to 24 MHz external operating frequency

•

– 500ns instruction cycle at 24 MHz operation
8K byte on-chip ROM (with optional ROM protection)

•

– alternatively up to 64K byte external program memory
Up to 64K byte external data memory

•

256 byte on-chip RAM

•

Six 8-bit parallel I/O ports

•

One input port for analog/digital input

•

Full duplex serial interface (USART)

•

– 4 operating modes, fixed or variable baud rates
Three 16-bit timer/counters

•

– Timer 0 / 1 (C501 compatible)
– Timer 2 for 16-bit reload, compare, or capture functions

C515

(more features on next page)

Power
Saving
Modes

8-Bit

A/D

Converter

On-Chip Emulation Support Module

Digital

Input

Watchdog

Port6Port 5 Port 4

I/O I/OAnalog/

Timer

T2

T0

T1

RAM

256 x 8

CPU

ROM

K8x8

USART

Port 0

Port 1

Port 2

Port 3

I/O

I/O

I/O

I/O

MCA03198

Figure 1
C515 Functional Units

Semiconductor Group 3 1997-08-01

Features (cont’d):

•

8-bit A/D converter
– 8 multiplexed analog inputs
– Programmable reference voltages

•

16-bit watchdog timer

•

Power saving modes
– Idle mode
– Slow down mode (can be combined with idle mode)
– Software power-down mode

•

12 interrupt sources (7 external, 5 internal) selectable at four priority levels

•

On-chip emulation support logic (Enhanced Hooks Technology

•

ALE switch-off capability

•

P-MQFP-80-1 package

•

Temperature Ranges : SAB-C515

SAF-C515
SAH-C515

T

= 0 to 70 ° C

A

T

= -40 to 85 ° C

A

T

= -40 to 110 ° C (max. operating frequency: 16 MHz)

A

TM

)

C515

The C515 is an upward compatible version of the SAB 80C515A 8-bit microcontroller which
additionally provides ALE switch-off capability, on-chip emulation support, ROM protection, and
slow down mode capability. With a maximum external clock rate of 24 MHz it achieves a 500 ns
instruction cycle time (1

Ordering Information
Type Ordering Code Package Description

SAB-C515-1RM
SAB-C515-1R24M

SAF-C515-1RM Q67127-DXXXX P-MQFP-80-1 with mask programmable ROM (16 MHz)

SAF-C515-1R24M Q67127-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz)

SAB-C515-LM
SAB-C515-L24M

SAF-C515-LM Q67127-C1031 P-MQFP-80-1 for external memory (16 MHz)

µ

s at 12 MHz). The C515 is mounted in a P-MQFP-80 package.

(8-Bit CMOS microcontroller)

Q67127-DXXXX
Q67127-DXXXX

Q67127-C1030
Q67127-C1032

P-MQFP-80-1
P-MQFP-80-1

P-MQFP-80-1
P-MQFP-80-1

with mask programmable ROM (16 MHz)
with mask programmable ROM (24 MHz)

ext. temp. – 40 ˚C to 85 ˚C

ext. temp. – 40 ˚C to 85 ˚C
for external memory (16 MHz)

for external memory (24 MHz

ext. temp. – 40 ˚C to 85 ˚C

SAF-C515-L24M Q67127-C1081 P-MQFP-80-1 for external memory (24 MHz)

ext. temp. – 40 ˚C to 85 ˚C

Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C515C-LM and SAH-

C515-1RM) are available on request. The ordering number of ROM types (DXXXX
extensions) is defined after program release (verification) of the customer.

Semiconductor Group 4 1997-08-01

C515

XTAL1
XTAL2

ALE
PSEN
EA

RESET
PE

V

AREF

V

AGND

V

C515

V

SSCC

Port 0
8 Bit Digital I/O

1Port

8 Bit Digital I/O
Port 2

8 Bit Digital I/O
Port 3

8 Bit Digital I/O

4Port

8 Bit Digital I/O
Port 5

8 Bit Digital I/O

6Port
8 Bit Analog/
Digital Input

MCL03199

Figure 2
Logic Symbol

Additional Literature

For further information about the C515 the following literature is available:

Title Ordering Number

C515 8-Bit CMOS Microcontroller User’s Manual B158-H7049-X-X-7600
C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

Semiconductor Group 5 1997-08-01

P0.7/AD7

P0.6/AD6

P5.7

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0EAALE

N.C.

N.C.

PSEN

N.C.

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

4142434445464748495051525354555657585960

C515

P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
N.C.

V

CC

N.C.
N.C.
P4.0

P4.1

P4.2

PE
P4.3
P4.4
P4.5
P4.6
P4.7

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

12

345

4061
39
38
37
36
35
34
33
32

C515

31
30
29
28
27
26
25
24
23
22
21

6

7

8

9

10

11

12

13 14 15

16

17

18

19

20

P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
N.C.

V

SS

V

CC

N.C.
P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2
P1.5/T2EX
P1.6/CLKOUT
P1.7/T2
N.C.
P3.7/RD
P3.6/WR

AREF

N.C.

V

RESET

AGND

V

P6.7/AIN7

P6.5/AIN5

P6.6/AIN6

P6.3/AIN3

P6.4/AIN4

P6.2/AIN2

N.C.

N.C.

P6.0/AIN0

P6.1/AIN1

P3.1/TXD

P3.0/RXD

Figure 3
C515 Pin Configuration (P-MQFP-80 Package, Top View)

P3.4/T0

P3.2/INT0

P3.5/T1

P3.3/INT1

MCP03200

Semiconductor Group 6 1997-08-01

Table 1
Pin Definitions and Functions

C515

Symbol Pin Number

(P-MQFP-80)

RESET

1I

VAREF 3 –
VAGND 4 –
P6.0-P6.7 12-5 I

*) I = Input

O = Output

I/O*) Function

RESET

A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C515. A
small internal pullup resistor permits power-on reset
using only a capacitor connected to V

Reference voltage for the A/D converter
Reference ground for the A/D converter
Port 6

is an 8-bit unidirectional input port to the A/D converter.
Port pins can be used for digital input, if voltage levels
simultaneously meet the specifications for high/low input
voltages and for the eight multiplexed analog inputs.

SS

.

Semiconductor Group 7 1997-08-01

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

(P-MQFP-80)

P3.0-P3.7 15-22

15

16

17

18

19
20
21

22

I/O*) Function

I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current ( I
characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that
function to operate. The secondary functions are
assigned to the pins of port 3 as follows:
P3.0 / RxD Receiver data input (asynch.) or data

P3.1 / TxD Transmitter data output (asynch.) or

P3.2 / INT0

P3.3 / INT1 External interrupt 1 input /

P3.4 / T0 Timer 0 counter input
P3.5 / T1 Timer 1 counter input
P3.6 / WR

P3.7 / RD RD control output; enables the

, in the DC

IL

input/output (synch.) of serial interface

clock output (synch.) of serial interface
External interrupt 0 input /
timer 0 gate control input

timer 1 gate control input

WR control output; latches the data byte
from port 0 into the external data
memory

external data memory

*) I = Input

O = Output

Semiconductor Group 8 1997-08-01

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

(P-MQFP-80)

P1.0 - P1.7 31-24

31

30

29

28

27
26

25
24

I/O*) Function

I/O Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current ( I
characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the
compare functions). The secondary functions are
assigned to the port 1 pins as follows :
P1.0 / INT3 /

P1.1 / INT4 /CC1 Interrupt 4 input /

P1.2 / INT5 /CC2 Interrupt 5 input /

P1.3 / INT6 /CC3 Interrupt 6 input /

P1.4 / INT2
P1.5 / T2EX Timer 2 external reload /

P1.6 / CLKOUT System clock output
P1.7 / T2 Counter 2 input

CC0 Interrupt 3 input /

compare 0 output /
capture 0 input

compare 1 output /
capture 1 input

compare 2 output /
capture 2 input

compare 3 output /
capture 3 input
Interrupt 2 input

trigger input

, in the DC

IL

V

SS

V

CC

34 –
33, 69 –

Ground (0 V)
Supply voltage

during normal, idle, and power-down operation.

*) I = Input

O = Output

Semiconductor Group 9 1997-08-01

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

(P-MQFP-80)

XTAL2 36 –

XTAL1 37 – XTAL1

P2.0-P2.7 38-45 I/O Port 2

I/O*) Function

XTAL2

Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source,
XTAL2 should be driven, while XTAL1 is left
unconnected.
times as well as rise/fall times specified in the AC
characteristics must be observed.

Output of the inverting oscillator amplifier.

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pullup resistors when issuing 1's. During
accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of
the P2 special function register.

Minimum and maximum high and low

, in the DC

IL

PSEN

ALE 48 O The Address Latch enable

*) I = Input

O = Output

Semiconductor Group 10 1997-08-01

47 O The Program Store Enable

output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator periods,
except during external data memory accesses. The
signal remains high during internal program execution.

output is used for latching the address into external
memory during normal operation. It is activated every six
oscillator periods, except during an external data
memory access.

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

I/O*) Function

(P-MQFP-80)

EA 49 I External Access Enable

When held high, the C515 executes instructions from
the internal ROM (C515-1R) as long as the program
counter is less than 2000H. When held low, the C515
fetches all instructions from ext. program memory. For
the C515-L this pin must be tied low.

P0.0-P0.7 52-59 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins
that have 1's written to them float, and in that state can
be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during
accesses to external program and data memory. In this
application it uses strong internal pullup resistors when
issuing 1's. Port 0 also outputs the code bytes during
program verification in the C515-1R. External pullup
resistors are required during program verification.

P5.ß-P5.7 67-60 I/O Port 5

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 5 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.

, in the DC

IL

P4.0-P4.7 72-74,

76-80

I/O Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull­up resistors. Port 4 pins that have 1’s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (I

, in the DC

IL

characteristics) because of the internal pull-up resistors.

PE

75 I Power saving mode enable

A low level on this pin allows the software to enter the
power saving modes (idle mode and power down
mode). When PE is held at high level it is impossible to
enter the power saving modes. When left unconnected
this pin is pulled high by a weak internal pull-up resistor.

*) I = Input

O = Output

Semiconductor Group 11 1997-08-01

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

(P-MQFP-80)

N.C. 2, 13, 14, 23,

32, 35, 46, 50,
51, 68, 70, 71

*) I = Input

O = Output

I/O*) Function

– Not connected

These pins of the P-MQFP-80 package must not be
connected.

Semiconductor Group 12 1997-08-01

XTAL1
XTAL2

ALE

C515

OSC & Timing

RAM ROM

256 x 8

8K x 8

C515

PSEN
EA
PE
RESET

V

AREF

V

AGND

CPU

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

USART

Baud Rate Generator

Interrupt Unit

Programmable

Reference Voltages

8-Bit

A/D Converter

Emulation

Support

Logic

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 0
8 Bit Digital I/O

Port 1
8 Bit Digital I/O

Port 2
8 Bit Digital I/O

Port 3
8 Bit Digital I/O

Port 4
8 Bit Digital I/O

Port 5
8 Bit Digital I/O

Port 6

S & H

Analog

MUX

Port 6

MCB03201

8 Bit Digital I/O

Digital Input

Figure 4
Block Diagram of the C515C

Semiconductor Group 13 1997-08-01

C515

CPU

The C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three­byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1.0µs (10 MHz: 600).

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

H

D7

CY AC

H

D6

H

D5

F0

H

D4

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1

RS0

Register Bank select control bits

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

H

D3

H

D2

H

D1

H

D0

H

PSW

H

H

H

H

OV Overflow Flag

Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Semiconductor Group 14 1997-08-01

Memory Organization

The C515 CPU manipulates data and operands in the following four address spaces:

– up to 64 Kbyte of internal/external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C515.

C515

External

Internal

"Code Space"

FFFF

2000

External
(EA = 0)1)=(EA

H

H

1FFF

0000

FFFF

H

External

Indirect

Address

FF

H

Internal

RAM

80

H

H

0000

H

"Data Space" "Internal Data Space"

H

Internal

RAM

Direct

Address

Special

Function

Register

7F

H

00

H

FF

H

80

H

MCD03202

Figure 5
C515 Memory Map

Semiconductor Group 15 1997-08-01

C515

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.

b)a)

&

+

Figure 6
Reset Circuitries

RESET

C515

RESET

C515

c)

+

RESET

C515

MCS03203

Semiconductor Group 16 1997-08-01

C515

Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation.

Crystal Oscillator Mode Driving from External Source

C

XTAL1

1-24 MHz

C

XTAL2 XTAL2

C

Crystal Mode :

= 20 pF±10 pF (incl. stray capacitance)

Figure 7
Recommended Oscillator Circuitries

N.C.

External Oscillator
Signal

XTAL1

MCS03204

Semiconductor Group 17 1997-08-01

C515

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

1)

The Enhanced Hooks Technology
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

TM

, which requires embedded logic in the C500 allows the C500

SYSCON

PCON
TCON

Optional
I/O Ports

ICE-System Interface

to Emulation Hardware

RESET

EA

ALE

PSEN

C500

0

MCU Interface Circuit

Port 3 Port 1

Port
Port

2

Target System Interface

RSYSCON

RPCON
RTCON

Enhanced Hooks

RPort 0RPort 2

EH-IC

TEA TALE TPSEN

MCS03280

Figure 8
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 18 1997-08-01

C515

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.

The 59 special function registers (SFRs) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0­2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.

The SFRs of the C515 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C515. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.

Semiconductor Group 19 1997-08-01

C515

Table 2
Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B
DPH
DPL
PSW
SP
SYSCON

A/D­Converter

ADCON
ADDAT
DAPR

Interrupt
System

IEN0
IEN1

2)

IP0

2)

2)

IP1
IRCON
TCON
T2CON

2)

Timer 0/
Timer 1

SCON
TCON

TH0
TH1
TL0
TL1
TMOD

Compare/
Capture
Unit /
Timer 2

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
System Control Register

2)

A/D Converter Control Register
A/D Converter Data Register
A/D Converter Program Register

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register

2)

Timer Control Register

2)

Timer 2 Control Register
Serial Channel Control Register

2)

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte

2)

Timer 2 Control Register

E0
F0

83
82

D0

81
B1

D8

D9
DA

A8
B8

A9
B9

C0
88
C8
98

88

8C
8D
8A
8B
89

C1
C3
C5
C7
C2
C4
C6
CB
CA
CD
CC

C8

H
H

H

H

H
H

H

H

H

H

H

H

H

H

H
H

H
H

H

H

H
H
H
H

H
H
H
H
H
H
H

H
H
H
H

H

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

4)

00

H

00

H

00

H

00

H

00

H

07

H

XX1X XXXX
00X0 0000

00

H

00

H

00

H

00

H

X000 0000
XX00 0000
00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

B

3)

B

3)

B

3)

B

3)

Semiconductor Group 20 1997-08-01

C515

Table 2
Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Ports P0

P1
P2
P3
P4
P5
P6

Serial
Channel

ADCON
PCON
SBUF
SCON

Watchdog IEN0

IEN1

2))

IP0

Power

PCON
Saving
Modes

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6, Analog/Digital Input

2)

A/D Converter Control Register

2)

Power Control Register
Serial Channel Buffer Register

2)

Serial Channel Control Register

2)

2)

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0

2)

Power Control Register 87

80
90
A0
B0
E8
F8

DB

D8

87
99

98
A8

B8

A9

H
H

H
H

H

H

H

H
H
H

H

H
H

H

1)

1)

1)
1

1)

1)

H

1

1)

1)

1)

FF

H

FF

H

FF

H

FF

H

FF

H

FF

H

–
00X0 0000

00

H

3)

XX

H

00

H

00

H

00

H

X000 0000
00

H

3)

B

3))

B

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

Semiconductor Group 21 1997-08-01

Table 3
Contents of the SFRs, SFRs in numeric order of their addresses

C515

Addr Register Content

after
Reset

2)

80
81
82
83
87
88
89

P0 FF

H

SP 07

H

DPL 00

H

DPH 00

H

PCON 00

H

2)

TCON 00

H

TMOD 00

H

8AHTL0 00
8BHTL1 00
8CHTH0 00
8DHTH1 00

2)

90

98
99
A0
A8

P1 FF

H

2)

SCON 00

H

SBUF XX

H

2)

P2 FF

H

2)

IEN0 00

H

1)

H
H
H
H
H
H
H
H
H
H
H

H

H

H

H
H

A9HIP0 X000-

0000

B

2)

B0

P3 FF

H

H

B1HSYSCON XX1X-

B8

2)

IEN1 00

H

XXXX

B

H

B9HIP1 XX00-

0000

B

2)

C0
C1HCCEN 00

IRCON 00

H

H
H

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
SMOD PDS IDLS SD GF1 GF0 PDE IDLE
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
GATE C/T

M1 M0 GATE C/T M1 M0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
T2 CLK-

T2EX INT2 INT6 INT5 INT4 INT3

OUT
SM0 SM1 SM2 REN TB8 RB8 TI RI
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
EAL WDT ET2 ES ET1 EX1 ET0 EX0
– WDTS .5 .4 .3 .2 .1 .0

RD WR T1 T0 INT1 INT0 TxD RxD
– – EALE –––––

EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC
– – .5.4.3.2.1.0

EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC
COCAH3COCAL3COCAH2COCAL2COCAH1COCAL1COCAH0COCAL

0

C2HCCL1 00

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

H

.7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 22 1997-08-01

Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C515

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H
H
H
H
H
H
H
H
H
H
H

H
H

1)

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
CY AC F0 RS1 RS0 OV F1 P
BD CLK – BSY ADM MX2 MX1 MX0

B

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0

Reset

C3HCCH1 00
C4HCCL2 00
C5HCCH2 00
C6HCCL3 00
C7HCCH3 00

2)

C8

T2CON 00

H

CAHCRCL 00
CBHCRCH 00
CCHTL2 00
CDHTH2 00

2)

D0
D8

PSW 00

H

2)

ADCON 00X0-

H

0000
D9HADDAT 00
DAHDAPR 00
DBHP6 – .7.6.5.4.3.2.1.0

2)

E0
E8
F0
F8

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

ACC 00

H

2)

P4 FF

H

2)

B 00

H

2)

P5 FF

H

H

H

H

H

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 23 1997-08-01

C515

Digital I/O Ports

The C515 allows for digital I/O on 48 lines grouped into 6 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P5 are performed via their corresponding special function registers P0 to P5.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time­multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.

Analog Input Ports

Ports 6 is available as input port only and provides two functions. When used as digital inputs, the
corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog
inputs the desired analog channel is selected by a three-bit field in SFR ADCON. Of course, it
makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have
no effect.

lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte
instructions.

Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care
must be taken that all bits of P6 that have an undetermined value caused by their analog function
are masked.

Semiconductor Group 24 1997-08-01

Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 :
Table 4

Timer/Counter 0 and 1 Operating Modes
Mode Description TMOD Input Clock

M1 M0 internal external (max)

C515

0 8-bit timer/counter with a

00

f

/12x32 f

OSC

OSC

/24x32

divide-by-32 prescaler
1 16-bit timer/counter 1 1
2 8-bit timer/counter with

10

8-bit autoreload
3 Timer/counter 0 used as one

11

/12 f

OSC

OSC

/24

f

8-bit timer/counter and one

8-bit timer

Timer 1 stops

In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is f

OSC

/12.

In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is f

/24. External inputs INT0 and INT1 (P3.2, P3.3) can be

OSC

programmed to function as a gate to facilitate pulse width measurements. Figure 9 illustrates the
input clock logic.

f

/12

OSC

Timer 0/1
Input Clock

P3.4/T0
P3.5/T1
max

P3.2/INT0
P3.3/INT1

f

OSC

/24

f

OSC

TR 0/1
TCON

Gate

TMOD

=1

÷

12

C/T

TMOD

0

1

Control

&

_

<

1

MCS01768

Figure 9
Timer/Counter 0 and 1 Input Clock Logic

Semiconductor Group 25 1997-08-01

C515

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C515 provides additional compare/capture/reload features. which allow the
selection of the following operating modes:

– Compare : up to 4 PWM signals with 16-bit/500 ns resolution
– Capture : up to 4 high speed capture inputs with 500 ns resolution
– Reload : modulation of timer 2 cycle time

The block diagram in figure 10 shows the general configuration of timer 2 with the additional
compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.

P1.5/
T2EX

P1.7/
T2

OSC

Sync.

T2I0

T2I1

Sync.

&

12

÷ 12

f

OSC

÷ 24

T2PS

24

Bit16 16 Bit 16 Bit 16 Bit

Comparator

Comparator

Comparator

EXEN2

Reload

EXF2

Reload

Timer 2

TH2TL2

Compare

Comparator

Capture

_

<

1

TF2

Input/

Output

Control

Interrupt
Request

P1.0/
INT3/
CC0

P1.1/
INT4/
CC1

P1.2/
INT5/
CC2

P1.2/
INT6/

CCL3/CCH3

CCL2/CCH2

CCL1/CCH1

CRCL/CRCH

CC3

MCB03205

Figure 10
Timer 2 Block Diagram

Semiconductor Group 26 1997-08-01

C515

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer
2 operation.

Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.

Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.

Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a 1­to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is
sampled every machine cycle. Since it takes two machine cycles (24 oscillator periods) to recognize
a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled
at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2: Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon­ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been
set.

Semiconductor Group 27 1997-08-01

C515

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows : the 16-bit value stored
in a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.

Compare Mode 0
In compare mode 0, upon matching the timer and compare register contents, the output signal

changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 11 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Compare Register

Circuit

Compare Reg.

16 Bit

Comparator

Bit16

Timer Register

Timer Circuit

Compare
Match

Timer
Overflow

Figure 11
Port Latch in Compare Mode 0

Port Circuit

Internal
Bus

Write to
Latch

S
D

Latch

CLK
R

Read Latch

Q

Port

Q

Read Pin

V

CC

Port

Pin

MCS02661

Semiconductor Group 28 1997-08-01

C515

Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the

new value will not appear at the output pin until the next compare match occurs. Thus, it can be
chosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.

In compare mode 1 (see figure 12) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Port Circuit

Compare Register

Circuit

Compare Reg.

16 Bit

Comparator

16 Bit

Timer Register

Timer Circuit

Compare
Match

Internal
Bus

Write to
Latch

Figure 12
Compare Function in Compare Mode 1

D

Shadow

Latch

CLK

Read Latch

Q

D

Port

Latch

Read Pin

V

CC

Q

QCLK

Port

Pin

MCS02662

Semiconductor Group 29 1997-08-01

C515

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 5. The possible baudrates can be calculated using the
formulas given in table 5.

Table 5
USART Operating Modes

Mode

SCON Description

SM0 SM1

0 0 0 Shift register mode

Serial data enters and exits through R×D/ T×D outputs the shift
clock; 8-bit are transmitted/received (LSB first); fixed baud rate

1 0 1 8-bit UART, variable baud rate

10 bits are transmitted (through T×D) or received (at R×D)

2 1 0 9-bit UART, fixed baud rate

11 bits are transmitted (through T×D) or received (at R×D)

3 1 1 9-bit UART, variable baud rate

Like mode 2

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in figure 13 to the serial interface which - there divided
by 16 - results in the actual "baud rate". Further, the abbrevation f

refers to the oscillator

OSC

frequency (crystal or external clock operation).
The variable baud rates for modes 1 and 3 of the serial interface can be derived from either timer 1

or from the system clock (see figure 13).

Semiconductor Group 30 1997-08-01

Timer

1

Overflow

/2

f

OSC

÷ 39

÷ 6

ADCON.7

(BD)

0
1

Mode

2

Mode

0

Mode 1

SCON.7
SCON.6

(SM0/

3Mode

SM1)

Only one mode
can be selected

÷ 2

PCON.7

(SMOD)

0
1

C515

Baud
Rate
Clock

Note: The switch configuration shows the reset state.

MCB03206

Figure 13
Block Diagram of Baud Rate Generation for the Serial Interface

Table 6 below lists the values/formulas for the baud rate calculation of the serial interface with its
dependencies of the control bits BD and SMOD.

Table 6
Serial Interface - Baud Rate Dependencies

Serial Interface 0
Operating Modes

Mode 0 (Shift Register) – – f
Mode 1 (8-bit UART)

Mode 3 (9-bit UART)

Active Control Bits Baud Rate Calculation

BD SMOD

/ 12

OSC

0 X Controlled by timer 1 overflow :

SMOD

(2

× timer 1 overflow rate) / 32

1 X Controlled by system clock divider circuits :

SMOD

Mode 2 (9-bit UART) – 0

(2

f

1

f

OSC
OSC

× f

/ 64
/ 32

) / 2496

OSC

Semiconductor Group 31 1997-08-01

C515

8-Bit A/D Converter

The C515 provides an A/D converter with the following features:

– Eight multiplexed input channels
– The possibility of using the analog inputs (port 6) also as digital inputs
– Programmable internal reference voltages (16 steps each) via resistor array
– 8-bit resolution within the selected reference voltage range
– Internal start-of-conversion trigger
– Interrupt request generation after each conversion

For the A/D conversion, the method of successive approximation via capacitor array is used. The
externally applied reference voltage range has to be held on a fixed value within the specifications
(see section "A/D Converter Characteristics" in this data sheet). The internal reference voltages can
be varied to reduce the reference voltage range of the A/D converter and thus to achieve a higher
resolution. Figure 14 shows a block diagram of the A/D converter.

Semiconductor Group 32 1997-08-01

IEN1 (B8 )

H

C515

Internal

Bus

Port 6

f

/2

OSC

EXEN2 SWDT

IRCON (C0 )

EXF2 TF2

ADCON (D8 )

BD CLK

MUX S & H

÷ 4

EX6

EX5

H

IEX6

IEX5

H

_

BSY

Conversion Clock

f

ADC

IEX4

ADM

IEX3

Single/
Continuous
Mode

Converter

0

MX1

A/D

EADCEX3EX4 ECAN

IADC

MX0MX2

ADDAT
(D9 )

H

LBS

.1
.2
.3
.4
.5
.6

MSB

Write to
DAPR

V

AREF

V

AGND

DAPR (DA )

.7 .6 .3.4.5

Shaded bit locations are not used in ADC-functions.

Figure 14
A/D Converter Block Diagram

Input Clock

f

IN

Internal Reference Voltages

H

Programming of

V

INTAREF

Start of
Conversion

V

INTAREF INTAGND

V

.2 .1 .0

Programming of

V

INTAGND

Internal

Bus

MCB03207

Semiconductor Group 33 1997-08-01

C515

Interrupt System

The C515 provides 12 interrupt sources with four priority levels. Five interrupts can be generated by
the on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seven
interrupts may be triggered externally (P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4,
P1.2/INT5, P1.3/INT6).

This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special
function registers. Figure 15 and 16 give a general overview of the interrupt sources and illustrate
the request and the control flags which are described in the next sections.

Semiconductor Group 34 1997-08-01

P3.2/
INT0

IT0

TCON.0

IE0

TCON.1

EX0

IEN0.0

0003

C515

Highest

Priority Level

H

Lowest

Priority Level

A/D Converter

Timer 0
Overflow

P1.4/
INT2

I2FR

T2CON.5

P3.3/
INT1

IT1

TCON.2

IADC

IRCON.0

TF0

TCON.5

IEX2

IRCON.1

IE1

TCON.3

EADC

IEN1.0

ET0

IEN0.1

EX2

IEN1.1

EX1

IEN0.2

0043

000B

004B

0013

H

IP1.0

H

H

H

IP0.0

Polling Sequence

IP0.1IP1.1

P1.0/
INT3

CC0

I3FR

T2CON.6

Bit addressable
Request Flag is

cleared by hardware

IEX3

IRCON.2

EX3

IEN1.2

0053

H

EAL

IEN0.7

IP1.2

IP0.2

MCS03208

Figure 15
Interrupt Request Sources (Part 1)

Semiconductor Group 35 1997-08-01

Timer 1
Overflow

P1.1/
INT4

CC1

TF1

TCON.7

IEX4

IRCON.3

ET1

IEN0.3

EX4

IEN1.3

001B

005B

C515

Highest

Priority Level

H

Lowest

Priority Level

H

USART

P1.2/
INT5

CC2

2

Timer
Overflow

P1.5/
T2EX

P1.3/
INT6

CC3

RI

SCON.0

SCON.1

EXEN2
IEN1.7

TI

TF2

IRCON.6

EXF2

IRCON.7

_

<

1

IEX5

IRCON.4

_

<

1

IEX6

IRCON.5

ES

IEN0.4

EX5

IEN1.4

ET2

IEN0.5

EX6

IEN1.5

0023

0063

002B

006B

IP1.3

IP0.3

H

H

Polling Sequence

IP0.4IP1.4

H

H

Bit addressable

EAL

IEN0.7

IP1.5 IP0.5

MCS03209

Request Flag is
cleared by hardware

Figure 16
Interrupt Request Sources (Part 2)

Semiconductor Group 36 1997-08-01

Table 7
Interrupt Source and Vectors

Interrupt Source Interrupt Vector Address Interrupt Request Flags

C515

External Interrupt 0 0003
Timer 0 Overflow 000B
External Interrupt 1 0013
Timer 1 Overflow 001B
Serial Channel 0023
Timer 2 Overflow / Ext. Reload 002B
A/D Converter 0043
External Interrupt 2 004B
External Interrupt 3 0053
External Interrupt 4 005B
External Interrupt 5 0063
External Interrupt 6 006B

H

H

H
H
H
H
H
H
H
H

H

H

IE0
TF0
IE1
TF1
RI / TI
TF2 / EXF2
IADC
IEX2
IEX3
IEX4
IEX5
IEX6

Semiconductor Group 37 1997-08-01

C515

Fail Save Mechanisms

As a means of graceful recovery from software or hardware upset a watchdog timer is provided in
the C515. lf the software fails to clear the watchdog timer at least every 65532 µs (at 12 MHz clock
rate), an internal hardware reset will be initiated. The software can be designed such that the
watchdog times out if the program does not progress properly. The watchdog will also time out if the
software error was due to hardware-related problems. This prevents the controller from
malfunctioning for longer than 65 ms if a 12-MHz oscillator is used. Figure 17 shows the block
diagram of the watchdog timer unit.

f

OSC

÷ 12

16-Bit Watchdog Timer

Reset

WDT Reset if WDT count is between

-------WDTS

External HW Reset

Control Logic

-

WDT

SWDT -

-

-

-

-

-

-

-

FFFC

FFFF-

HH

IP0 ( A9H)

-

--

IEN0

-

-

IEN1

A8()

H

)(B8

H

MCB03210

Figure 17
Block Diagram of the Watchdog Timer

The watchdog timer can be started by software (bit SWDT) but it cannot be stopped during active
mode of the C515. lf the software fails to clear the watchdog in time, an internally generated
watchdog reset is entered at the counter state FFFCH and lasts four instruction cycles. This internal
reset differs from an external reset only to the extent that the watchdog timer is not disabled. Bit
WDTS (was set by starting WDT) allows the software to examine from which source the reset was
initiated. lf it is set, the reset was caused by a watchdog timer overflow.

Semiconductor Group 38 1997-08-01

C515

Power Saving Modes

The C515 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock
rate in normal operating mode and it can be also used for further power reduction in idle mode.

– Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.

– Power down mode

The operation of the C515 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/INT0.

– Slow-down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,
to 1/8 th of their normal operating frequency. Slowing down the frequency significantly
reduces power consumption.

Table 8 gives a general overview of the entry and exit procedures of the power saving modes.
Table 8

Power Saving Modes Overview
Mode Entering

Leaving by Remarks
2-Instruction
Example

Idle mode ORL PCON, #01H

ORL PCON, #20H

Occurrence of an

interrupt from a

peripheral unit

Hardware Reset

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Power Down Mode ORL PCON, #02H

ORL PCON, #40H

Hardware Reset Oscillator is stopped;

contents of on-chip RAM and
SFR’s are maintained;

Slow Down Mode In normal mode :

ORL PCON,#10H

ANL PCON,#0EFH

or

Internal clock rate is reduced
to 1/8 of its nominal frequency

Hardware Reset
With idle mode :

ORL PCON,#01H
ORL PCON, #30H

Occurrence of an

interrupt from a

peripheral unit

Hardware reset

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/8
of its nominal frequency

In the power down mode of operation,
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that V

V

can be reduced to minimize power consumption. It must

CC

CC

is restored to its normal operating level, before the power down mode is terminated.

Semiconductor Group 39 1997-08-01

C515

Absolute Maximum Ratings

Ambient temperature under bias (TA) ......................................................... – 40 to 110 °C

Storage temperature (T

Voltage on VCC pins with respect to ground (VSS) ....................................... – 0.5 V to 6.5 V

Voltage on any pin with respect to ground (VSS)......................................... – 0.5 V to VCC +0.5 V

Input current on any pin during overload condition..................................... – 10 mA to 10 mA

Absolute sum of all input currents during overload condition ..................... I 100 mA I

Power dissipation........................................................................................ TBD

Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (
Voltage on

V

absolute maximum ratings.

) .......................................................................... – 65 °C to 150 °C

stg

V

>

V

IN

pins with respect to ground (

CC

V

) must not exceed the values defined by the

SS

CC

or

V

<

V

SS

) the

IN

Semiconductor Group 40 1997-08-01

C515

DC Characteristics

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515-1RM

CC

T

= – 40 to 85 °C for the SAF-C515-1RM

A

T

= – 40 to 110 °C for the SAH-C515-1RM

A

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltages
all except EA
EA pin

Input high voltages
all except XTAL2 and RESET
XTAL2 pin
RESET pin

Output low voltages
Ports 1, 2, 3, 4, 5
Port 0, ALE, PSEN

Output high voltages
Ports 1, 2, 3, 4, 5

Port 0 in external bus mode,
ALE, PSEN

Logic 0 input current
Ports 1, 2, 3, 4, 5 I

Logical 0-to-1 transition current
Ports 1, 2, 3, 4, 5

V

IL

V

IL1

V

IH

V

IH1

V

IH2

V

OL

V

OL1

V

OH

V

OH2

IL

I

TL

– 0.5
– 0.5

0.2 VCC + 0.9

0.7 V

CC

0.6 V

CC

–
–

2.4

0.9 V

CC

2.4

0.9 V

CC

0.2 VCC - 0.1

0.2 VCC - 0.3VV

V

+ 0.5

CC

V

+ 0.5

CC

V

+ 0.5

CC

0.45

0.45

–
–
–
–

–
–

V
V
V

V
V

V
V
V
V

–
–
–

I

= 1.6 mA

OL

I

= 3.2 mA

OL

I

= – 80 µA

OH

I

= – 10 µA

OH

I

= – 800 µA

OH

I

= – 80 µA

OH

– 10 – 70 µA VIN = 0.45 V
– 65 – 650 µA VIN = 2 V

1)

1)

2)

Input leakage current
Port 0, AIN0-7 (Port 6), EA

I

LI

– ± 1 µA 0.45 < VIN < V

CC

Input low current
to RESET for reset
XTAL2
PE

Pin capacitance

Overload current

Notes on next page

I
I
I

C

I

LI2
LI3
LI4

OV

–10
–
–

IO

–10pFf
– ± 5mA

– 100
– 15
– 20

µA
µA
µA

V

= 0.45 V

IN

V

= 0.45 V

IN

V

= 0.45 V

IN

= 1 MHz,

c

T

= 25 °C

A

7) 8)

Semiconductor Group 41 1997-08-01

C515

Power Supply Current
Parameter Symbol Limit Values Unit Test Condition

9)

typ.

Active mode 16 MHz

24 MHz

Idle mode 16 MHz

24 MHz

Active mode with
slow-down enabled

16 MHz
24 MHz

Power-down mode I

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

PD

13.7

19.6

6.9

9.1

4.9

6.5
10 30 µA VCC = 2…5.5 V

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and ports1, 3, 4, and 5. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins
when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF),
the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt­trigger, or use an address latch with a schmitt-trigger strobe input.

max.

18.2
25

9.6

12.8

7.0

8.8

10)

mA
mA

mA
mA

mA
mA

4)

5)

6)

3)

V

2) Capacitive loading on ports 0 and 2 may cause the

V

0.9

specification when the address lines are stabilizing.

CC

on ALE and PSEN to momentarily fall below the

OH

3) IPD (power-down mode) is measured under following conditions:

= Port 0 = Port 6 = VCC ; RESET = VCC; XTAL1 = N.C.; PE = XTAL2 = VSS ; V

EA

I

other pins are disconnected. The typical

current is measured at VCC = 5 V.

PD

AGND

= VSS ; V

= VCC ; all

AREF

4) ICC (active mode) is measured with:

t

, t

XTAL2 driven with

= Port 0 = Port 6 = VCC ; RESET = VSS ; all other pins are disconnected.

EA

CLCH

= 5 ns , VIL = VSS + 0.5 V, VIH =

CHCL

V

– 0.5 V; XTAL1 = N.C.;

CC

5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled;

t

, t

XTAL2 driven with

= Port 0 = Port 6 = VCC ; RESET = VCC ; all other pins are disconnected;

EA

CLCH

= 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL1 = N.C.;

CHCL

6) ICC (active mode with slow-down mode) is measured : TBD

7) ICC (active mode with slow-down mode) is measured : TBD

8) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin

V

exceeds the specified range (i.e.

> VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must

OV

remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

9) Not 100% tested, guaranteed by design characterization

I

10)The typical

values are periodically measured at T

CC

= +25 °C but not 100% tested.

A

Semiconductor Group 42 1997-08-01

C515

30

mA

Ι

CC

25

20

15

10

5

0

0

4 8 12 16 20 24

Active mode

Idle mode

Active mode with slow-down

Ι

CC max

Ι

CC typ

Ι

:

Ι

:

Ι

:

Ι

:

Ι
Ι

= 0.68 x + 2.8
= 0.85 x + 4.6:

CC max

= 0.28 x + 2.4

CC typ

= 0.39 x + 3.4

CC max

= 0.18 x + 2.0

CC typ

= 0.23 x + 3.3:

CC max

Active Mode

Active Mode

Idle Mode
Idle Mode

Active Mode with Slow Down

f

OSC

f

OSCCC typ

f

OSC

f

OSC

f

OSC

f

OSC

f

OSC

MHz

Figure 18
ICC Diagram

f

is the oscillator frequency in MHz. values are given in mA.

Ι

CCOSC

MCD03282

Semiconductor Group 43 1997-08-01

A/D Converter Characteristics

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515-1RM

CC

T

= – 40 to 85 °C for the SAF-C515-1RM

A

T

= – 40 to 110 °C for the SAH-C515-1RM

A

V

– 0.25 V ≤ V

CC

≤ VCC + 0.25 V ; VSS – 0.2 V ≤ V

AREF

≤ Vss + 0.2 V; V

AGND

IntAREF

− V

IntAGND

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage

V

AIN

V

AGND

0.2

-

V

AREF

+

V

0.2

1)

C515

≥ 1 V;

A/D converter input clock t
Sample time
Conversion cycle time t
Total unadjusted error T

Internal resistance of
reference voltage source

Internal resistance of

IN

t

S

ADCC

UE

R

R

AREF

ASRC

– 2 x t
– 16 x t
– 80 x t

CLCL

ns

IN

ns

IN

ns

– ± 1 LSB V

–8 x tIN /500

kΩ

- 1

– tS / 500 - 1 kΩ

2)

3)

IntAREF

V

IntAGND

t

in [ns]

IN

t

in [ns]

S

= V

= V

AREF

AGND

5) 6)

2) 6)

= V

= V

CC

SS

analog source
ADC input capacitance C

AIN

–45 pF

Notes:

1) V

2) During the sample time the input capacitance C

may exceed V

AIN

AGND

these cases will be 00

or V

or FFH, respectively.

H

up to the absolute maximum ratings. However, the conversion result in

AREF

can be charged/discharged by the external source. The

AIN

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t
After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion

S

result.

3) This parameter includes the sample time t

is always 8 x tIN.

t

ADC

4) TUE is tested at V

AREF

= 5.0 V, V

AGND

and the conversion time tC. The values for the conversion clock

S

= 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

6)

4)

.

S

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Semiconductor Group 44 1997-08-01

C515

AC Characteristics (16 MHz)

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515-1RM

CC

T

= – 40 to 85 °C for the SAF-C515-1RM

A

T

= – 40 to 110 °C for the SAH-C515-1RM

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

16 MHz

Clock

Variable Clock

1/

t

= 1 MHz to 16 MHz

CLCL

min. max. min. max.

ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
PSEN
PSEN

pulse width t

to valid instr in t
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN

*)

Interfacing the C515 to devices with float times up to 75 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

PLPH

PLIV

t

PXIX

PXIZ

t

PXAV

t

AVIV

t

AZPL

*)

85 – 2t
33 – t
28 – t
– 150 – 4t
38 – t
153 – 3t
–88– 3t

– 40 – ns

CLCL

– 30 – ns

CLCL

– 35 – ns

CLCL

– 100 ns

CLCL

– 25 – ns

CLCL

– 35 – ns

CLCL

– 100 ns

CLCL

0–0–ns
–43– t

*)

55 – t

– 8 – ns

CLCL

– 198 – 5t

– 20 ns

CLCL

– 115 ns

CLCL

0–0–ns

CLKOUT Characteristics
Parameter Symbol Limit Values Unit

16 MHz

Clock

Variable Clock

1/t

= 1 MHz to 16 MHz

CLCL

min. max. min. max.

ALE to CLKOUT
CLKOUT high time
CLKOUT low time
CLKOUT low to ALE high

t

LLSH

t

SHSL

t

SLSH

t

SLLH

398 – 7 t
85 – 2 t
585 – 10 t
23 103 t

CLCL

– 40 – ns

CLCL

– 40 – ns

CLCL

– 40 – ns

CLCL

– 40 t

+ 40 ns

CLCL

Semiconductor Group 45 1997-08-01

C515

AC Characteristics (16 MHz) (cont’d)
External Data Memory Characteristics

Parameter Symbol Limit Values Unit

pulse width t

RD
WR

pulse width t

Address hold after ALE

to valid data in t

RD
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR
Address valid to WR
WR

or RD high to ALE high t

Data valid to WR

or RD t

or RD t

transition t
Data setup before WR
Data hold after WR
Address float after RD

RLRH

WLWH

t

LLAX2

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

LLWL

AVWL

WHLH

QVWX

t

QVWH

t

WHQX

t

RLAZ

16 MHz

Clock

Variable Clock

1/

t

= 1 MHz to 16 MHz

CLCL

min. max. min. max.

275 – 6t
275 – 6t
90 – 2t
– 148 – 5t

– 100 – ns

CLCL

– 100 – ns

CLCL

– 35 – ns

CLCL

– 165 ns

CLCL

0–0–ns
–55– 2t
– 350 – 8t
– 398 – 9t
138 238 3t
120 – 4t
23 103 t
13 – t
288 – 7t
13 – t

– 50 3t

CLCL

– 130 – ns

CLCL

– 40 t

CLCL

– 50 – ns

CLCL

– 150 – ns

CLCL

– 50 – ns

CLCL

– 70 ns

CLCL

– 150 ns

CLCL

– 165 ns

CLCL

+ 50 ns

CLCL

+ 40 ns

CLCL

–0–0ns

External Clock Drive Characteristics
Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 1 MHz to 16 MHz

min. max.

Oscillator period
High time
Low time
Rise time
Fall time

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

62.5 1000 ns
15 t
15 t

CLCL

CLCL

– t
– t

CLCX

CHCX

ns

ns
–15ns
–15ns

Semiconductor Group 46 1997-08-01

C515

AC Characteristics (24 MHz)

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515-1RM

CC

T

= – 40 to 85 °C for the SAF-C515-1RM

A

T

= – 40 to 110 °C for the SAH-C515-1RM

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

24 MHz

Clock

Variable Clock

1/

t

= 1 MHz to 24 MHz

CLCL

min. max. min. max.

ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
PSEN
PSEN

pulse width t

to valid instr in t
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN

*)

Interfacing the C515 to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

PLPH

PLIV

t

PXIX

PXIZ

t

PXAV

t

AVIV

t

AZPL

*)

43 – 2t
17 – t
17 – t
–80– 4t
22 – t
95 – 3t
–60– 3t

– 40 – ns

CLCL

– 25 – ns

CLCL

– 25 – ns

CLCL

– 87 ns

CLCL

– 20 – ns

CLCL

– 30 – ns

CLCL

– 65 ns

CLCL

0–0–ns
–32– t

*)

37 – t

– 5 – ns

CLCL

– 148 – 5t

– 10 ns

CLCL

– 60 ns

CLCL

0–0–ns

CLKOUT Characteristics
Parameter Symbol Limit Values Unit

24 MHz

Clock

Variable Clock

1/t

= 1 MHz to 24 MHz

CLCL

min. max. min. max.

ALE to CLKOUT
CLKOUT high time
CLKOUT low time
CLKOUT low to ALE high

t

LLSH

t

SHSL

t

SLSH

t

SLLH

252 – 7 t
43 – 2 t
377 – 10 t
282t

– 40 – ns

CLCL

– 40 – ns

CLCL

CLCL

– 40 t

CLCL

– 40 – ns

+ 40 ns

CLCL

Semiconductor Group 47 1997-08-01

C515

AC Characteristics (24 MHz) (cont’d)
External Data Memory Characteristics

Parameter Symbol Limit Values Unit

pulse width t

RD
WR

pulse width t

Address hold after ALE

to valid data in t

RD
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR
Address valid to WR
WR

or RD high to ALE high t

Data valid to WR

or RD t

or RD t

transition t
Data setup before WR
Data hold after WR
Address float after RD

RLRH

WLWH

t

LLAX2

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

LLWL

AVWL

WHLH

QVWX

t

QVWH

t

WHQX

t

RLAZ

24 MHz

Clock

Variable Clock

1/

t

= 1 MHz to 24 MHz

CLCL

min. max. min. max.

180 – 6t
180 – 6t
15 – t
– 118 – 5t

– 70 – ns

CLCL

– 70 – ns

CLCL

– 27 – ns

CLCL

– 90 ns

CLCL

0–0–ns
–63– 2t
– 200 – 8t
– 220 – 9t
75 175 3t
67 – 4t
17 67 t
5–t
170 – 7t
15 – t

– 50 3t

CLCL

– 97 – ns

CLCL

– 25 t

CLCL

– 37 – ns

CLCL

– 122 – ns

CLCL

– 27 – ns

CLCL

– 20 ns

CLCL

– 133 ns

CLCL

– 155 ns

CLCL

+ 50 ns

CLCL

+ 25 ns

CLCL

–0–0ns

External Clock Drive Characteristics
Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 1 MHz to 24 MHz

min. max.

Oscillator period
High time
Low time
Rise time
Fall time

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

41.7 1000 ns
12 t
12 t

CLCL

CLCL

– t
– t

CLCX

CHCX

ns

ns
–12ns
–12ns

Semiconductor Group 48 1997-08-01

ALE

t

LHLL

C515

PSEN

Port 0

Port 2

Figure 19
Program Memory Read Cycle

t

AVLL PLPH

t

LLIV

t

t

PLIV

t

AZPL

t

LLAX

t

LLPL

t

t

PXAV

t

PXIZ

PXIX

A0 - A7 Instr.IN A0 - A7

t

AVIV

A8 - A15 A8 - A15

MCT00096

Semiconductor Group 49 1997-08-01

ALE

PSEN

RD

Port 0

t

WHLH

t

LLDV

t

LLWL

t

AVLL

t

LLAX2

A0 - A7 from

Ri or DPL from PCL

t

RLDV

t

RLAZ

t

RLRH

Data IN

t

RHDZ

t

RHDX

A0 - A7 Instr.

C515

IN

Port 2

Figure 20
Data Memory Read Cycle

t

AVWL

t

AVDV

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

MCT00097

Figure 21
CLKOUT Timing

Semiconductor Group 50 1997-08-01

ALE

PSEN

t

WHLH

C515

WR

t

AVLL

Port 0

A0 - A7 from

Ri or DPL from PCL

t

AVWL

Port 2

Figure 22
Data Memory Write Cycle

V

- 0.5V

CC

0.45V

0.2

0.7

V

t

LLAX2

CC

t

LLWL

V

CC

- 0.1

t

QVWX

Data OUT

t

CHCL

t

WLWH

t

QVWH

t

CLCX

t

CLCH

t

CLCL

t

CHCX

t

WHQX

A0 - A7

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

Instr.IN

MCT00098

MCT00033

Figure 23
External Clock Drive at XTAL2

Semiconductor Group 51 1997-08-01

C515

ROM Verification Characteristics for the C515-1RM
ROM Verification Mode 1

Parameter Symbol Limit Values Unit

min. max.

Address to valid data

P1.0 - P1.7
P2.0 - P2.4

Port 0

Address : P1.0 - P1.7 = A0 - A7

t

AVQV

Address

Data OUT

P2.0 - P2.4 = A8 - A12
P0.0 - P0.7 = D0 - D7

– 10 t

New Address

t

AVQV

New Data Out

Inputs : PSEN =

V

SS

ALE, EA =
RESET =Data :

V

V

IH

IL2

MCT03212

ns

CLCL

Figure 24
ROM Verification Mode 1

Semiconductor Group 52 1997-08-01

C515

ROM Verification Mode 2
Parameter Symbol Limit Values Unit

min. typ max.

ALE pulse width
ALE period
Data valid after ALE
Data stable after ALE
P3.5 setup to ALE low
Oscillator frequency

ALE

Port 0

t

AWD

t

AS

t

DVA

t

AWD

t

ACY

t

DVA

t

DSA

t

AS

1/

t

CLCL

t

DSA

–2 t
– 12 t
––4 t
8 t

––ns

CLCL

– t

–ns

CLCL

–ns

CLCL

ns

CLCL

–ns

CLCL

1–24MHz

t

ACY

Data Valid

P3.5

Figure 25
ROM Verification Mode 2

MCT02613

Semiconductor Group 53 1997-08-01

V

-0.5 V

CC

V

+0.90.2

CC

Test Points

V

0.2 -0.1

CC

0.45 V

MCT00039

AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at V

for a logic ’1’ and V

IHmin

for a logic ’0’.

ILmax

Figure 26
AC Testing: Input, Output Waveforms

C515

-0.1 V

V

OH

V

+0.1 V

OL

MCT00038

V

Load

V

V

Load

Load

+0.1 V

Timing Reference

Points

-0.1 V

For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs and begins to float when a 100 mV change from the loaded

V

OH/VOL

level occurs.

Figure 27
AC Testing : Float Waveforms

Crystal Oscillator Mode Driving from External Source

C

XTAL1

N.C.

XTAL1

1-24 MHz

C

Crystal Mode :

C

XTAL2 XTAL2

= 20 pF±10 pF (incl. stray capacitance)

External Oscillator
Signal

MCS03204

Figure 28
Recommended Oscillator Circuits for Crystal Oscillator

Semiconductor Group 54 1997-08-01

Plastic Package, P-MQFP-80-1 (SMD)

(Plastic Metric Quad Flat Package)

C515

Figure 29
P-MQFP-80-1 Package Outlines

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”

SMD = Surface Mounted Device

GPM05249

Dimensions in mm

Semiconductor Group 55 1997-08-01