Datasheet SAB-C167SR-LM, SAF-C167SR-LM, SAK-C167SR-LM Datasheet (Siemens)

Data Sheet 06.95 Advance Information

Microcomputer Components

C167SR

16-Bit CMOS Single-Chip Microcontroller

Edition 06.95
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

©Siemens AG 1995.

All Rights Reserved.

Attention please!

As far as patents or other rights of third par­ties are concerned, liability is only assumed
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characteristics.

Terms of delivery and rights to change design
reserved.

For questions on technology, delivery and
prices please contact the Semiconductor
Group Offices in Germany or the Siemens
Companies and Representatives worldwide
(see address list).

Due to technical requirements components
may contain dangerous substances. For in­formation on the types in question please
contact your nearest Siemens Office, Semi­conductor Group.

Siemens AG is an approved CECC manufac­turer.

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1

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2

with the ex-

Ausgabe 06.95
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Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
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C167SR
Revision History: Original Version: 06.95 (Advance Information)

Previous Releases: Data Sheet C167 06.94
Page Subjects (changes compared to C167)
31 Register PICON added
36 V
36 R
37 I

, V

ILS

RST

P6L

, HYS, IOV added.

IHS

, I

, I

RWH

RWL

, ICC, IID changed.

, I

ALEL

, I

ALEH

, I

, test cond. I

P6H

37 ICC, IID typical values added
39 ADC specification changed.

41...43 PLL description added.
44 External Clock Drive specification changed.
46 t14, t15, t16, t17, t22, t39, t46 changed.
47 t47 changed.
52 t14, t15, t16, t17, t20, t

21,t22

changed.
53 t39, t46, t47, t55 changed.
56, 57 t53 changed to t68.
58 t36 changed.
61 t63 changed.

changed.

OZx

C16x-Family of

C167SR

High-Performance CMOS 16-Bit Microcontrollers

Advance Information
C167SR 16-Bit Microcontroller

High Performance 16-bit CPU with 4-Stage Pipeline

●

●

100 ns Instruction Cycle Time at 20 MHz CPU Clock
500 ns Multiplication (16 × 16 bit), 1 µs Division (32 / 16 bit)

●

●

Enhanced Boolean Bit Manipulation Facilities

● Additional Instructions to Support HLL and Operating Systems

●

Register-Based Design with Multiple Variable Register Banks

●

Single-Cycle Context Switching Support
Clock Generation via on-chip PLL or via direct clock input

●

●

Up to 16 MBytes Linear Address Space for Code and Data
2 KBytes On-Chip Internal RAM (IRAM)

●

●

2 KBytes On-Chip Extension RAM (XRAM)

● Programmable External Bus Characteristics for Different Address Ranges

●

8-Bit or 16-Bit External Data Bus

●

Multiplexed or Demultiplexed External Address/Data Buses
Five Programmable Chip-Select Signals

●

●

Hold- and Hold-Acknowledge Bus Arbitration Support
1024 Bytes On-Chip Special Function Register Area

●

●

Idle and Power Down Modes

● 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event

Controller (PEC)

●

16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns

●

16-Channel 10-bit A/D Converter with 9.7 µs Conversion Time

●

Two 16-Channel Capture/Compare Units
4-Channel PWM Unit

●

●

Two Multi-Functional General Purpose Timer Units with 5 Timers

● Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

●

Programmable Watchdog Timer

●

Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

●

Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards

●

On-Chip Bootstrap Loader

● 144-Pin MQFP Package (EIAJ)

This document describes the SAB-C167SR-LM, the SAF-C167SR-LM and the SAK-C167SR-LM.
For simplicity all versions are referred to by the term C167SR throughout this document.

Semiconductor Group 1 06.95

C167SR
Revision History: Original Version: 06.95 (Advance Information)

Previous Releases: Data Sheet C167 06.94
Page Subjects (changes compared to C167)
31 Register PICON added
36
36
37
37

V

,

ILS

R

RST

I

P6L

I

CC

, HYS,

IHS

I

,

,

RWH

I

I

,

,

CC

ID

I

,

typical values added

ID

I

added.

OV

I

I

,

RWL

ALEL

changed.

I

ALEH

I

,

, test cond.

P6H

,

I

changed.

OZx

V

39 ADC specification changed.

41...43 PLL description added.

C167SR

44 External Clock Drive specification changed.

t

t

t

t

t

t

46
47
52
53
56, 57
58
61

,

,

14

15

16

t

changed.

47

t

t

t

,

,

14

15

16

t

t

t

,

,

39

46

47

t

changed to

53

t

changed.

36

t

changed.

63

,

,

17

t

t

,

,

17

t

,

changed.

55

22

,

20

t

68

,

t

21,

.

t

,

39

46

t

changed.

22

changed.

Semiconductor Group 2

C167SR

Introduction

The C167SR is a new derivative of the Siemens C16x Family of full featured single-chip CMOS
microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities. It also provides on-chip high-speed RAM
and clock generation via PLL.

C167SR

Figure 1
Logic Symbol

Ordering Information
Type Ordering Code Package Function

SAB-C167SR-LM Q67121-C952 P-MQFP-144-1 16-bit microcontroller with

2 × 2 KByte RAM
Temperature range 0 to + 70 ˚C

SAF-C167SR-LM Q67121-C953 P-MQFP-144-1 16-bit microcontroller with

2 × 2 KByte RAM
Temperature range – 40 to + 85 ˚C

SAK-C167SR-LM C P-MQFP-144-1 16-bit microcontroller with

2 × 2 KByte RAM
Temperature range – 40 to + 125 ˚C

Semiconductor Group 3

Pin Configuration

(top view)

C167SR

Figure 2

C167SR

Semiconductor Group 4

Pin Definitions and Functions

C167SR

Symbol Pin

Number

P6.0 ­P6.7

P8.0 ­P8.7

1 ­8

1
...
5
6
7
8

9 ­16

9
...
16

Input (I)
Output (O)

I/O

O
...
O
I
O
O

I/O

I/O
...
I/O

Function

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The following Port 6 pins also serve for alternate functions:
P6.0 CS0

... ... ...

P6.4 CS4 Chip Select 4 Output
P6.5 HOLD External Master Hold Request Input
P6.6 HLDA Hold Acknowledge Output
P6.7 BREQ Bus Request Output

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out

... ... ...

P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out

Chip Select 0 Output

P7.0 ­P7.7

19 ­26

19
...
22
23
...
26

I/O

O
...
O
I/O
...
I/O

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 7 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 7 is
selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
P7.0 POUT0 PWM Channel 0 Output

... ... ...

P7.3 POUT3 PWM Channel 3 Output
P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out

... ... ...

P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out

Semiconductor Group 5

C167SR

Pin Definitions and Functions
Symbol Pin

Number

P5.0 ­P5.15

P2.0 ­P2.15

27 - 36
39 - 44

39
40
41
42
43
44

47 - 54
57 - 64

47
...
54
57

...
64

Input (I)
Output (O)

I
I

I
I
I
I
I
I

I/O

I/O
...
I/O
I/O
I
...
I/O
I
I

(cont’d)

Function

Port 5 is a 16-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 16)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x), or they serve as timer
inputs:
P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input
P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input
P5.12 T6IN GPT2 Timer T6 Count Input
P5.13 T5IN GPT2 Timer T5 Count Input
P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 2 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 2 is
selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out

... ... ...

P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out
P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out,

EX0IN Fast External Interrupt 0 Input

... ... ...

P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out,

EX7IN Fast External Interrupt 7 Input

T7IN CAPCOM2 Timer T7 Count Input

Semiconductor Group 6

C167SR

Pin Definitions and Functions
Symbol Pin

Number

P3.0 ­P3.13,
P3.15

65 - 70,
73 - 80,
81

65
66
67
68
69
70

73
74

75
76
77
78
79

80
81

Input (I)
Output (O)

I/O
I/O
I/O

I
O
I
O
I
I

I
I

I/O
I/O
O
I/O
O
O
I/O
O

(cont’d)

Function

Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is
bit-wise programmable for input or output via direction bits.
For a pin configured as input, the output driver is put into high­impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
P3.0 T0IN CAPCOM Timer T0 Count Input
P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
P3.2 CAPIN GPT2 Register CAPREL Capture Input
P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input
P3.5 T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture
P3.6 T3IN GPT1 Timer T3 Count/Gate Input
P3.7 T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture
P3.8 MRST SSC Master-Rec./Slave-Transmit I/O
P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I
P3.10 T×D0 ASC0 Clock/Data Output (Asyn./Syn.)
P3.11 R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12 BHE

WRH Ext. Memory High Byte Write Strobe
P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp.
P3.15 CLKOUT System Clock Output (=CPU Clock)

Ext. Memory High Byte Enable Signal,

P4.0 ­P4.7

RD

Semiconductor Group 7

85 - 92

85
...
89
...
92

95 O External Memory Read Strobe. RD is activated for every

I/O

O
...
O
...
O

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0 A16 Least Significant Segment Addr. Line

... ... ...

P4.4 A20 Least Significant Segment Addr. Line
.. : :
P4.7 A23 Most Significant Segment Addr. Line

external instruction or data read access.

C167SR

Pin Definitions and Functions
Symbol Pin

Number

/

WR
WRL

READY

ALE 98 O Address Latch Enable Output. Can be used for latching the

EA

96 O External Memory Write Strobe. In WR-mode this pin is

97 I Ready Input. When the Ready function is enabled, a high

99 I External Access Enable pin. A low level at this pin during and

Input (I)
Output (O)

(cont’d)

Function

activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16­bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.

level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.

address into external memory or an address latch in the
multiplexed bus modes.

after Reset forces the C167SR to begin instruction execution
out of external memory. A high level forces execution out of
the internal ROM. ROMless versions must have this pin tied
to ‘0’.

PORT0:
P0L.0 ­P0L.7,
P0H.0 ­P0H.7

100 ­107
108,
111-117

I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed bus
modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit
P0L.0 - P0L.7: D0 - D7 D0 - D7
P0H.0- P0H.7: I/O D8 - D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit
P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7
P0H.0 - P0H.7: A8 - A15 AD8 - AD15

Semiconductor Group 8

C167SR

Pin Definitions and Functions
Symbol Pin

Number

PORT1:
P1L.0 ­P1L.7,
P1H.0 ­P1H.7

118 ­125
128 ­135

132
133
134
135

XTAL1

XTAL2

138

137

Input (I)
Output (O)

I/O

I
I
I
I

I

O

(cont’d)

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed
bus mode.
The following PORT1 pins also serve for alternate functions:
P1H.4 CC24IO CAPCOM2: CC24 Capture Input
P1H.5 CC25IO CAPCOM2: CC25 Capture Input
P1H.6 CC26IO CAPCOM2: CC26 Capture Input
P1H.7 CC27IO CAPCOM2: CC27 Capture Input

XTAL1: Input to the oscillator amplifier and input to the

internal clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.

RSTIN

RSTOUT

NMI

V

AREF

V

AGND

V

PP

140 I Reset Input with Schmitt-Trigger characteristics. A low level at

this pin for a specified duration while the oscillator is running
resets the C167SR. An internal pullup resistor permits power­on reset using only a capacitor connected to V

SS

.

141 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.

142 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167SR to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.

37 – Reference voltage for the A/D converter.
38 – Reference ground for the A/D converter.
84 – Flash programming voltage. This pin accepts the

programming voltage for flash versions of the C167SR.
Note: This pin is not connected (NC) on non-flash versions.

Semiconductor Group 9

Pin Definitions and Functions (cont’d)

C167SR

Symbol Pin

Number

V

CC

17, 46,
56, 72,
82, 93,
109,
126,
136, 144

V

SS

18, 45,
55, 71,
83, 94,
110,
127,
139, 143

Input (I)

Function

Output (O)

– Digital Supply Voltage:

+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode.

– Digital Ground.

Semiconductor Group 10

C167SR

Functional Description

The architecture of the C167SR combines advantages of both RISC and CISC processors and of
advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an
overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the C167SR.

Note: All time specifications refer to a CPU clock of 20 MHz

(see definition in the AC Characteristics section).

Figure 3
Block Diagram

Semiconductor Group 11

C167SR

Memory Organization

The memory space of the C167SR is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bitaddressable.

The C167SR is prepared to incorporate on-chip mask-programmable ROM or Flash Memory for
code or constant data. Currently no ROM is integrated.

2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the
system stack, general purpose register banks and even for code. A register bank can consist of up
to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose
Registers (GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C16x family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code.
The XRAM is accessed like external memory and therefore cannot be used for the system stack or
for register banks and is not bitadressable. The XRAM allows 16-bit accesses with maximum
speed.

In order to meet the needs of designs where more memory is required than is provided on chip, up
to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on

PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-

State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories. In addition, different address ranges
may be accessed with different bus characteristics. Up to 5 external CS
in order to save external glue logic. Access to very slow memories is supported via a particular
‘Ready’ function. A HOLD/HLDA protocol is available for bus arbitration.

signals can be generated

For applications which require less than 16 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.

Semiconductor Group 12

C167SR

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C167SR’s instructions can be executed in just one
machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very
fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

Figure 4
CPU Block Diagram

Semiconductor Group 13

C167SR

The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C167SR instruction set which includes the following
instruction classes:

– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.

Semiconductor Group 14

C167SR

Interrupt System

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal
program execution), the C167SR is capable of reacting very fast to the occurence of non­deterministic events.

The architecture of the C167SR supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The C167SR
has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.

Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.

The following table shows all of the possible C167SR interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

Note: Three nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from

integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used
to generate software controlled interrupt requests by setting the respective XPnIR bit.

Semiconductor Group 15

C167SR

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004C
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005C
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006C
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007C
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CC
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0
CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DC
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4
CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00EC
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080

Trap
Number

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H
H

10

H

11

H

12

H

13

H

H

H

H
H
H
H

H
H
H
H

H
H
H
H

H
H

14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
44
45
46
20

H
H
H
H
H
H
H

H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H

H

H

H
H
H
H
H

Semiconductor Group 16

C167SR

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8
GPT1 Timer 2 T2IR T2IE T2INT 00’0088
GPT1 Timer 3 T3IR T3IE T3INT 00’008C
GPT1 Timer 4 T4IR T4IE T4INT 00’0090
GPT2 Timer 5 T5IR T5IE T5INT 00’0094
GPT2 Timer 6 T6IR T6IE T6INT 00’0098
GPT2 CAPREL Register CRIR CRIE CRINT 00’009C
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0
A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C
ASC0 Receive S0RIR S0RIE S0RINT 00’00AC
ASC0 Error S0EIR S0EIE S0EINT 00’00B0
SSC Transmit SCTIR SCTIE SCTINT 00’00B4
SSC Receive SCRIR SCRIE SCRINT 00’00B8
SSC Error SCEIR SCEIE SCEINT 00’00BC
PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FC
X-Peripheral Node XP0IR XP0IE XP0INT 00’0100
X-Peripheral Node XP1IR XP1IE XP1INT 00’0104
X-Peripheral Node XP2IR XP2IE XP2INT 00’0108
PLL Unlock XP3IR XP3IE XP3INT 00’010C

Trap
Number

H
H
H
H

H
H
H

H
H
H

21

H

3D

H

3E

H

22

H

23

H

H
H
H
H
H

H
H
H
H

H
H

H

24
25
26
27
28
29
2A
47
2B
2C
2D
2E
2F
3F
40
41
42
43

H
H
H
H
H
H
H

H

H

H
H
H

H
H
H
H
H
H
H

Semiconductor Group 17

C167SR

The C167SR also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during run­time:

Exception Condition Trap

Flag

Trap
Vector

Vector
Location

Reset Functions:

Hardware Reset
Software Reset
Watchdog Timer Overflow

RESET
RESET
RESET

00’0000
00’0000
00’0000

Class A Hardware Traps:

Non-Maskable Interrupt
Stack Overflow
Stack Underflow

NMI
STKOF
STKUF

NMITRAP
STOTRAP
STUTRAP

00’0008
00’0010
00’0018

Class B Hardware Traps:

Undefined Opcode
Protected Instruction

UNDOPC
PRTFLT

BTRAP
BTRAP

00’0028

00’0028
Fault
Illegal Word Operand

ILLOPA

BTRAP

00’0028
Access
Illegal Instruction Access
Illegal External Bus

ILLINA
ILLBUS

BTRAP
BTRAP

00’0028

00’0028
Access

Reserved [2C
Software Traps

TRAP Instruction

Any

[00’0000

00’01FCH]

in steps

of 4

Trap
Number

H
H
H

H
H
H

H
H

H

H
H

– 3CH] [0BH – 0FH]

H

00
00
00

02
04
06

0A
0A

0A

0A
0A

H
H
H

H
H
H

H
H

H

H
H

Any

–

[00H – 7FH]

H

H

Trap
Priority

III
III
III

II
II
II

I
I

I

I
I

Current
CPU
Priority

Semiconductor Group 18

C167SR

Capture/Compare (CAPCOM) Units

The CAPCOM units support generation and control of timing sequences on up to 32 channels with
a maximum resolution of 400 ns (at 20-MHz system clock). The CAPCOM units are typically used
to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external
events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the
capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal system
clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a
wide range of variation for the timer period and resolution and allows precise adjustments to the
application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7
allow event scheduling for the capture/compare registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8,
respectively), and programmed for capture or compare function. Each register has one port pin
associated with it which serves as an input pin for triggering the capture function, or as an output pin
(except for CC24...CC27) to indicate the occurence of a compare event.

When a capture/compare register has been selected for capture mode, the current contents of the
allocated timer will be latched (‘capture’d) into the capture/compare register in response to an
external event at the port pin which is associated with this register. In addition, a specific interrupt
request for this capture/compare register is generated. Either a positive, a negative, or both a
positive and a negative external signal transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes are
continuously compared with the contents of the allocated timers. When a match occurs between the
timer value and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.

Compare Modes Function

Mode 0 Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1 Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2 Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double
Register Mode

Semiconductor Group 19

Two registers operate on one pin; pin toggles on each compare match;
several compare events per timer period are possible.

C167SR

*)

*) 12 outputs on CAPCOM2

Figure 5
CAPCOM Unit Block Diagram

Semiconductor Group 20

C167SR

PWM Module

The Pulse Width Modulation Module can generate up to four PWM output signals using edge­aligned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and
single shot outputs. The frequency range of the PWM signals covers 4.8 Hz to 1 MHz (referred to
a CPU clock of 20 MHz), depending on the resolution of the PWM output signal. The level of the
output signals is selectable and the PWM module can generate interrupt requests.

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1
and GPT2. Each timer in each module may operate independently in a number of different modes,
or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three
basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the
input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while
Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 400 ns (@ 20-MHz CPU clock).

The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking.

Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer over­flow/underflow. The state of these latches may be output on port pins (TxOUT) e. g. for time out
monitoring of external hardware components, or may be used internally to clock timers T2 and T4
for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.

With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler or with external signals. The count direction (up/down) for each timer is
programmable by software or may additionally be altered dynamically by an external signal on a
port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of
timer T6, which changes its state on each timer overflow/underflow.

Semiconductor Group 21

C167SR

The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register. The CAPREL register may capture the contents
of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer
T5 may optionally be cleared after the capture procedure. This allows absolute time differences to
be measured or pulse multiplication to be performed without software overhead.

Figure 6
Block Diagram of GPT1

Semiconductor Group 22

C167SR

Figure 7
Block Diagram of GPT2

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT
in order to allow external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 25 µs and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval
after reset is 6.55 ms (@ 20 MHz).

pin low

Semiconductor Group 23

C167SR

A/D Converter

For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a
sample and hold circuit has been integrated on-chip. It uses the method of successive
approximation. The sample time (for loading the capacitors) and the conversion time is
programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register (ADDAT): either an
interrupt request will be generated when the result of a previous conversion has not been read from
the result register at the time the next conversion is complete, or the next conversion is suspended
in such a case until the previous result has been read.

For applications which require less than 16 analog input channels, the remaining channel inputs can
be used as digital input port pins.

The A/D converter of the C167SR supports four different conversion modes. In the standard Single
Channel conversion mode, the analog level on a specified channel is sampled once and converted
to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel
is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the
analog levels on a prespecified number of channels are sequentially sampled and converted. In the
Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and
converted. In addition, the conversion of a specific channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is called Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the conversion results
into a table in memory for later evaluation, without requiring the overhead of entering and exiting
interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs calibration
cycles. This automatic self-calibration constantly adjusts the converter to changing operating
conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal operation
of the A/D converter.

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

ASC0 is upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family
and support full-duplex asynchronous communication up to 625 KBaud and half-duplex
synchronous communication up to 2.5 Mbaud on the @ 20-MHz system clock.
The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20-MHz system clock.

Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning.
For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for
each serial channel.

Semiconductor Group 24

C167SR

In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit
and terminated by one or two stop bits. For multiprocessor communication, a mechanism to
distinguish address from data bytes has been included (8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length
synchronously to a shift clock which can be generated by the SSC (master mode) or by an external
master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0
always shifts the LSB first.
A loop back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.

Parallel Ports

The C167SR provides up to 111 I/O lines which are organized into eight input/output ports and one
input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of five
I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. During the internal reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the
special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input
threshold may be selected individually for each byte of the respective ports.

All port lines have programmable alternate input or output functions associated with them.
PORT0 and PORT1 may be used as address and data lines when accessing external memory,
while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where
segmentation is enabled to access more than 64 KBytes of memory.

Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM
units and/or with the outputs of the PWM module.
Port 6 provides optional bus arbitration signals (BREQ
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE
and the system clock output (CLKOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.

, HLDA, HOLD) and chip select signals.

All port lines that are not used for these alternate functions may be used as general purpose IO
lines.

Semiconductor Group 25

C167SR

Instruction Set Summary

The table below lists the instructions of the C167SR in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the “C16x Family Instruction Set Manual”.

This document also provides a detailled description of each instruction.

Instruction Set Summary
Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2 / 4
OR(B) Bitwise OR, (word/byte operands) 2 / 4
XOR(B) Bitwise XOR, (word/byte operands) 2 / 4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

4

CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2

Semiconductor Group 26

2

C167SR

Instruction Set Summary
Mnemonic Description Bytes

MOV(B) Move word (byte) data 2 / 4
MOVBS Move byte operand to word operand with sign extension 2 / 4
MOVBZ Move byte operand to word operand. with zero extension 2 / 4
JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call

TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2

(cont’d)

4

absolute subroutine

SCXT Push direct word register onto system stack und update

register with word operand
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct

word register from system stack
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode

(supposes NMI
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4

-pin being low)

4

2

4

EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2

Semiconductor Group 27

C167SR

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C167SR in alphabetical order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).

Special Function Registers Overview
Name Physical

Address

ADCIC b FF98

ADCON b FFA0
ADDAT FEA0

H

H
H

8-Bit
Address

CC

D0
50

ADDAT2 F0A0HE 50
ADDRSEL1 FE18
ADDRSEL2 FE1A
ADDRSEL3 FE1C
ADDRSEL4 FE1E
ADEIC b FF9A

BUSCON0 b FF0C
BUSCON1 b FF14
BUSCON2 b FF16

0C

H

0D

H

0E

H

0F

H

CD

H

86

H

8A

H

8B

H

Description Reset

Value

H

A/D Converter End of Conversion Interrupt

0000

H

Control Register

H

H
H

H

H

H

H

H

A/D Converter Control Register 0000
A/D Converter Result Register 0000
A/D Converter 2 Result Register 0000
Address Select Register 1 0000
Address Select Register 2 0000
Address Select Register 3 0000
Address Select Register 4 0000
A/D Converter Overrun Error Interrupt Control

0000

H
H
H
H
H
H
H
H

Register

H

H

H

Bus Configuration Register 0 0XX0
Bus Configuration Register 1 0000
Bus Configuration Register 2 0000

H
H
H

BUSCON3 b FF18
BUSCON4 b FF1A
CAPREL FE4A
CC0 FE80
CC0IC b FF78
CC1 FE82
CC1IC b FF7A
CC2 FE84
CC2IC b FF7C

8C

H

H

H
H
H
H

H
H

H

8D
25
40
BC
41
BD
42
BE

H

H
H
H

H

H

H

H

H

Bus Configuration Register 3 0000
Bus Configuration Register 4 0000
GPT2 Capture/Reload Register 0000
CAPCOM Register 0 0000
CAPCOM Register 0 Interrupt Control Register 0000
CAPCOM Register 1 0000
CAPCOM Register 1 Interrupt Control Register 0000
CAPCOM Register 2 0000
CAPCOM Register 2 Interrupt Control Register 0000

Semiconductor Group 28

H
H
H
H
H
H
H
H
H

Special Function Registers Overview (cont’d)

C167SR

Name Physical

Address

CC3 FE86
CC3IC b FF7E
CC4 FE88
CC4IC b FF80
CC5 FE8A
CC5IC b FF82
CC6 FE8C
CC6IC b FF84
CC7 FE8E
CC7IC b FF86
CC8 FE90
CC8IC b FF88
CC9 FE92

H

H
H
H

H
H

H
H

H
H
H
H
H

8-Bit
Address

43

H

BF

H

44

H

C0

H

45

H

C1

H

46

H

C2

H

47

H

C3

H

48

H

C4

H

49

H

Description Reset

Value

CAPCOM Register 3 0000
CAPCOM Register 3 Interrupt Control Register 0000
CAPCOM Register 4 0000
CAPCOM Register 4 Interrupt Control Register 0000
CAPCOM Register 5 0000
CAPCOM Register 5 Interrupt Control Register 0000
CAPCOM Register 6 0000
CAPCOM Register 6 Interrupt Control Register 0000
CAPCOM Register 7 0000
CAPCOM Register 7 Interrupt Control Register 0000
CAPCOM Register 8 0000
CAPCOM Register 8 Interrupt Control Register 0000
CAPCOM Register 9 0000

H
H
H
H
H
H
H
H
H
H
H
H
H

CC9IC b FF8A
CC10 FE94
CC10IC b FF8C
CC11 FE96
CC11IC b FF8E
CC12 FE98
CC12IC b FF90
CC13 FE9A
CC13IC b FF92
CC14 FE9C
CC14IC b FF94
CC15 FE9E
CC15IC b FF96
CC16 FE60

C5

H

4A

H

C6

H

4B

H

C7

H

4C

H

C8

H

4D

H

C9

H

4E

H

CA

H

4F

H

CB

H

30

H

CC16IC b F160HE B0

H
H
H
H
H
H
H
H
H
H

H

H

H

H

H

CAPCOM Register 9 Interrupt Control Register 0000
CAPCOM Register 10 0000
CAPCOM Register 10 Interrupt Control Register 0000
CAPCOM Register 11 0000
CAPCOM Register 11 Interrupt Control Register 0000
CAPCOM Register 12 0000
CAPCOM Register 12 Interrupt Control Register 0000
CAPCOM Register 13 0000
CAPCOM Register 13 Interrupt Control Register 0000
CAPCOM Register 14 0000
CAPCOM Register 14 Interrupt Control Register 0000
CAPCOM Register 15 0000
CAPCOM Register 15 Interrupt Control Register 0000
CAPCOM Register 16 0000
CAPCOM Register 16 Interrupt Control Register 0000

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

CC17 FE62

31

H

H

CAPCOM Register 17 0000

Semiconductor Group 29

H

Special Function Registers Overview (cont’d)

C167SR

Name Physical

Address

CC17IC b F162

H

CC18 FE64

H

8-Bit
Address

E B1

32

CC18IC b F164HE B2
CC19 FE66

33

H

CC19IC b F166HE B3
CC20 FE68

34

H

CC20IC b F168HE B4
CC21 FE6A

35

H

CC21IC b F16AHE B5
CC22 FE6C

36

H

CC22IC b F16CHE B6
CC23 FE6E

37

H

CC23IC b F16EHE B7

Description Reset

Value

H

H

H

H

H

H

H

H

H

H

H

H

H

CAPCOM Register 17 Interrupt Control Register 0000
CAPCOM Register 18 0000
CAPCOM Register 18 Interrupt Control Register 0000
CAPCOM Register 19 0000
CAPCOM Register 19 Interrupt Control Register 0000
CAPCOM Register 20 0000
CAPCOM Register 20 Interrupt Control Register 0000
CAPCOM Register 21 0000
CAPCOM Register 21 Interrupt Control Register 0000
CAPCOM Register 22 0000
CAPCOM Register 22 Interrupt Control Register 0000
CAPCOM Register 23 0000
CAPCOM Register 23 Interrupt Control Register 0000

H
H
H
H
H
H
H
H
H
H
H
H
H

CC24 FE70

38

H

CC24IC b F170HE B8
CC25 FE72

39

H

CC25IC b F172HE B9
CC26 FE74

3A

H

CC26IC b F174HE BA
CC27 FE76

3B

H

CC27IC b F176HE BB
CC28 FE78

3C

H

CC28IC b F178HE BC
CC29 FE7A

3D

H

CC29IC b F184HE C2
CC30 FE7C

3E

H

CC30IC b F18CHE C6
CC31 FE7E

3F

H

H

H

H

H
H

H

H

H

H

H
H
H
H
H

H

CAPCOM Register 24 0000
CAPCOM Register 24 Interrupt Control Register 0000
CAPCOM Register 25 0000
CAPCOM Register 25 Interrupt Control Register 0000
CAPCOM Register 26 0000
CAPCOM Register 26 Interrupt Control Register 0000
CAPCOM Register 27 0000
CAPCOM Register 27 Interrupt Control Register 0000
CAPCOM Register 28 0000
CAPCOM Register 28 Interrupt Control Register 0000
CAPCOM Register 29 0000
CAPCOM Register 29 Interrupt Control Register 0000
CAPCOM Register 30 0000
CAPCOM Register 30 Interrupt Control Register 0000
CAPCOM Register 31 0000

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

CC31IC b F194HE CA

H

CAPCOM Register 31 Interrupt Control Register 0000

Semiconductor Group 30

H

Special Function Registers Overview (cont’d)

C167SR

Name Physical

Address

CCM0 b FF52
CCM1 b FF54
CCM2 b FF56
CCM3 b FF58
CCM4 b FF22
CCM5 b FF24
CCM6 b FF26
CCM7 b FF28
CP FE10
CRIC b FF6A
CSP FE08

H
H
H
H
H
H
H
H
H

H

H

8-Bit
Address

A9
AA
AB
AC
91
92
93
94
08
B5
04

DP0L b F100HE 80
DP0H b F102HE 81

Description Reset

Value

H

H

H

H

H
H
H
H
H

H

H
H
H

CAPCOM Mode Control Register 0 0000
CAPCOM Mode Control Register 1 0000
CAPCOM Mode Control Register 2 0000
CAPCOM Mode Control Register 3 0000
CAPCOM Mode Control Register 4 0000
CAPCOM Mode Control Register 5 0000
CAPCOM Mode Control Register 6 0000
CAPCOM Mode Control Register 7 0000
CPU Context Pointer Register FC00
GPT2 CAPREL Interrupt Control Register 0000
CPU Code Segment Pointer Register (read only) 0000
P0L Direction Control Register 00
P0H Direction Control Register 00

H
H

H
H
H
H
H
H
H
H

H
H
H

DP1L b F104HE 82
DP1H b F106HE 83
DP2 b FFC2
DP3 b FFC6
DP4 b FFCA
DP6 b FFCE
DP7 b FFD2
DP8 b FFD6
DPP0 FE00
DPP1 FE02
DPP2 FE04
DPP3 FE06

E1

H

E3

H

E5

H

E7

H

E9

H

EB

H

00

H

01

H

02

H

03

H

EXICON b F1C0HE E0
MDC b FF0E
MDH FE0C

87

H

06

H

H
H

H
H
H
H
H

H
H
H
H
H

H
H
H

P1L Direction Control Register 00
P1H Direction Control Register 00

H
H

Port 2 Direction Control Register 0000
Port 3 Direction Control Register 0000
Port 4 Direction Control Register 00
Port 6 Direction Control Register 00
Port 7 Direction Control Register 00
Port 8 Direction Control Register 00

H
H
H
H

CPU Data Page Pointer 0 Register (10 bits) 0000
CPU Data Page Pointer 1 Register (10 bits) 0001
CPU Data Page Pointer 2 Register (10 bits) 0002
CPU Data Page Pointer 3 Register (10 bits) 0003
External Interrupt Control Register 0000
CPU Multiply Divide Control Register 0000
CPU Multiply Divide Register – High Word 0000

H
H

H
H
H
H
H
H
H

MDL FE0E

07

H

H

CPU Multiply Divide Register – Low Word 0000

Semiconductor Group 31

H

Special Function Registers Overview (cont’d)

C167SR

Name Physical

Address

ODP2 b F1C2

H

8-Bit
Address

E E1
ODP3 b F1C6HE E3
ODP6 b F1CEHE E7
ODP7 b F1D2HE E9
ODP8 b F1D6HE EB
ONES FF1E
P0L b FF00
P0H b FF02
P1L b FF04
P1H b FF06
P2 b FFC0
P3 b FFC4
P4 b FFC8

8F

H

80

H

81

H

82

H

83

H

E0

H

E2

H

E4

H

Description Reset

Value

H
H
H
H

H
H
H
H
H
H

H
H
H

Port 2 Open Drain Control Register 0000
Port 3 Open Drain Control Register 0000
Port 6 Open Drain Control Register 00
Port 7 Open Drain Control Register 00
Port 8 Open Drain Control Register 00

H
H
H

Constant Value 1’s Register (read only) FFFF
Port 0 Low Register (Lower half of PORT0) 00
Port 0 High Register (Upper half of PORT0) 00
Port 1 Low Register (Lower half of PORT1) 00
Port 1 High Register (Upper half of PORT1) 00

H
H
H
H

Port 2 Register 0000
Port 3 Register 0000
Port 4 Register (8 bits) 00

H

H
H

H

H
H

P5 b FFA2
P6 b FFCC
P7 b FFD0
P8 b FFD4
PECC0 FEC0
PECC1 FEC2
PECC2 FEC4
PECC3 FEC6
PECC4 FEC8
PECC5 FECA
PECC6 FECC
PECC7 FECE

D1

H

E6

H

E8

H

EA

H

60

H

61

H

62

H

63

H

64

H

65

H

66

H

67

H

PICON F1C4HE E2
PP0 F038HE 1C
PP1 F03AHE 1D

H
H
H

H
H
H
H
H
H
H
H
H

H
H
H

Port 5 Register (read only) XXXX
Port 6 Register (8 bits) 00
Port 7 Register (8 bits) 00
Port 8 Register (8 bits) 00

H
H
H

PEC Channel 0 Control Register 0000
PEC Channel 1 Control Register 0000
PEC Channel 2 Control Register 0000
PEC Channel 3 Control Register 0000
PEC Channel 4 Control Register 0000
PEC Channel 5 Control Register 0000
PEC Channel 6 Control Register 0000
PEC Channel 7 Control Register 0000
Port Input Threshold Control Register 0000
PWM Module Period Register 0 0000
PWM Module Period Register 1 0000

H

H
H
H
H
H
H
H
H
H
H
H

PP2 F03CHE 1E

H

PWM Module Period Register 2 0000

Semiconductor Group 32

H

Special Function Registers Overview (cont’d)

C167SR

Name Physical

Address

PP3 F03E
PSW b FF10

H
H

8-Bit
Address

E 1F

88

PT0 F030HE 18
PT1 F032HE 19
PT2 F034HE 1A
PT3 F036HE 1B
PW0 FE30
PW1 FE32
PW2 FE34
PW3 FE36
PWMCON0b FF30
PWMCON1b FF32

18

H

19

H

1A

H

1B

H

98

H

99

H

PWMIC b F17EHE BF

Description Reset

Value

H
H
H
H

H

H
H
H

H

H
H
H

H

PWM Module Period Register 3 0000
CPU Program Status Word 0000
PWM Module Up/Down Counter 0 0000
PWM Module Up/Down Counter 1 0000
PWM Module Up/Down Counter 2 0000
PWM Module Up/Down Counter 3 0000
PWM Module Pulse Width Register 0 0000
PWM Module Pulse Width Register 1 0000
PWM Module Pulse Width Register 2 0000
PWM Module Pulse Width Register 3 0000
PWM Module Control Register 0 0000
PWM Module Control Register 1 0000
PWM Module Interrupt Control Register 0000

H
H
H
H
H
H
H
H
H
H
H
H
H

RP0H b F108HE 84
S0BG FEB4

S0CON b FFB0
S0EIC b FF70
S0RBUF FEB2

S0RIC b FF6E

5A

H

D8

H

B8

H

59

H

B7

H

S0TBIC b F19CHE CE

S0TBUF FEB0

S0TIC b FF6C

SP FE12

58

H

B6

H

09

H

SSCBR F0B4HE 5A

H

H

System Startup Configuration Register (Rd. only) XX
Serial Channel 0 Baud Rate Generator Reload

0000

H

H

Register

H

H
H

Serial Channel 0 Control Register 0000
Serial Channel 0 Error Interrupt Control Register 0000
Serial Channel 0 Receive Buffer Register

XX

H

H
H

(read only)

H

Serial Channel 0 Receive Interrupt Control

0000

H

Register

H

Serial Channel 0 Transmit Buffer Interrupt Control

0000

H

Register

H

Serial Channel 0 Transmit Buffer Register

00

H

(write only)

H

Serial Channel 0 Transmit Interrupt Control

0000

H

Register

H

H

CPU System Stack Pointer Register FC00
SSC Baudrate Register 0000

H

H

SSCCON b FFB2

D9

H

H

SSC Control Register 0000

Semiconductor Group 33

H

Special Function Registers Overview (cont’d)

C167SR

Name Physical

Address

SSCEIC b FF76

H

8-Bit
Address

BB

SSCRB F0B2HE 59
SSCRIC b FF74

BA

H

SSCTB F0B0HE 58
SSCTIC b FF72
STKOV FE14
STKUN FE16
SYSCON b FF12
T0 FE50
T01CON b FF50
T0IC b FF9C
T0REL FE54
T1 FE52

B9

H

0A

H

0B

H

89

H

28

H

A8

H

CE

H

2A

H

29

H

Description Reset

Value

H

H

H

H

H

H

H
H
H

H

H

H
H

SSC Error Interrupt Control Register 0000
SSC Receive Buffer (read only) XXXX
SSC Receive Interrupt Control Register 0000
SSC Transmit Buffer (write only) 0000
SSC Transmit Interrupt Control Register 0000
CPU Stack Overflow Pointer Register FA00
CPU Stack Underflow Pointer Register FC00
CPU System Configuration Register 0xx0
CAPCOM Timer 0 Register 0000
CAPCOM Timer 0 and Timer 1 Control Register 0000
CAPCOM Timer 0 Interrupt Control Register 0000
CAPCOM Timer 0 Reload Register 0000
CAPCOM Timer 1 Register 0000

H

H
H
H
H

H
H

1)

H

H
H
H
H
H

T1IC b FF9E
T1REL FE56
T2 FE40
T2CON b FF40
T2IC b FF60
T3 FE42
T3CON b FF42
T3IC b FF62
T4 FE44
T4CON b FF44
T4IC b FF64
T5 FE46
T5CON b FF46
T5IC b FF66
T6 FE48

CF

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

2B
20
A0
B0
21
A1
B1
22
A2
B2
23
A3
B3
24

H

H

H

H
H

H

H
H

H

H
H

H

H
H

H

CAPCOM Timer 1 Interrupt Control Register 0000
CAPCOM Timer 1 Reload Register 0000
GPT1 Timer 2 Register 0000
GPT1 Timer 2 Control Register 0000
GPT1 Timer 2 Interrupt Control Register 0000
GPT1 Timer 3 Register 0000
GPT1 Timer 3 Control Register 0000
GPT1 Timer 3 Interrupt Control Register 0000
GPT1 Timer 4 Register 0000
GPT1 Timer 4 Control Register 0000
GPT1 Timer 4 Interrupt Control Register 0000
GPT2 Timer 5 Register 0000
GPT2 Timer 5 Control Register 0000
GPT2 Timer 5 Interrupt Control Register 0000
GPT2 Timer 6 Register 0000

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

T6CON b FF48

A4

H

H

GPT2 Timer 6 Control Register 0000

Semiconductor Group 34

H

Special Function Registers Overview (cont’d)

C167SR

Name Physical

Address

T6IC b FF68

H

8-Bit
Address

B4

T7 F050HE 28
T78CON b FF20

90

H

T7IC b F17AHE BE
T7REL F054HE 2A
T8 F052HE 29
T8IC b F17CHE BF
T8REL F056HE 2B
TFR b FFAC
WDT FEAE
WDTCON FFAE

D6

H

57

H

D7

H

XP0IC b F186HE C3
XP1IC b F18EHE C7

Description Reset

Value

H
H
H

H

H
H

H

H

H
H

H

H

H

GPT2 Timer 6 Interrupt Control Register 0000
CAPCOM Timer 7 Register 0000
CAPCOM Timer 7 and 8 Control Register 0000
CAPCOM Timer 7 Interrupt Control Register 0000
CAPCOM Timer 7 Reload Register 0000
CAPCOM Timer 8 Register 0000
CAPCOM Timer 8 Interrupt Control Register 0000
CAPCOM Timer 8 Reload Register 0000
Trap Flag Register 0000
Watchdog Timer Register (read only) 0000
Watchdog Timer Control Register 000X
X-Peripheral 0 Interrupt Control Register 0000
X-Peripheral 1 Interrupt Control Register 0000

H
H
H
H
H
H
H
H
H
H

2)

H
H
H

XP2IC b F196HE CB
XP3IC b F19EHE CF
ZEROS b FF1C

1)

The system configuration is selected during reset.

2)

Bit WDTR indicates a watchdog timer triggered reset.

H

8E

H
H

H

X-Peripheral 2 Interrupt Control Register 0000
PLL Interrupt Control Register 0000
Constant Value 0’s Register (read only) 0000

H
H
H

Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from

integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used
to generate software controlled interrupt requests by setting the respective XPnIR bit.

Semiconductor Group 35

Absolute Maximum Ratings

C167SR

Ambient temperature under bias (

T

):

A

SAB-C167SR-LM............................................................................................................0 to + 70 ˚C

SAF-C167SR-LM....................................................................................................... – 40 to + 85 ˚C

SAK-C167SR-LM.....................................................................................................– 40 to + 125 ˚C

Storage temperature (TST)........................................................................................– 65 to + 150 ˚C

Voltage on VCC pins with respect to ground (VSS) .....................................................– 0.5 to + 6.5 V

Voltage on any pin with respect to ground (VSS).................................................– 0.5 to VCC + 0.5 V

Input current on any pin during overload condition.................................................. – 10 to + 10 mA

Absolute sum of all input currents during overload condition.............................................. |100 mA|

Power dissipation.....................................................................................................................1.5 W

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
voltage on pins with respect to ground (VSS) must not exceed the values defined by the
Absolute Maximum Ratings.

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C167SR and partly
its demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column “Symbol”:

CC (Controller Characteristics):
The logic of the C167SR will provide signals with the respective timing characteristics.

SR (System Requirement):
The external system must provide signals with the respective timing characteristics to the C167SR.

Semiconductor Group 36

C167SR

DC Characteristics

V

= 5 V ± 10 %; VSS = 0 V; f

CC

T

= 0 to + 70 ˚C for SAB-C167SR-LM

A

T

= – 40 to + 85 ˚C for SAF-C167SR-LM

A

T

= – 40 to + 125 ˚C for SAK-C167SR-LM

A

Parameter Symbol Limit Values Unit Test Condition

= 20 MHz; Reset active

CPU

min. max.

Input low voltage
(TTL)

Input low voltage
(Special Threshold)

Input high voltage, all except
RSTIN

and XTAL1 (TTL)
Input high voltage RSTIN
Input high voltage XTAL1
Input high voltage

(Special Threshold)
Input Hysteresis

(Special Threshold)
Output low voltage

(PORT0, PORT1, Port 4, ALE, RD

,

WR, BHE, CLKOUT, RSTOUT)
Output low voltage

(all other outputs)
Output high voltage

(PORT0, PORT1, Port 4, ALE, RD

,

WR, BHE, CLKOUT, RSTOUT)
Output high voltage

1)

(all other outputs)
Input leakage current (Port 5)
Input leakage current (all other) I
Overload current I
RSTIN pullup resistor R
Read/Write inactive current
Read/Write active current
ALE inactive current
ALE active current

4)

4)

Port 6 inactive current

4)

4)

4)

V

SR – 0.5 0.2 V

IL

CC

V–

– 0.1

V

SR – 0.5 2.0 V –

ILS

V

SR 0.2 V

IH

CC

V

+ 0.5 V –

CC

+ 0.9

V

IH1

V

IH2

V

IHS

SR 0.6 V
SR 0.7 V
SR 0.8 V

CC

CC

CC

V

+ 0.5 V –

CC

V

+ 0.5 V –

CC

V

+ 0.5 V –

CC

– 0.2

HYS 400 – mV –

V

CC – 0.45 V IOL = 2.4 mA

OL

V

CC – 0.45 V I

OL1

V

CC 0.9 V

OH

CC

–VI

2.4

V

CC 0.9 V

OH1

CC

2.4

I

CC – ±200 nA 0.45V < VIN < V

OZ1

CC – ±500 nA 0.45V < VIN < V

OZ2

SR – ±5mA

OV

CC 50 250 kΩ –

RST

2)

I

RWH

I

RWL

I

ALEL

I

ALEH

I

P6H

– – 40 µA V

3)

– 500 – µA V

2)

–40µAV

3)

500 – µA V

2)

– – 40 µA V

–V

V

OL1

OH

I

OH

I

OH

I

OH

5) 8)

OUT

OUT

OUT

OUT

OUT

= 1.6 mA

= – 500 µA
= – 2.4 mA

= – 250 µA
= – 1.6 mA

= 2.4 V
= V

OLmax

= V

OLmax

= 2.4 V
= 2.4 V

CC

CC

Semiconductor Group 37

C167SR

Parameter Symbol Limit Values Unit Test Condition

min. max.

Port 6 active current
PORT0 configuration current

4)

4)

XTAL1 input current I
Pin capacitance

5)

(digital inputs/outputs)
Power supply current

Idle mode supply current I

Power-down mode supply current I

3)

I
I
I

C

I

P6L

P0H

P0L

IL

IO

CC

ID

PD

3)

– 500 – µA V

2)

– – 10 µA VIN = V

– 100 – µA VIN = V
CC – ± 20 µA 0 V < VIN < V
CC – 10 pF f = 1 MHz

– 20 +

5 × f

– 20 +

2 × f

CPU

CPU

mA RSTIN = V

mA RSTIN = V

– 100 µA VCC = 5.5 V

= V

OUT

T

= 25 ˚C

A

f

in [MHz]

CPU

f

in [MHz]

CPU

OL1max

IHmin

ILmax

IL2

IH1

7)

CC

6)

6)

Notes

1)

This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.

2)

The maximum current may be drawn while the respective signal line remains inactive.

3)

The minimum current must be drawn in order to drive the respective signal line active.

4)

This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if
they are used for CS

5)

Not 100 % tested, guaranteed by design characterization.

6)

The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at V

or VIH.

V

IL

7)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at V

8)

Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin

CC

exceeds the specified range (i.e. V

output and the open drain function is not enabled.

and 20 MHz CPU clock with all outputs disconnected and all inputs at

CCmax

– 0.1 V to VCC, V

= 0 V, all outputs (including pins configured as outputs) disconnected.

REF

> VCC + 0.5 V or VOV < VSS – 0.5 V). The absolute sum of input overload

OV

currents on all port pins may not exceed 50 mA.

Semiconductor Group 38

C167SR

Figure 8
Supply/Idle Current as a Function of Operating Frequency

Semiconductor Group 39

C167SR

A/D Converter Characteristics

V

= 5 V ± 10 %; VSS = 0 V

CC

T

= 0 to + 70 ˚C for SAB-C167SR-LM

A

T

= – 40 to + 85 ˚C for SAF-C167SR-LM

A

T

= – 40 to + 125 ˚C for SAK-C167SR-LM

A

4.0 V ≤ V

Parameter Symbol Limit Values Unit Test Condition

Analog input voltage range
Sample time t
Conversion time t

Total unadjusted error TUE CC – ± 2 LSB
Internal resistance of reference

voltage source
Internal resistance of analog

source
ADC input capacitance C

≤ VCC + 0.1 V; VSS – 0.1 V ≤ V

AREF

≤ VSS + 0.2 V

AGND

min. max.

V

SR V

AIN

CC – 2 t

S

CC – 14 tCC +

C

R

SR – tCC / 165

AREF

AGND

V

t

S

– 0.25

R

SR – tS / 330

ASRC

– 0.25

CC – 33 pF

AIN

AREF

SC

+ 4TCL

V

kΩ

kΩ

1)

2) 4)

3) 4)

5)

t

in [ns] 6)

CC

t

in [ns] 2)

S

7)

7)

7)

Sample time and conversion time of the C167SR’s ADC are programmable. The table below should
be used to calculate the above timings.

ADCON.15|14

(ADCTC)

00 TCL × 24 00 t
01 Reserved, do not use 01 t
10 TCL × 96 10 t
11 TCL × 48 11 t

Conversion Clock t

CC

ADCON.13|12

(ADSTC)

Sample Clock t

CC

× 2

CC

× 4

CC

× 8

CC

SC

Semiconductor Group 40

C167SR

Notes

1)

V

may exceed V

AIN

cases will be X000

2)

During the sample time the input capacitance CI can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within
After the end of the sample time
Values for the sample clock

3)

This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the conversion clock

4)

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

5)

TUE is tested at V
voltages within the defined voltage range.
The specified TUE is guaranteed only if an overload condition (see
selected analog input pins and the absolute sum of input overload currents on all analog input pins does not
exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ± 4 LSB.

6)

During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

t

within

7)

Not 100 % tested, guaranteed by design characterization.

. The maximum internal resistance results from the programmed conversion timing.

CC

or V

AGND

or X3FFH, respectively.

H

= 5.0 V, V

AREF

up to the absolute maximum ratings. However, the conversion result in these

AREF

t

, changes of the analog input voltage have no effect on the conversion result.

S

t

depend on programming and can be taken from the table above.

SC

t

depend on programming and can be taken from the table above.

CC

= 0 V, V

AGND

= 4.9 V. It is guaranteed by design characterization for all other

CC

I

specification) occurs on maximum 2 not

OV

t

.

S

Semiconductor Group 41

Testing Waveforms

AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’.
Timing measurements are made at V

min for a logic ‘1’ and VIL max for a logic ‘0’.

IH

C167SR

Figure 9
Input Output Waveforms

For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs
(IOH/IOL = 20 mA).

Figure 10
Float Waveforms

Semiconductor Group 42

AC Characteristics
Definition of Internal Timing

C167SR

The internal operation of the C167SR is controlled by the internal CPU clock

f

. Both edges of the

CPU

CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time between

two consecutive edges of the CPU clock, called “TCL” (see figure below).

Phase Locked Loop Operation

f

XTAL

f

CPU

TCLTCL

Direct Clock Drive

f

XTAL

f

CPU

TCLTCL

Figure 11
Generation Mechanisms for the CPU Clock

The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their
variation (and also the derived external timing) depends on the used mechanism to generate

f

CPU

This influence must be regarded when calculating the timings for the C167SR.

Direct Drive

When pin P0.15 (P0H.7) is low (‘0’) during reset the on-chip phase locked loop is disabled and the
CPU clock is directly driven from the oscillator with the input clock signal.
The frequency of f
duration of an individual TCL) is defined by the duty cycle of the input clock f

directly follows the frequency of f

CPU

so the high and low time of f

XTAL

XTAL

(i.e. the

CPU

.

The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL
that is possible under the respective circumstances. This minimum value can be calculated via the
following formula:

TCL

For two consecutive TCLs the deviation caused by the duty cycle of f
duration of 2TCL is always 1/f

min

= 1/f

× DC

XTAL

XTAL

min

. The minimum value TCL

(DC = duty cycle)

is compensated so the

XTAL

therefore has to be used only once for

min

timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs
(2,4,...) may use the formula 2TCL = 1/f

XTAL

.

Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of

TCL (TCL

max

= 1/f

XTAL

× DC

) instead of TCL

max

min

.

.

Semiconductor Group 43

C167SR

Phase Locked Loop

When pin P0.15 (P0H.7) is high (‘1’) during reset the on-chip phase locked loop is enabled and
provides the CPU clock. The PLL multiplies the input frequency by 4 (i.e.
fourth transition of f

the PLL circuit synchronizes the CPU clock to the input clock. This

XTAL

synchronization is done smoothely, i.e. the CPU clock frequency does not change abruptly.

f

CPU

= f

× 4). With every

XTAL

Due to this adaptation to the input clock the frequency of f
to f

. The slight variation causes a jitter of f

XTAL

which also effects the duration of individual TCLs.

CPU

is constantly adjusted so it is locked

CPU

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly
adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)
the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula
and figure below).
For a period of N × TCL the minimum value is computed using the corresponding deviation DN:

TCL

= TCL

min

× (1 – DN / 100) DN = ± (4 – N /15) [%],

NOM

where N = number of consecutive TCLs
and 1 ≤ N ≤ 40.

So for a period of 3 TCLs (i.e. N = 3): D3 = 4 – 3/15 = 3.8 %,
and TCL

= TCL

min

× (1 – 3.8 / 100) = TCL

NOM

× 0.962 (24.1 nsec @ f

NOM

= 20 MHz).

CPU

This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial
interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.

Figure 12
Approximated Maximum PLL Jitter

Semiconductor Group 44

C167SR

AC Characteristics
External Clock Drive XTAL1

V

= 5 V ± 10 %; VSS = 0 V

CC

T

= 0 to + 70 ˚C for SAB-C167SR-LM

A

T

= – 40 to + 85 ˚C for SAF-C167SR-LM

A

T

= – 40 to + 125 ˚C for SAK-C167SR-LM

A

Parameter Symbol Direct Drive 1:1 PLL 1:4 Unit

min. max. min. max.

Oscillator period
High time
Low time
Rise time
Fall time

1)

For temperatures above TA = +85 ˚C the minimum value for t1 and t2 is 25 ns.

2)

The clock input signal must reach the defined levels VIL and V

t

SR 50 1000 200 333 ns

OSC

t

SR 23 1)

1

t

SR 23 1)

2

t

SR – 10

3

t

SR – 10 2)– 10 2)ns

4

2)

–10–ns

2)

–10–ns

2)

IH2

– 10

.

2)

ns

Figure 13
External Clock Drive XTAL1

Semiconductor Group 45

C167SR

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.

Description Symbol Values

ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time

t

A

t

C

t

F

TCL × <ALECTL>
2TCL × (15 – <MCTC>)
2TCL × (1 – <MTTC>)

AC Characteristics
Multiplexed Bus

V

= 5 V ± 10 %; VSS = 0 V

CC

T

= 0 to + 70 ˚C for SAB-C167SR-LM

A

T

= – 40 to + 85 ˚C for SAF-C167SR-LM

A

T

= – 40 to + 125 ˚C for SAK-C167SR-LM

A

C

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

L

C

(for Port 6, CS) = 100 pF

L

ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)

Parameter Symbol Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD

WR (with RW-delay)
ALE falling edge to RD

WR (no RW-delay)
Address float after RD

WR (with RW-delay)
Address float after RD

WR (no RW-delay)

, WR low time

RD
(with RW-delay)

, WR low time

RD
(no RW-delay)

min. max. min. max.

t

CC 15 + t

5

t

CC

6

t

CC

7

t

8

t

9

t

10

t

11

t

12

t

13

CC

CC

CC

CC

CC 40 + t

CC 65 + t

,

,

,

,

t

10 +

t

15 +

t

15 +

– 10 +

–5–5ns

– 30 – TCL + 5 ns

– TCL – 10 + tA–ns

A

– TCL – 15 + tA–ns

A

– TCL – 10 + tA–ns

A

– TCL – 10 + tA–ns

A

t

– – 10 + t

A

– 2TCL – 10

C

– 3TCL – 10

C

+ t

+ t

A

C

C

–ns

–ns

–ns

Semiconductor Group 46

C167SR

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

RD

to valid data in

t

SR – 30 + t

14

C

(with RW-delay)

to valid data in

RD

t

SR – 55 + t

15

C

(no RW-delay)

t

ALE low to valid data in

SR – 55

16

+ tA + t

t

Address to valid data in

SR – 70

17

+ 2tA + t

t

Data hold after RD

SR0–0–ns

18

rising edge

t

Data float after RD

Data valid to WR

Data hold after WR

ALE rising edge after RD

,

SR – 35 + t

19

t

SR 25 + t

22

t

CC 35 + t

23

t

CC 35 + t

25

F

– 2TCL – 25

C

– 2TCL – 15

F

– 2TCL – 15

F

WR
Address hold after RD

CC 35 + t

27

– 2TCL – 15

F

,

t

WR
ALE falling edge to CS
CS

low to Valid Data In t

hold after RD, WR t

CS

ALE fall. edge to RdCS

(with RW delay)

WrCS
ALE fall. edge to RdCS

CC – 5 – t

38

SR – 55

39

CC 60 + t

40

,

t

CC 20 + t

42

,

t

CC – 5 + t

43

10 – t

A

F

A

A

A

+ t

+ 2t

C

– 3TCL – 15

– TCL – 5

–– 5

t

WrCS (no RW delay)

,

t

Address float after RdCS

CC–0–0ns

44

WrCS (with RW delay)

Variable CPU Clock

1/2TCL = 1 to 20 MHz

– 2TCL – 20

– 3TCL – 20

– 3TCL – 20

C

– 4TCL – 30

C

– 2TCL – 15

+ t

C

+ t

F

+ t

F

+ t

F

– 5 – t

A

– 3TCL – 20

A

+ t

F

t

+

A

+ t

A

Unit

ns

+ t

C

ns

+ t

C

ns

+ tA + t

C

ns

+ 2tA + t

C

ns

+ t

F

–ns

–ns

–ns

–ns

10 – t

A

ns
ns

+ t

+ 2t

C

A

–ns

–ns

–ns

,

t

Address float after RdCS

CC – 25 – TCL ns

45

WrCS (no RW delay)

to Valid Data In

RdCS

t

SR – 25 + t

46

(with RW delay)

Semiconductor Group 47

– 2TCL – 25

C

+ t

ns

C

C167SR

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

RdCS

to Valid Data In

t

SR – 50 + t

47

C

(no RW delay)

, WrCS Low Time

RdCS

t

48

CC 40 + t

– 2TCL – 10

C

(with RW delay)

, WrCS Low Time

RdCS

t

49

CC 65 + t

– 3TCL – 10

C

(no RW delay)

t

Data valid to WrCS

Data hold after RdCS
Data float after RdCS

Address hold after

, WrCS

RdCS
Data hold after WrCS

CC 35 + t

50

t

SR0–0–ns

51

t

SR – 30 + t

52

t

CC 30 + t

54

t

CC 30 + t

56

– 2TCL – 15

C

F

– 2TCL – 20

F

– 2TCL – 20

F

Variable CPU Clock

1/2TCL = 1 to 20 MHz

– 3TCL – 25

+ t

C

–ns

+ t

C

–ns

+ t

C

–ns

+ t

C

– 2TCL – 20

+ t

F

–ns

+ t

F

–ns

+ t

F

Unit

ns

ns

Semiconductor Group 48

C167SR

ALE

CSx

A23-A16

(A15-A8)

BHE

Read Cycle

BUS

RD

t

5

t

6

t

38

Address

t

8

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

7

t

54

t

19

t

18

Data In

t

10

t

14

RdCSx

Write Cycle

BUS

WR,

WRL, WRH

WrCSx

t

t

t

42

12

44

t

46

t

48

t

51

t

52

t

23

Data OutAddress

t

t

t

8

t

42

10

t

44

t

22

t

12

t

50

t

48

56

Figure 14-1
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE

Semiconductor Group 49

C167SR

ALE

CSx

A23-A16

(A15-A8)

BHE

Read Cycle

BUS

RD

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

t

7

t

54

t

19

t

18

Data InAddress

t

t

8

10

t

14

RdCSx

Write Cycle

BUS

WR,

WRL, WRH

WrCSx

t

t

t

42

12

44

t

46

t

48

t

51

t

52

t

23

Data OutAddress

t

t

t

8

t

42

10

t

44

t

22

t

12

t

50

t

48

56

Figure 14-2
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE

Semiconductor Group 50

C167SR

ALE

CSx

A23-A16

(A15-A8)

BHE

Read Cycle

BUS

RD

t

5

t

38

t

16

t

39

t

17

Address

t

6

t

7

Address Data In

t

9

t

11

t

15

t

25

t

40

t

27

t

54

t

19

t

18

RdCSx

Write Cycle

BUS

WR,

WRL, WRH

WrCSx

t

t

43

t

45

13

t

47

t

49

t

51

t

52

t

23

Data OutAddress

t

t

9

t

43

t

11

t

45

t

22

t

13

t

50

t

49

56

Figure 14-3
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE

Semiconductor Group 51

C167SR

ALE

CSx

A23-A16

(A15-A8)

BHE

Read Cycle

BUS

RD

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

t

7

t

54

t

19

t

18

Data InAddress

t

9

t

11

t

15

RdCSx

Write Cycle

BUS

WR,

WRL, WRH

WrCSx

t

13

t

43

t

45

t

47

t

49

t

51

t

52

t

23

Data OutAddress

t

56

t

9

t

43

t

11

t

45

t

22

t

13

t

50

t

49

Figure 14-4
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE

Semiconductor Group 52

C167SR

AC Characteristics
Demultiplexed Bus

V

= 5 V ± 10 %; VSS = 0 V

CC

T

= 0 to + 70 ˚C for SAB-C167SR-LM

A

T

= – 40 to + 85 ˚C for SAF-C167SR-LM

A

T

= – 40 to + 125 ˚C for SAK-C167SR-LM

A

C

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

L

C

(for Port 6, CS) = 100 pF

L

ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

ALE high time t
Address setup to ALE
ALE falling edge to RD

,

5

t

6

t

8

CC 15 + t
CC

10 +

CC

15 +

– TCL – 10 + tA–ns

A

t
t

– TCL – 15 + tA–ns

A

– TCL – 10

A

WR (with RW-delay)

t

ALE falling edge to RD

,

CC

9

– 10 +

t

– – 10

A

WR (no RW-delay)

, WR low time

RD

t

12

CC 40 + t

– 2TCL – 10

C

(with RW-delay)

, WR low time

RD

t

13

CC 65 + t

– 3TCL – 10

C

(no RW-delay)

to valid data in

RD

t

SR – 30 + t

14

C

(with RW-delay)

to valid data in

RD

t

SR – 55 + t

15

C

(no RW-delay)

t

ALE low to valid data in

SR – 55

16

+ tA + t

t

Address to valid data in

Data hold after RD

SR – 70

17

2t

+ t

+

A

t

SR0–0–ns

18

rising edge

Variable CPU Clock

1/2TCL = 1 to 20 MHz

+ t

A

+ t

A

+ t

C

+ t

C

– 2TCL – 20

– 3TCL – 20

– 3TCL – 20

C

– 4TCL – 30

C

Unit

–ns

–ns

–ns

–ns

ns

+ t

C

ns

+ t

C

ns

+ tA + t

C

ns

2t

+ t

+

A

C

Data float after RD

rising

t

SR – 35 + t

20

edge (with RW-delay 1))
Data float after RD

rising

t

SR – 15 + t

21

edge (no RW-delay 1))

t

Data valid to WR

Data hold after WR

22

t

24

CC 25 + t

CC 15 + t

C

F

Semiconductor Group 53

– 2TCL – 15

F

– TCL – 10

F

– 2TCL – 25

+ t

C

+ 2tA + tF

+ 2tA + tF
–ns

ns

1)

ns

1)

– TCL – 10 + tF–ns

C167SR

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

,

t

ALE rising edge after RD

CC – 10 + tF– – 10

26

WR
Address hold after RD

28

CC 0 + t

F

–0

,

t

WR
ALE falling edge to CS
CS

low to Valid Data In t

hold after RD, WR t

CS

ALE falling edge to

, WrCS (with RW-

RdCS

CC – 5 – t

38

SR – 55

39

CC 10 + t

41

t

CC 20 + t

42

10 – t

A

F

A

A

+ t

+ 2t

C

– TCL – 15

– TCL – 5

t

delay)
ALE falling edge to

RdCS

, WrCS (no RW-

t

CC – 5 + t

43

–– 5

A

delay)

Variable CPU Clock

1/2TCL = 1 to 20 MHz

– ns

+ t

F

–ns

+ t

F

– 5 – t

A

10 – t

– 3TCL – 20

A

+ t
–ns

+ t

F

–ns

+ t

A

–ns

+ t

A

+ 2t

C

Unit

A

ns
ns

A

RdCS

to Valid Data In

(with RW-delay)

to Valid Data In

RdCS
(no RW-delay)

, WrCS Low Time

RdCS
(with RW-delay)

, WrCS Low Time

RdCS
(no RW-delay)

Data valid to WrCS

Data hold after RdCS
Data float after RdCS

(with RW-delay)
Data float after RdCS

(no RW-delay)
Address hold after

, WrCS

RdCS
Data hold after WrCS

t

SR – 25 + t

46

t

SR – 50 + t

47

t

CC 40 + t

48

t

CC 65 + t

49

t

CC 35 + t

50

t

SR0–0–ns

51

t

SR – 30 + t

53

t

SR – 5 + t

68

t

CC – 10 + tF– – 10

55

t

CC 10 + t

57

– 2TCL – 10

C

– 3TCL – 10

C

– 2TCL – 15

C

F

– TCL – 15

F

– 2TCL – 25

C

– 3TCL – 25

C

+ t

C

+ t

C

+ t

C

– 2TCL – 20

F

– TCL – 20

+ t

F

+ t

F

ns

+ t

C

ns

+ t

C

–ns

–ns

–ns

ns

+ t

F

ns

+ t

F

–ns

–ns

1)

RW-delay and tA refer to the next following bus cycle.

Semiconductor Group 54

C167SR

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

20

t

18

Data In

t

8

t

14

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

WrCSx

t

12

t

42

t

46

t

48

t

51

t

53

t

24

Data Out

t

57

t

8

t

42

t

22

t

12

t

50

t

48

Figure 15-1
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE

Semiconductor Group 55

C167SR

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

20

t

18

Data In

t

8

t

14

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

WrCSx

t

12

t

42

t

46

t

48

t

51

t

53

t

24

Data Out

t

57

t

8

t

42

t

22

t

12

t

50

t

48

Figure 15-2
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE

Semiconductor Group 56

C167SR

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

21

t

18

Data In

t

9

t

15

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

WrCSx

t

t

43

13

t

47

t

49

t

51

t

68

t

24

Data Out

t

t

9

t

43

t

22

t

13

t

50

t

49

57

Figure 15-3
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE

Semiconductor Group 57

C167SR

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

21

t

18

Data In

t

9

t

15

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

WrCSx

t

13

t

43

t

47

t

49

t

51

t

68

t

24

Data Out

t

57

t

9

t

43

t

22

t

13

t

50

t

49

Figure 15-4
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE

Semiconductor Group 58

AC Characteristics
CLKOUT and READY

V

= 5 V ± 10 %; VSS = 0 V

CC

T

= 0 to + 70 ˚C for SAB-C167SR-LM

A

T

= – 40 to + 85 ˚C for SAF-C167SR-LM

A

T

= – 40 to + 125 ˚C for SAK-C167SR-LM

A

C

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

L

C

(for Port 6, CS) = 100 pF

L

C167SR

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

CLKOUT cycle time t
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to

CC 50 50 2TCL 2TCL ns

29

t

CC

30

t

31

t

32

t

33

t

34

20 – TCL – 5 – ns

CC

15 – TCL – 10 – ns
CC–5–5ns
CC–5–5ns
CC 0 + t

A

10 + t

A

ALE falling edge

t

Synchronous READY

SR 15 – 15 – ns

35

setup time to CLKOUT

t

Synchronous READY

SR0–0–ns

36

hold time after CLKOUT

t

Asynchronous READY

SR 65 – 2TCL + 15 – ns

37

low time

t

SR

Asynchronous READY

1)

setup time

58

15 – 15 – ns

Variable CPU Clock

1/2TCL = 1 to 20 MHz

0 + t

A

10 + t

Unit

A

ns

t

SR

Asynchronous READY

1)

hold time
Async. READY

after RD
(Demultiplexed Bus)

Notes

1)

These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2)

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY
The 2t

hold time

, WR high

2)

refer to the next following bus cycle.

A

59

t

60

0–0–ns

SR

00

.

2t

+ t

+

A

2)

0 TCL – 25

F

2t

+ t

+

A

2)

F

Semiconductor Group 59

ns

C167SR

Running cycle

1)

READY

waitstate

MUX/Tristate

6)

CLKOUT

ALE

Command

RD, WR

Sync

READY

Async

READY

t

32

t

30

t

34

t

58

t

59

3)

t

33

t

t

31

2)

t

35

3)

t

58

3)

t

37

5)

29

7)

t

36

t

59

t

35

t

36

3)

4)

t

60

see 6)

Figure 16
CLKOUT and READY

Notes

1)

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

2)

The leading edge of the respective command depends on RW-delay.

3)

READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY

4)

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR

5)

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(eg. because CLKOUT is not enabled), it must fulfill
if READY

6)

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.

7)

The next external bus cycle may start here.

sampled LOW at this sampling point terminates the currently running bus cycle.

).

t

in order to be safely synchronized. This is guaranteed,

37

is removed in reponse to the command (see Note 4)).

Semiconductor Group 60

AC Characteristics
External Bus Arbitration

V

= 5 V ± 10 %; VSS = 0 V

CC

T

= 0 to + 70 ˚C for SAB-C167SR-LM

A

T

= – 40 to + 85 ˚C for SAF-C167SR-LM

A

T

= – 40 to + 125 ˚C for SAK-C167SR-LM

A

C

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

L

C

(for Port 6, CS) = 100 pF

L

C167SR

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

HOLD input setup time

t

SR 20 – 20 – ns

61

to CLKOUT
CLKOUT to HLDA

high

t

CC – 20 – 20 ns

62

or BREQ low delay
CLKOUT to HLDA

low

t

CC – 20 – 20 ns

63

or BREQ high delay

release t

CSx
CSx

drive
Other signals release
Other signals drive

CC – 20 – 20 ns

64

t

CC

65

t

66

t

67

– 5 25 – 5 25 ns

CC

– 20 – 20 ns

CC

– 5 25 – 5 25 ns

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

Semiconductor Group 61

CLKOUT

HOLD

HLDA

C167SR

t

61

t

63

1)

t

62

BREQ

t

64

2)

3)

CSx

(On P6.x)

t

66

Other

Signals

1)

Figure 17
External Bu

Notes

1)

The C167SR will complete the currently running bus cycle before granting bus access.

2)

This is the first possibility for BREQ to get active.

3)

The CS outputs will be resistive high (pullup) after

s Arbitration, Releasing the Bus

t

.

64

Semiconductor Group 62

C167SR

CLKOUT

HOLD

HLDA

BREQ

CSx

(On P6.x)

2)

t

61

t

62

t

62

t

62

1)

t

63

t

65

t

67

Other

Signals

Figure 18
External Bus Arbitration, (Regaining the Bus)

Notes

1)

This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ
Please note that HOLD

2)

The next C167SR driven bus cycle may start here.

is activated earlier, the regain-sequence is initiated by HOLD going high.

may also be deactivated without the C167SR requesting the bus.

Semiconductor Group 63