Datasheet SAB-C165-LM, SAB-C165-RM, SAF-C165-LM Datasheet (Siemens)

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Page 1

Data Sheet 09.94

Microcomputer Components

C165

16-Bit CMOS Single-Chip Microcontroller

Page 2

C16x-Family of High-Performance CMOS 16-Bit Microcontrollers

Preliminary C165 16-Bit Microcontroller

High Performance 16-bit CPU with 4-Stage Pipeline

●

● 100 ns Instruction Cycle Time at 20-MHz CPU Clock

500 ns Multiplication (16 × 16 bits), 1 µs Division (32 / 16 bit)

●

Enhanced Boolean Bit Manipulation Facilities

●

Additional Instructions to Support HLL and Operating Systems

●

Single-Cycle Context Switching Support

●

Up to 16 MBytes Linear Address Space for Code and Data

●

● 2 KBytes On-Chip RAM

4 KBytes On-Chip ROM (RM types only)

●

Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus

●

Multiplexed or Demultiplexed External Address/Data Buses

●

Five Programmable Chip-Select Signals

●

Hold- and Hold-Acknowledge Bus Arbitration Support

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● 1024 Bytes On-Chip Special Function Register Area

Idle and Power Down Modes

●

8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 50 ns

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Two Multi-Functional General Purpose Timer Units with 5 Timers

●

Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

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● Programmable Watchdog Timer

Up to 77 General Purpose I/O Lines

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Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader

●

100-Pin MQFP Package (EIAJ)

●

● 100-Pin TQFP Package (Thin QFP)

C165

09.94 Data Sheet Addendum – Attention

The C165 is offered in two different packages: P-MQFP-100: rectangular package

P-TQFP-100: square package. For the pin configurations please refer to page 3 (P-MQFP-100) and page 8 (P-TQFP-100) of the

09.94 C165 Data Sheet. Please note that the table “Pin Definition and Functions” on pages 9 through 12 lists the pin numbers for the MQFP package only.

The pin numbers for the TQFP package are different and should be taken from the pin configuration on page 3.

Semiconductor Group 1 09.94

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C165

Introduction

The C165 is a new derivative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities.

C165

Figure 1 Logic Symbol

Ordering Information Type Ordering Code Package Function

SAB-C165-RM Q67121-D... P-MQFP-100-2 16-bit microcontroller with

2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 ˚C

SAB-C165-LM Q67121-C862 P-MQFP-100-2 16-bit microcontroller with

2 KByte RAM Temperature range 0 to +70 ˚C

SAF-C165-LM Q67121-C923 P-MQFP-100-2 16-bit microcontroller with

2 KByte RAM Temperature range -40 to +85 ˚C

Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product

after verification of the respective ROM code.

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C165

Ordering Information Type Ordering Code Package Function

SAB-C165-RF Q67121-D... P-TQFP-100-3 16-bit microcontroller with

2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 ˚C

SAB-C165-LF Q67121-C941 P-TQFP-100-3 16-bit microcontroller with

2 KByte RAM Temperature range 0 to +70 ˚C

Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product

after verification of the respective ROM code.

Pin Configuration TQFP Package

(top view)

C165

Figure 2

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Pin Configuration MQFP Package

(top view)

C165

Figure 3

C165

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Pin Definitions and Functions

C165

Symbol Pin

No.

P5.10 – P5.15

XTAL1

XTAL2

P3.0 – P3.13, P3.15

100 1 - 5 100 1 2 3 4 5

10 – 23, 24

11 12 13 14 15

16 17

18 19 20 21 22

23 24

Input (I) Output (O)

I I I I I I I I

I/O I/O I/O

O I O I I

I I

I/O I/O O I/O O O I/O O

Function

Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input

XTAL1: Input to the oscillator amplifier and input to the

internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The following Port 3 pins also serve for alternate functions: P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 T×D0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE

WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock)

Ext. Memory High Byte Enable Signal,

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Pin Definitions and Functions (cont’d)

C165

Symbol Pin

No.

P4.0 – P4.7

WRL

READY

25 - 28, 31 - 34

25 ... 34

35 O External Memory Read Strobe. RD is activated for every

36 O External Memory Write Strobe. In WR-mode this pin is

37 I Ready Input. When the Ready function is enabled, a high

Input (I) Output (O)

I/O

O ... O

Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line

... ... ...

P4.7 A23 Most Significant Segment Addr. Line

external instruction or data read access.

activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level.

ALE 38 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the multiplexed bus modes.

39 I External Access Enable pin. A low level at this pin during and

after Reset forces the C165 to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. The C165 must have this pin tied to ‘0’.

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Pin Definitions and Functions (cont’d)

C165

Symbol Pin

No.

PORT0: P0L.0 – P0L.7, P0H.0 P0H.7

43 – 50 53 – 60

PORT1: P1L.0 – P1L.7, P1H.0 P1H.7

61 68 69 - 70, 73 - 78

Input (I)

Function

Output (O)

I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 - A15 AD8 - AD15

I/O PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.

RSTIN

RSTOUT

NMI

81 I Reset Input with Schmitt-Trigger characteristics. A low level at

this pin for a specified duration while the oscillator is running resets the C165. An internal pullup resistor permits power-on

reset using only a capacitor connected to

82 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed.

83 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C165 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally.

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Pin Definitions and Functions (cont’d)

C165

Symbol Pin

No.

P6.0 – P6.7

84 91

84 ... 88 89 90 91

P2.8 – P2.15

92 99

92 ... 99

Input (I) Output (O)

I/O

O ... O I O O

I/O

I ... I

Function

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The following Port 6 pins also serve for alternate functions: P6.0 CS0 Chip Select 0 Output

... ... ...

P6.4 CS4 Chip Select 4 Output P6.5 HOLD External Master Hold Request Input P6.6 HLDA Hold Acknowledge Output P6.7 BREQ Bus Request Output

Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The following Port 2 pins also serve for alternate functions: P2.8 EX0IN Fast External Interrupt 0 Input

... ... ...

P2.15 EX7IN Fast External Interrupt 7 Input

42 - Flash programming voltage. This pin accepts the

programming voltage for flash versions of the C165. Note: This pin is not connected (NC) on non-flash versions.

9, 30, 40, 51, 71, 80

6, 29,

- Digital Supply Voltage: + 5 V during normal operation and idle mode. ≥ 2.5 V during power down mode

- Digital Ground.

41, 52, 72, 79

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C165

Functional Description

The architecture of the C165 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C165.

Note: All time specifications refer to a CPU clock of 20 MHz

(see definition in the AC Characteristics section).

Figure 4 Block Diagram

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C165

Memory Organization

The memory space of the C165 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable.

The C165 is prepared to incorporate on-chip mask-programmable ROM for code or constant data. Currently no ROM is integrated.

2 KBytes of on-chip RAM are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C165 family.

In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on

PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-

State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Up to 5 external CS in order to save external glue logic. Access to very slow memories is supported via a particular ‘Ready’ function. A HOLD/HLDA protocol is available for bus arbitration.

signals can be generated

For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.

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C165

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C165’s instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

Figure 5 CPU Block Diagram

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C165

The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C165 instruction set which includes the following instruction classes:

– Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

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C165

Interrupt System

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C165 is capable of reacting very fast to the occurrence of non-deterministic events.

The architecture of the C165 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C165 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

The following table shows all of the possible C165 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

Note: Four nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from

integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit. Also the three listed Software Nodes can be used for this purpose.

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C165

Source of Interrupt or PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

External Interrupt 0 CC8IR CC8IE CC8INT 00’0060 External Interrupt 1 CC9IR CC9IE CC9INT 00’0064 External Interrupt 2 CC10IR CC10IE CC10INT 00’0068 External Interrupt 3 CC11IR CC11IE CC11INT 00’006C External Interrupt 4 CC12IR CC12IE CC12INT 00’0070 External Interrupt 5 CC13IR CC13IE CC13INT 00’0074 External Interrupt 6 CC14IR CC14IE CC14INT 00’0078 External Interrupt 7 CC15IR CC15IE CC15INT 00’007C GPT1 Timer 2 T2IR T2IE T2INT 00’0088 GPT1 Timer 3 T3IR T3IE T3INT 00’008C GPT1 Timer 4 T4IR T4IE T4INT 00’0090 GPT2 Timer 5 T5IR T5IE T5INT 00’0094 GPT2 Timer 6 T6IR T6IE T6INT 00’0098 GPT2 CAPREL Register CRIR CRIE CRINT 00’009C ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8 ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C ASC0 Receive S0RIR S0RIE S0RINT 00’00AC ASC0 Error S0EIR S0EIE S0EINT 00’00B0 SSC Transmit SCTIR SCTIE SCTINT 00’00B4 SSC Receive SCRIR SCRIE SCRINT 00’00B8 SSC Error SCEIR SCEIE SCEINT 00’00BC X-Peripheral Node 0 XP0IR XP0IE XP0INT 00’0100 X-Peripheral Node 1 XP1IR XP1IE XP1INT 00’0104 X-Peripheral Node 2 XP2IR XP2IE XP2INT 00’0108 X-Peripheral Node 3 XP3IR XP3IE XP3INT 00’010C Software Node CC29IR CC29IE CC29INT 00’0110 Software Node CC30IR CC30IE CC30INT 00’0114 Software Node CC31IR CC31IE CC31INT 00’0118

Trap Number

H H H

H H H H

1C 1D 1E 1F 22 23 24 25 26 27 2A 47 2B 2C 2D 2E 2F 40 41 42 43 44 45 46

H H H

H H H H H H H H

H H

H H H H H H H H H

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C165

The C165 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during runtime:

Exception Condition Trap

Flag

Trap Vector

Vector Location

Reset Functions:

Hardware Reset Software Reset Watchdog Timer Overflow

RESET RESET RESET

00’0000 00’0000 00’0000

Class A Hardware Traps:

Non-Maskable Interrupt Stack Overflow Stack Underflow

NMI STKOF STKUF

NMITRAP STOTRAP STUTRAP

00’0008 00’0010 00’0018

Class B Hardware Traps:

Undefined Opcode Protected Instruction

UNDOPC PRTFLT

BTRAP BTRAP

00’0028

00’0028 Fault Illegal Word Operand

ILLOPA

BTRAP

00’0028 Access Illegal Instruction Access Illegal External Bus

ILLINA ILLBUS

BTRAP BTRAP

00’0028

00’0028 Access

Reserved [2C Software Traps

TRAP Instruction

Any

[00’0000

00’01FCH]

in steps

of 4

Trap Number

H H H

H H

– 3CH] [0BH – 0FH]

00 00 00

02 04 06

0A 0A

H H H

H H

Any

–

[00H – 7FH]

Trap Priority

III III III

II II II

I I

Current CPU Priority

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C165

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20-MHz CPU clock).

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking.

Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer overflow/underflow. The state of these latches may be output on port pins (TxOUT) e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.

With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.

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C165

Figure 6 Block Diagram of GPT1

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C165

Figure 7 Block Diagram of GPT2

Parallel Ports

The C165 provides up to 77 I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for timer control signals. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.

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C165

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 KBaud and half-duplex synchronous communication up to 5 Mbaud (2.5 Mbaud on the ASC0) @ 20-MHz system clock.

Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel.

In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0 always shifts the LSB first. A loop back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT in order to allow external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 µs and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz).

pin low

Semiconductor Group 19

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C165

Instruction Set Summary

The table below lists the instructions of the C165 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C16x Family Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Instruction Set Summary Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2

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C165

Instruction Set Summary (cont’d) Mnemonic Description Bytes

MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ Move byte operand to word operand. with zero extension 2 / 4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call

absolute subroutine TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update

register with word operand RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct

word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode

(supposes NMI SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4

-pin being low)

EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2

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C165

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C165 in alphabetical order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Special Function Registers Overview Name Physical

Address

ADDRSEL1 FE18 ADDRSEL2 FE1A ADDRSEL3 FE1C ADDRSEL4 FE1E BUSCON0 b FF0C BUSCON1 b FF14 BUSCON2 b FF16 BUSCON3 b FF18 BUSCON4 b FF1A CAPREL FE4A CC8IC b FF88 CC9IC b FF8A CC10IC b FF8C

H H H

H H H H H

H H H

8-Bit Address

Description Reset

Value

Address Select Register 1 0000 Address Select Register 2 0000 Address Select Register 3 0000 Address Select Register 4 0000 Bus Configuration Register 0 0XX0 Bus Configuration Register 1 0000 Bus Configuration Register 2 0000 Bus Configuration Register 3 0000 Bus Configuration Register 4 0000 GPT2 Capture/Reload Register 0000 EX0IN Interrupt Control Register 0000 EX1IN Interrupt Control Register 0000 EX2IN Interrupt Control Register 0000

H H H H

H H H H H H H H H

CC11IC b FF8E CC12IC b FF90 CC13IC b FF92 CC14IC b FF94 CC15IC b FF96 CC29IC b F184HE C2 CC30IC b F18CHE C6 CC31IC b F194HE CA CP FE10

H H H H H

C8 C9 CA CB

H H H

EX3IN Interrupt Control Register 0000 EX4IN Interrupt Control Register 0000 EX5IN Interrupt Control Register 0000 EX6IN Interrupt Control Register 0000 EX7IN Interrupt Control Register 0000 Software Node Interrupt Control Register 0000 Software Node Interrupt Control Register 0000 Software Node Interrupt Control Register 0000 CPU Context Pointer Register FC00

Semiconductor Group 22

H H H H H H H H

Page 24

Special Function Registers Overview (cont’d)

C165

Name Physical

Address

CRIC b FF6A CSP FE08

H H

8-Bit Address

B5 04

DP0L b F100HE 80 DP0H b F102HE 81 DP1L b F104HE 82 DP1H b F106HE 83 DP2 b FFC2 DP3 b FFC6 DP4 b FFCA DP6 b FFCE DPP0 FE00 DPP1 FE02 DPP2 FE04

Description Reset

Value

H H H H H H H H H H H H H

GPT2 CAPREL Interrupt Control Register 0000 CPU Code Segment Pointer Register (read only) 0000 P0L Direction Control Register 00 P0H Direction Control Register 00 P1L Direction Control Register 00 P1H Direction Control Register 00

H H H H

Port 2 Direction Control Register 0000 Port 3 Direction Control Register 0000 Port 4 Direction Control Register 00 Port 6 Direction Control Register 00

H H

CPU Data Page Pointer 0 Register (10 bits) 0000 CPU Data Page Pointer 1 Register (10 bits) 0001 CPU Data Page Pointer 2 Register (10 bits) 0002

H H

H H H

DPP3 FE06

EXICON b F1C0HE E0 MDC b FF0E MDH FE0C MDL FE0E

ODP2 b F1C2HE E1 ODP3 b F1C6HE E3 ODP6 b F1CEHE E7 ONES FF1E P0L b FF00 P0H b FF02 P1L b FF04 P1H b FF06 P2 b FFC0

H H H H

80 81 82 83 E0

H H H H H H H H H H H H H H

CPU Data Page Pointer 3 Register (10 bits) 0003 External Interrupt Control Register 0000 CPU Multiply Divide Control Register 0000 CPU Multiply Divide Register – High Word 0000 CPU Multiply Divide Register – Low Word 0000 Port 2 Open Drain Control Register 0000 Port 3 Open Drain Control Register 0000 Port 6 Open Drain Control Register 00

Constant Value 1’s Register (read only) FFFF Port 0 Low Register (Lower half of PORT0) 00 Port 0 High Register (Upper half of PORT0) 00 Port 1 Low Register (Lower half of PORT1) 00 Port 1 High Register (Upper half of PORT1) 00

H H H H

Port 2 Register 0000

H H H H H H H

P3 b FFC4 P4 b FFC8

H H

Port 3 Register 0000 Port 4 Register (8 bits) 00

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Special Function Registers Overview (cont’d)

C165

Name Physical

Address

P5 b FFA2 P6 b FFCC PECC0 FEC0 PECC1 FEC2 PECC2 FEC4 PECC3 FEC6 PECC4 FEC8 PECC5 FECA PECC6 FECC PECC7 FECE PSW b FF10

H H H H H H

8-Bit Address

D1 E6 60 61 62 63 64 65 66 67 88

RP0H b F108HE 84 S0BG FEB4

Description Reset

Value

H H H H H H H H H H H H H

Port 5 Register (read only) XXXX Port 6 Register (8 bits) 00

PEC Channel 0 Control Register 0000 PEC Channel 1 Control Register 0000 PEC Channel 2 Control Register 0000 PEC Channel 3 Control Register 0000 PEC Channel 4 Control Register 0000 PEC Channel 5 Control Register 0000 PEC Channel 6 Control Register 0000 PEC Channel 7 Control Register 0000 CPU Program Status Word 0000 System Startup Configuration Register (Rd. only) XX Serial Channel 0 Baud Rate Generator Reload

0000

H H H H H H H H H

S0CON b FFB0 S0EIC b FF70 S0RBUF FEB2

S0RIC b FF6E

B8 59

S0TBIC b F19CHE CE

S0TBUF FEB0

S0TIC b FF6C

SP FE12

SSCBR F0B4HE 5A SSCCON b FFB2 SSCEIC b FF76

H H H

Serial Channel 0 Control Register 0000 Serial Channel 0 Error Interrupt Control Register 0000 Serial Channel 0 Receive Buffer Register

H H

(read only)

Serial Channel 0 Receive Interrupt Control

0000

Serial Channel 0 Transmit Buffer Interrupt Control

0000

Serial Channel 0 Transmit Buffer Register

(write only)

Serial Channel 0 Transmit Interrupt Control

0000

H H

CPU System Stack Pointer Register FC00 SSC Baudrate Register 0000 SSC Control Register 0000 SSC Error Interrupt Control Register 0000

H H H H

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Special Function Registers Overview (cont’d)

C165

Name Physical

Address

8-Bit Address

SSCRB F0B2HE 59 SSCRIC b FF74

SSCTB F0B0HE 58 SSCTIC b FF72 STKOV FE14 STKUN FE16 SYSCON b FF12 T2 FE40 T2CON b FF40 T2IC b FF60 T3 FE42 T3CON b FF42 T3IC b FF62

H H

B9 0A

89 20

A0 B0 21

A1 B1

Description Reset

Value

H H H H H H H H H H H H

SSC Receive Buffer (read only) XXXX SSC Receive Interrupt Control Register 0000 SSC Transmit Buffer (write only) 0000 SSC Transmit Interrupt Control Register 0000 CPU Stack Overflow Pointer Register FA00 CPU Stack Underflow Pointer Register FC00

H H H H

H H

CPU System Configuration Register 0xx0H*) GPT1 Timer 2 Register 0000 GPT1 Timer 2 Control Register 0000 GPT1 Timer 2 Interrupt Control Register 0000 GPT1 Timer 3 Register 0000 GPT1 Timer 3 Control Register 0000 GPT1 Timer 3 Interrupt Control Register 0000

H H H H H H

T4 FE44 T4CON b FF44 T4IC b FF64 T5 FE46 T5CON b FF46 T5IC b FF66 T6 FE48 T6CON b FF48 T6IC b FF68 TFR b FFAC WDT FEAE WDTCON FFAE

H H

A2 B2 23

A3 B3 24

A4 B4 D6

XP0IC b F186HE C3 XP1IC b F18EHE C7

H H H H H H H H H

H H H

GPT1 Timer 4 Register 0000 GPT1 Timer 4 Control Register 0000 GPT1 Timer 4 Interrupt Control Register 0000 GPT2 Timer 5 Register 0000 GPT2 Timer 5 Control Register 0000 GPT2 Timer 5 Interrupt Control Register 0000 GPT2 Timer 6 Register 0000 GPT2 Timer 6 Control Register 0000 GPT2 Timer 6 Interrupt Control Register 0000 Trap Flag Register 0000 Watchdog Timer Register (read only) 0000 Watchdog Timer Control Register 0000 X-Peripheral 0 Interrupt Control Register 0000 X-Peripheral 1 Interrupt Control Register 0000

H H H H H H H H H H H H H H

XP2IC b F196HE CB

X-Peripheral 2 Interrupt Control Register 0000

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Special Function Registers Overview (cont’d)

C165

Name Physical

Address

XP3IC b F19EHE CF ZEROS b FF1C

8-Bit Address

Description Reset

Value

X-Peripheral 3 Interrupt Control Register 0000 Constant Value 0’s Register (read only) 0000

H H

*) The system configuration is selected during reset. Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from

integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.

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C165

Absolute Maximum Ratings

Ambient temperature under bias (TA):

SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF .....................................0 to + 70 ˚C

SAF-C165-LM............................................................................................................ – 40 to + 85 ˚C

Storage temperature (TST) ....................................................................................... – 65 to + 150 ˚C

Voltage on VCC pins with respect to ground (VSS) ...................................................... –0.5 to + 6.5 V

Voltage on any pin with respect to ground (VSS).................................................– 0.5 to VCC + 0.5 V

Input current on any pin during overload condition.................................................. – 10 to + 10 mA

Absolute sum of all input currents during overload condition ..............................................|100 mA|

Power dissipation..................................................................................................................... 1.5 W

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings.

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C165 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics): The logic of the C165 will provide signals with the respective timing characteristics.

SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C165.

DC Characteristics

= 5 V ± 10 %; VSS = 0 V; f

= 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF

= -40 to +85 ˚C for SAF-C165-LM

= 20 MHz; Reset active

CPU

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltage

SR – 0.5 0.2 V

V–

– 0.1

Input high voltage (all except RSTIN

and XTAL1) Input high voltage RSTIN Input high voltage XTAL1

IH1

IH2

SR 0.2 V

+ 0.9 SR 0.6 V SR 0.7 V

Semiconductor Group 27

+ 0.5 V –

Page 29

C165

Parameter Symbol Limit Values Unit Test Condition

min. max.

Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT)

Output low voltage (all other outputs)

Output high voltage (PORT0, PORT1, Port 4, ALE, RD

WR, BHE, CLKOUT, RSTOUT) Output high voltage

(all other outputs) Input leakage current (Port 5) Input leakage current (all other) I RSTIN pullup resistor R Read/Write inactive current Read/Write active current ALE inactive current ALE active current

Port 6 inactive current Port 6 active current

PORT0 configuration current

XTAL1 input current I

Pin capacitance (digital inputs/outputs)

Power supply current

Idle mode supply current I

Power-down mode supply current I

CC – 0.45 V IOL = 2.4 mA

CC – 0.45 V I

OL1

CC 0.9 V

2.4

CC 0.9 V

OH1

2.4

CC – ±200 nA 0 V < VIN < V

OZ1

CC – ±500 nA 0 V < VIN < V

OZ2

CC 50 150 kΩ –

RST

RWH

RWL

ALEL

ALEH

P6H

P6L

P0H

P0L

– -40 µA V

-500 – µA V

–40µAV

500 – µA V

– -40 µA V

-500 – µA V

– -10 µA VIN = V

-100 – µA VIN = V CC – ±20 µA 0 V < VIN < V CC – 10 pF f = 1 MHz

–VI

–V

I I

– 10 +

4 * f

CPU

–2 +

1.2 * f

CPU

mA RSTIN = V

– 100 µA VCC = 5.5 V

= 1.6 mA

OL1

= – 500 µA

= – 2.4 mA

= – 250 µA

= – 1.6 mA

= 2.4 V

OUT

= V

OUT

= 25 ˚C

CPU

OLmax

= V

OLmax

= 2.4 V = 2.4 V = V

OL1max

IHmin

ILmax

in [MHz]

IL2

IH1

Semiconductor Group 28

Page 30

Notes

This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS

Not 100% tested, guaranteed by design characterization.

The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at V

or VIH.

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at V

output and the open drain function is not enabled.

and 20 MHz CPU clock with all outputs disconnected and all inputs at

CCmax

– 0.1 V to VCC, V

= 0 V, all outputs (including pins configured as outputs) disconnected.

REF

C165

Figure 8 Supply/Idle Current as a Function of Operating Frequency

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Testing Waveforms

AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at V

min for a logic ‘1’ and VIL max for a logic ‘0’.

C165

Figure 9 Input Output Waveforms

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA).

Figure 10 Float Waveforms

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AC Characteristics External Clock Drive XTAL1

= 5 V ± 10 %; VSS = 0 V

= 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF

= -40 to +85 ˚C for SAF-C165-LM

C165

Parameter Symbol Max. CPU Clock

= 20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

min. max. min. max.

Oscillator period TCL SR 25 25 25 500 ns

High time Low time Rise time Fall time

SR6–6–ns

SR–5–5ns

Figure 11 External Clock Drive XTAL1

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed.

Description Symbol Values

ALE Extension t Memory Cycle Time Waitstates Memory Tristate Time

TCL * <ALECTL> 2TCL * (15 - <MCTC>) 2TCL * (1 - <MTTC>)

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AC Characteristics (cont’d) Multiplexed Bus

= 5 V ± 10 %; VSS = 0 V

= 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF

= -40 to +85 ˚C for SAF-C165-LM

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

(for Port 6, CS) = 100 pF

ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)

C165

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

ALE high time t Address setup to ALE Address hold after ALE ALE falling edge to RD

CC 15 + t CC 10 + t CC 15 + t CC 15 + t

– TCL - 10 + tA–ns – TCL - 15 + tA–ns – TCL - 10 + tA–ns – TCL - 10 + tA–ns

WR (with RW-delay) ALE falling edge to RD

CC -10 + t

– -10 + t

WR (no RW-delay) Address float after RD

CC–5–5ns

WR (with RW-delay) Address float after RD

CC – 30 – TCL + 5 ns

WR (no RW-delay)

, WR low time

CC 40 + t

– 2TCL - 10

(with RW-delay)

, WR low time

CC 65 + t

– 3TCL - 10

(no RW-delay)

to valid data in

SR – 30 + t

(with RW-delay) RD

to valid data in

SR – 55 + t

(no RW-delay)

ALE low to valid data in

SR – 55

+ tA + t

Address to valid data in

SR – 70

+ 2tA + t

Data hold after RD

SR0–0–ns

rising edge

Variable CPU Clock

1/2TCL = 1 to 20 MHz

+ t

– 2TCL - 20

– 3TCL - 20

– 4TCL - 30

Unit

–ns

+ t

+ tA + t

+ 2tA + t

Data float after RD

Data valid to WR

SR – 35 + t

SR 35 + t

Semiconductor Group 32

– 2TCL - 15

+ t

–ns

Page 34

C165

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

Data hold after WR t

ALE rising edge after RD

CC 35 + t

– 2TCL - 15

WR Address hold after RD

CC 35 + t

– 2TCL - 15

WR ALE falling edge to CS CS

low to Valid Data In t

hold after RD, WR t

ALE fall. edge to RdCS

CC -5 - t

SR – 55

CC 60 + t

CC 20 + t

10 - t

+ t

+ 2t

– 3TCL - 15

– TCL - 5

WrCS (with RW delay) ALE fall. edge to RdCS

CC -5 + t

–-5

WrCS (no RW delay)

Address float after RdCS

CC–0–0ns

WrCS (with RW delay)

Variable CPU Clock

1/2TCL = 1 to 20 MHz

–ns

+ t

–ns

+ t

–ns

+ t

-5 - t

10 - t

– 3TCL - 20

+ t –ns

+ t

–ns

+ t

–ns

+ t

+ 2t

Unit

ns ns

Address float after RdCS WrCS (no RW delay)

RdCS

to Valid Data In

(with RW delay) RdCS

to Valid Data In

(no RW delay) RdCS

, WrCS Low Time

(with RW delay) RdCS

, WrCS Low Time

(no RW delay) Data valid to WrCS

Data hold after RdCS Data float after RdCS

Address hold after RdCS

, WrCS

Data hold after WrCS

CC – 25 – TCL ns

SR – 25 + t

SR – 50 + t

CC 40 + t

CC 65 + t

CC 35 + t

SR0–0–ns

SR – 30 + t

CC 30 + t

– 2TCL - 10

– 3TCL - 10

– 2TCL - 15

– 2TCL - 20

– 2TCL - 25

+ t

– 3TCL - 25

+ t

–ns

+ t

–ns

+ t

– 2TCL - 20

+ t

–ns

+ t

–ns

+ t

Semiconductor Group 33

Page 35

C165

ALE

CSx

A23-A16

(A15-A8)

BHE

Read Cycle

BUS

Address

Data In

RdCSx

Write Cycle

BUS

WR,

WRL, WRH

WrCSx

Data OutAddress

Figure 12-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE

Semiconductor Group 34

Page 36

C165

ALE

CSx

A23-A16

(A15-A8)

BHE

Read Cycle

BUS

Address

Data InAddress

RdCSx

Write Cycle

BUS

WR,

WRL, WRH

WrCSx

Data OutAddress

Figure 12-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE

Semiconductor Group 35

Page 37

C165

ALE

CSx

A23-A16

(A15-A8)

BHE

Read Cycle

BUS

Address

Address Data In

RdCSx

Write Cycle

BUS

WR,

WRL, WRH

WrCSx

Data OutAddress

Figure 12-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE

Semiconductor Group 36

Page 38

C165

ALE

CSx

A23-A16

(A15-A8)

BHE

Read Cycle

BUS

Address

Data InAddress

RdCSx

Write Cycle

BUS

WR,

WRL, WRH

WrCSx

Data OutAddress

Figure 12-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE

Semiconductor Group 37

Page 39

AC Characteristics (cont’d) Demultiplexed Bus

= 5 V ± 10 %; VSS = 0 V

= 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF

= -40 to +85 ˚C for SAF-C165-LM

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

(for Port 6, CS) = 100 pF

ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)

C165

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

ALE high time t Address setup to ALE ALE falling edge to RD

CC 15 + t CC 10 + t CC 15 + t

– TCL - 10 + tA–ns – TCL - 15 + tA–ns – TCL - 10

WR (with RW-delay) ALE falling edge to RD

CC -10 + t

– -10

WR (no RW-delay)

, WR low time

CC 40 + t

– 2TCL - 10

(with RW-delay)

, WR low time

CC 65 + t

– 3TCL - 10

(no RW-delay)

to valid data in

SR – 30 + t

(with RW-delay)

to valid data in

SR – 55 + t

(no RW-delay)

ALE low to valid data in

SR – 55

+ tA + t

Address to valid data in

SR – 70

+ 2tA + t

Data hold after RD

SR0–0–ns

rising edge

Variable CPU Clock

1/2TCL = 1 to 20 MHz

+ t

– 2TCL - 20

– 3TCL - 20

– 4TCL - 30

Unit

–ns

+ t

+ tA + t

+ 2tA + t

Data float after RD

rising

SR – 35 + t

edge (with RW-delay) Data float after RD

rising

SR – 15 + t

edge (no RW-delay)

Data valid to WR

Data hold after WR ALE rising edge after RD

CC 35 + t

CC 15 + t CC -10 + t

Semiconductor Group 38

– 2TCL - 15

– TCL - 10

– 2TCL - 15

+ t

–ns

– TCL - 10 + tF–ns – -10

+ t

–ns

Page 40

C165

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

Address hold after RD,

CC 0 + t

–0

WR ALE falling edge to CS CS

low to Valid Data In t

hold after RD, WR t

ALE falling edge to RdCS

CC -5 - t

SR – 55

CC 10 + t

CC 20 + t

10 - t

+ t

+ 2t

– TCL - 15

– TCL - 5

WrCS (with RW-delay) ALE falling edge to RdCS

CC -5 + t

–-5

WrCS (no RW-delay) RdCS

to Valid Data In

SR – 25 + t

(with RW-delay) RdCS

to Valid Data In

SR – 50 + t

(no RW-delay) RdCS

, WrCS Low Time

CC 40 + t

– 2TCL - 10

(with RW-delay) RdCS

, WrCS Low Time

CC 65 + t

– 3TCL - 10

(no RW-delay) Data valid to WrCS

Data hold after RdCS Data float after RdCS

CC 35 + t

SR0–0–ns

SR – 30 + t

– 2TCL - 15

(with RW-delay) Data float after RdCS

SR – 5 + t

(no RW-delay)

Address hold after RdCS

, WrCS

Data hold after WrCS

CC -5 + t

CC 10 + t

–-5

– TCL - 15

Variable CPU Clock

1/2TCL = 1 to 20 MHz

–ns

+ t

-5 - t

10 - t

– 3TCL - 20

+ t –ns

+ t

–ns

+ t

–ns

+ t

– 2TCL - 25

+ t

– 3TCL - 25

+ t –ns

+ t

–ns

+ t

–ns

+ t

– 2TCL - 20

+ t

– TCL - 20

+ t –ns

+ t

–ns

+ t

+ 2t

Unit

ns ns

Semiconductor Group 39

Page 41

C165

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

Address

Data In

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

WrCSx

Data Out

Figure 13-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE

Semiconductor Group 40

Page 42

C165

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

Address

Data In

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

WrCSx

Data Out

Figure 13-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE

Semiconductor Group 41

Page 43

C165

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

Address

Data In

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

WrCSx

Data Out

Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE

Semiconductor Group 42

Page 44

C165

ALE

CSx

A23-A16

A15-A0

BHE

Read Cycle

BUS

(D15-D8)

D7-D0

Address

Data In

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

WrCSx

Data Out

Figure 13-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE

Semiconductor Group 43

Page 45

AC Characteristics (cont’d) CLKOUT and READY

= 5 V ± 10 %; VSS = 0 V

= 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF

= -40 to +85 ˚C for SAF-C165-LM

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

(for Port 6, CS) = 100 pF

C165

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

CLKOUT cycle time t CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to

CC 50 50 2TCL 2TCL ns

CC 20 – TCL – 5 – ns

CC 15 – TCL – 10 – ns

CC–5–5ns

CC 0 + t

10 + t

ALE falling edge

Synchronous READY

SR 10 – 10 – ns

setup time to CLKOUT

Synchronous READY

SR0–0–ns

hold time after CLKOUT

Asynchronous READY

SR 65 – 2TCL + 15 – ns

low time

Asynchronous READY

setup time

SR 15 – 15 – ns

Variable CPU Clock

1/2TCL = 1 to 20 MHz

0 + t

10 + t

Unit

Asynchronous READY

hold time Async. READY

hold time

after RD, WR high

(Demultiplexed Bus)

Notes

These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY The 2t

refer to the next following bus cycle.

SR0–0–ns

SR 0 0

+ 2tA + t

0 TCL - 25

+ 2tA + t

Semiconductor Group 44

Page 46

C165

Running cycle

READY

waitstate

MUX/Tristate

CLKOUT

ALE

Command

RD, WR

Sync

READY

Async

READY

see 6)

Figure 14 CLKOUT and READY

Notes

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill if READY

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero.

The next external bus cycle may start here.

sampled LOW at this sampling point terminates the currently running bus cycle.

in order to be safely synchronized. This is guaranteed,

is removed in response to the command (see Note 4)).

Semiconductor Group 45

Page 47

AC Characteristics (cont’d) External Bus Arbitration

= 5 V ± 10 %; VSS = 0 V

= 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF

= -40 to +85 ˚C for SAF-C165-LM

(for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

(for Port 6, CS) = 100 pF

C165

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

HOLD input setup time

SR 20 – 20 – ns

to CLKOUT CLKOUT to HLDA

high

CC – 20 – 20 ns

or BREQ low delay CLKOUT to HLDA

low

CC – 20 – 20 ns

or BREQ high delay

release t

CSx CSx

drive t Other signals release Other signals drive

CC – 20 – 20 ns

CC -5 25 -5 25 ns

CC – 20 – 20 ns

CC -5 25 -5 25 ns

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Unit

Semiconductor Group 46

Page 48

CLKOUT

HOLD

HLDA

C165

BREQ

CSx

(On P6.x)

Other

Signals

Figure 15 External Bus Arbitration, Releasing the Bus

Notes

The C165 will complete the currently running bus cycle before granting bus access.

This is the first possibility for BREQ to get active.

The CS outputs will be resistive high (pullup) after

Semiconductor Group 47

Page 49

C165

CLKOUT

HOLD

HLDA

BREQ

CSx

(On P6.x)

Other

Signals

Figure 16 External Bus Arbitration, (Regaining the Bus)

Notes

This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ Please note that HOLD

The next C165 driven bus cycle may start here.

is activated earlier, the regain-sequence is initiated by HOLD going high.

may also be deactivated without the C165 requesting the bus.

Semiconductor Group 48

Datasheet SAB-C165-LM, SAB-C165-RM, SAF-C165-LM Datasheet (Siemens)

Specifications and Main Features

Frequently Asked Questions

User Manual