Preliminary
SAB 83C517A-5 Microcontroller with factory mask-programmable ROM
SAB 80C517A Microcontroller for external ROM
SAB 80C517A/83C517A-5,
l
Eight data pointers for external memory
l
up to 18 MHz operationaddressing
l
32 K
8 ROM (SAB 83C517A-5 only,
×
Seventeen interrupt vectors, four priority
l
ROM-Protection available)levels selectable
256
l
l
l
8 on-chip RAM
×
×
2 K
8 on-chip RAM (XRAM)12 multiplexed inputs
Superset of SAB 80C51 architecture:
µ
– 1
s instruction cycle time at 12 MHzprogrammable Baudrate-Generators
– 666 ns instruction cycle time at 18 MHz
Genuine 10-bit A/D converter with
l
l
Two full duplex serial interfaces with
Fully upward compatible with SAB 80C515,
l
– 256 directly addressable bitsSAB 80C517, SAB 80C515A
– Boolean processor
– 64 Kbyte external data and
program memory addressing
Four 16-bit timer/counters
l
Powerful 16-bit compare/capture unit 0 to 70
l
(CCU) with up to 21 high-speed or PWM – 40 to 85
output channels and 5 capture inputs– 40 to 110
l
Versatile "fail-safe" provisions
Fast 32-bit division, 16-bit multiplication, P-MQFP-100-2
l
l
Extended power saving mode
Fast Power-On Reset
l
l
Nine ports: 56 I/O lines, 12 input lines
Three temperature ranges available:
l
o
C (T1)
o
C (T3)
o
C (T4)
l
Plastic packages: P-LCC-84,
32-bit normalize and shift by peripheral
MUL/DIV unit (MDU)
The SAB 80C517A/83C517A-5 is a high-end member of the Siemens SAB 8051 family of
microcontrollers. It is designed in Siemens ACMOS technology and based on SAB 8051
architecture. ACMOS is a technology which combines high-speed and density characteristics
with low-power consumption or dissipation.
While maintaining all the SAB 80C517 features and operating characteristics the
SAB 80C517A is expanded in its "fail-safe" characteristics and timer capabilities.The
SAB 80C517A is identical with the SAB 83C517A-5 except that it lacks the on-chip program
memory. The SAB 80C517A/83C517A-5 is supplied in a 84-pin plastic leaded chip carrier
package (P-LCC-84) and in a 100-pin plastic quad flat package (P-MQFP-100-2).
Semiconductor Group11994-05-01
Page 3
,
SAB 80C517A/83C517A-5
Revision History05.94
Previous Releases01.94/08.93/11.92/10.91/04.91
PageSubjects (changes since last revision 04.91)
SAB 80C517A/83C517A-5
6
4
7-15
several
3
26, 27, 31
– Pin configuration P-MQFP-100-2 added
– Pin differences updated
– Pin numbers for P-MQFP-100-2 package added
– Correction of P-MRFP-100 into P-MQFP-100-2
°
– Ordering information for -40 to +110
C versions
– Correction of register names S0RELL, SCON, ADCON, ICRON,
and SBUF
34
41
49
60
62
65
several
66
66
– Figure 4 corrected
– Figure 8 corrected
/SWD function description completed
– PE
– Correct ordering numbers
V
– Test condition for V
– t
t
name corrected
PXIZ
AVIV,
t
values corrected
AZPL
OH
OH1
corrected
– Minimum clock frequence is now 3.5 MHz
– t
– t
(data setup before WR
QVWH
LLAX2
corrected
) corrected and added
PageSubjects (changes since last revision 08.93)
26
51
– Corrected SFR name S0RELL
– Below "Termination of HWPD Mode": 4th paragraph with ident
corrected
65
65
74
– Description of t
– Program Memory Read Cycle: t
– Oscillator circuit drawings: MQFP-100-2 pin numbers added.
LLIV
corrected
PXAV
added
PageSubjects (changes since last revision 01.94)
– Minor changes on several pages
47
– Table 6 corrected
Semiconductor Group21994-05-01
Page 4
SAB 80C517A/83C517A-5
Ordering Information
TypeOrdering
Code
PackageDescription
8-bit CMOS Microcontroller
SAB 80C517A-N18Q67120-C583P-LCC-84
for external memory,18 MHz
SAB 80C517A-M18TBDP-MQFP-100-2
SAB 83C517A-5N18Q67120-C582P-LCC-84with mask-programmable ROM,
18 MHz
SAB 80C517A-N18-T3Q67120-C769P-LCC-84for external memory,18 MHz
o
ext. temperature – 40 to 85
C
SAB 83C517A-5N18-T3Q67120-C771P-LCC-84with mask-programmable ROM,
18 MHz
ext. temperature – 40 to 85
o
C
SAB 83C517A-N18-T4TBDP-LCC-84for external memory, 18 MHz
ext. temperature -40 to +110
o
C
SAB 83C517A-5N18-T4TBDP-LCC-84with mask-programmable ROM,
18 MHz
ext. temperature -40 to +110
o
C
Semiconductor Group31994-05-01
Page 5
SAB 80C517A/83C517A-5
Logic Symbol
Semiconductor Group41994-05-01
Page 6
Pin Configuration
(P-LCC-84)
SAB 80C517A/83C517A-5
The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with
one exception:
TypSAB 80C517ASAB 80C517/80C537
P-LCC-84, Pin 60
HWPD
P-MQFP-100-2, Pin 36
N.C.
Semiconductor Group51994-05-01
Page 7
SAB 80C517A/83C517A-5
Pin Configuration
(P-MQFP-100-2)
Semiconductor Group61994-05-01
Page 8
Pin Definitions and Functions
SAB 80C517A/83C517A-5
SymbolPin NumberI/O
P-LCC-84P-MQFP-100-2
P4.0 – P4.7 1– 3, 5 – 964 - 66,
I/O
68 - 72
*)
Function
Port 4
is a bidirectional I/O port with internal
pull-up resistors. Port 4 pins that have 1
s written to them are pulled high by the
internal pull-up resistors, and in that
state can be used as inputs. As inputs,
port 4 pins being externally pulled low
will source current ( I
in the DC char-
IL,
acteristics) because of the internal pullup resistors.
This port also serves alternate compare
functions. The secondary functions are
assigned to the pins of port 4 as follows:
– CM0 (P4.0): Compare Channel 0
– CM1 (P4.1): Compare Channel 1
– CM2 (P4.2): Compare Channel 2
– CM3 (P4.3): Compare Channel 3
– CM4 (P4.4): Compare Channel 4
– CM5 (P4.5): Compare Channel 5
– CM6 (P4.6): Compare Channel 6
– CM7 (P4.7): Compare Channel 7
/SWD467I
PE
*
I = Input
O = Output
Power saving modes enable Start
Watchdog Timer
A low level on this pin allows the software to enter the power down, idle and
slow down mode. In case the low level
is also seen during reset, the watchdog
timer function is off on default.
Use of the software controlled power
saving modes is blocked, when this pin
is held on high level. A high level during
reset performs an automatic start of the
watchdog timer immediately after reset.
When left unconnected this pin is pulled
high by a weak internal pull-up resistor.
Semiconductor Group71994-05-01
Page 9
Pin Definitions and Functions (cont’d)
SAB 80C517A/83C517A-5
SymbolPin Number
P-LCC-84P-MQFP-100-2
RESET
V
AREF
V
AGND
1073IRESET
1178
1279
P7.7 -P7.013 - 2080 - 87I
I/O
*)
Function
A low level on this pin for the duration of
one machine cycle while the oscillator is
running resets the SAB 80C517A. A
small internal pull-up resistor permits
power-on reset using only a capacitor
connected to V
SS
.
Reference voltage for the A/D con-
verter.
Reference ground for the A/D
converter.
Port 7
is an 8-bit unidirectional input port. Port
pins can be used for digital input, if
voltage levels meet the specified input
high/low voltages, and for the lower 8bit of the multiplexed analog inputs of
the A/D converter, simultaneously.
*
I = Input
O = Output
Semiconductor Group81994-05-01
Page 10
Pin Definitions and Functions (cont’d)
SAB 80C517A/83C517A-5
SymbolPin Number
I/O
*)
Function
P-LCC-84P-MQFP-100-2
P3.0 - P3.7 21 - 2890 - 97I/O Port 3
is a bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 3
pins being externally pulled low will source
current ( I
because of the internal pull-up resistors.
Port 3 also contains the interrupt, timer,
serial port 0 and external memory strobe
pins that are used by various options. The
output latch corresponding to a secondary
function must be programmed to a one (1)
for that function to operate.
The secondary functions are assigned to
the pins of port 3, as follows:
in the DC characteristics)
IL,
× D0 (P3.0): receiver data input
– R
(asynchronous) or data input/output
(synchronous) of serial interface
× D0 (P3.1): transmitter data output
–T
(asynchronous) or clock output
(synchronous) of serial interface 0
(P3.6):the write control signal
latches the data byte from port 0 into the
external data memory
– RD
(P3.7):the read control signal
enables the external data memory to
port 0
*
I = Input
O = Output
Semiconductor Group91994-05-01
Page 11
Pin Definitions and Functions (cont’d)
SAB 80C517A/83C517A-5
SymbolPin Number
P-LCC-84P-MQFP-100-2
P1.7 - P1.0 29 - 3698 - 100,
1, 6 - 9
*)
I/O
Function
I/OPort 1
is a bidirectional I/O port with internal
pull-up resistors. Port 1 pins that have
1 s written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 1
pins being externally pulled low will source
current (I
because of the internal pull-up resistors. It
is used for the low order address byte
during program verification. It also contains
the interrupt, timer, clock, capture and
compare pins that are used by various
options. The output latch must be
programmed to a one (1) for that function to
operate (except when used for the compare
functions).
The secondary functions are assigned to
the port 1 pins as follows:
Input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
XTAL14013–XTAL1
Output of the inverting oscillator amplifier.
To drive the device from an external clock
source, XTAL2 should be driven, while
XTAL1 is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, since the input to the
internal clocking circuitry is devided down
by a divide-by-two flip-flop. Minimum and
maximum high and low times as well as
rise/fall times specified in the AC
characteristics must be observed.
P2.0 - P2.7 41 - 4814 - 21I/OPort 2
is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as in-puts. As inputs, port 2
pins being externally pulled low will source
current (I
because of the internal pull-up resistors.
Port 2 emits the high-order address byte
during fetches from external program
memory and during accesses to external
data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses
strong internal pull-up resistors when
issuing1 s. During accesses to external
data memory that use 8-bit addresses
(MOVX @Ri), port 2 issues the contents of
the P2 special function register.
, in the DC characteristics)
IL
*
I = Input
O = Output
Semiconductor Group111994-05-01
Page 13
Pin Definitions and Functions (cont’d)
SAB 80C517A/83C517A-5
SymbolPin Number
I/O
*)
Function
P-LCC-84P-MQFP-100-2
PSEN4922OThe Program Store Enable
output is a control signal that enables the
external program memory to the bus during
external fetch operations. It is activated
every six oscillator periodes except during
external data memory accesses. Remains
high during internal program execution.
ALE5023OThe Address Latch Enable
output is used for latching the address into
external memory during normal operation.
It is activated every six oscillator periodes
except during an external data memory
access
EA
5124IExternal Access Enable
When held at high level, instructions are
fetched from the internal ROM (SAB
83C517A-5 only) when the PC is less than
8000H. When held at low level, the SAB
80C517A fetches all instructions from external program memory. For the SAB
80C517A this pin must be tied low
P0.0 - P0.7 52 - 5926 - 27,
30 - 35
*
I = Input
O = Output
I/OPort 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1 s written to them
float, and in that state can be used as highimpe-dance inputs. Port 0 is also the
multiplexed low-order address and data
bus during accesses to external program or
data memory. In this application it uses
strong internal pull-up resistors when
issuing 1 s. Port 0 also out-puts the code
bytes during program verification in the
SAB 83C517A if ROM-Protection was not
enabled. External pull-up resistors are
required during program verification.
Semiconductor Group121994-05-01
Page 14
Pin Definitions and Functions (cont’d)
SAB 80C517A/83C517A-5
SymbolPin Number
I/O
*)
Function
P-LCC-84P-MQFP-100-2
HWPD6036IHardware Power Down
A low level on this pin for the duration of
one machine cycle while the oscillator is
running resets the SAB 80C517A. A low
level for a longer period will force the part to
Power Down Mode with the pins floating.
(see table 7)
P5.7 - P5.0 61 - 6837 - 44I/OIPort 5
is a bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 5
pins being externally pulled low will source
current (I
, in the DC characteristics)
IL
because of the internal pull-up resistors.
This port also serves the alternate function
"Concurrent Compare" and "Set/Reset
Compare". The secondary functions are
assigned to the port 5 pins as follows:
– CCM0 to CCM7 (P5.0 to P5.7):
concurrent compare or Set/Reset
OWE6945I/OOscillator Watchdog Enable
A high level on this pin enables the
oscillator watchdog. When left
unconnected this pin is pulled high by a
weak internal pull-up resistor. When held at
low level the oscillator watchdog function is
off.
*
I = Input
O = Output
Semiconductor Group131994-05-01
Page 15
Pin Definitions and Functions (cont’d)
SAB 80C517A/83C517A-5
SymbolPin Number
P-LCC-84P-MQFP-100-2
P6.0 - P6.7 70 - 7746 - 50,
54 - 56
*)
I/O
Function
I/OPort 6
is a bidirectional I/O port with internal pullup resistors. Port 6 pins that have 1 s
written to them are pulled high by the
internal pull-up resistors, and in that state
can be used as inputs. As inputs, port 6
pins being externally pulled low will source
current (I
because of the internal pull-up resistors.
Port 6 also contains the external A/D
converter control pin and the transmit and
receive pins for serial channel 1. The
output latch corresponding to a secondary
function must be programmed to a one (1)
for that function to operate.
The secondary functions are assigned to
the pins of port 6, as follows:
, in the DC characteristics)
IL
– ADST
start pin
× D1 (P6.1): receiver data input
– R
of serial interface 1
× D1 (P6.2): transmitter data output
–T
of serial interface 1
P8.0 - P8.3 78 - 8157 - 60IPort 8
is a 4-bit unidirectional input port. Port pins
can be used for digital input, if voltage
levels meet the specified input high/low
voltages, and for the higher 4-bit of the
multiplexed analog inputs of the A/D
converter, simultaneously
*
I = Input
O = Output
(P6.0):external A/D converter
Semiconductor Group141994-05-01
Page 16
Pin Definitions and Functions (cont’d)
SAB 80C517A/83C517A-5
SymbolPin Number
I/O
*)
Function
P-LCC-84P-MQFP-100-2
R
O8261OReset Output
This pin outputs the internally
synchronized reset request signal. This
signal may be generated by an external
hardware reset, a watchdog timer reset
or an oscillator watch-dog reset. The
reset output is active low.
V
S S
V
CC
37, 8310, 62–Circuit ground potential
38, 8411, 63–Supply Terminal for all operating
modes
N.C.–2 - 5, 25,
–Not connected
28 - 29,
51 - 53,
74 - 77,
88 - 89
*
I = Input
O = Output
Semiconductor Group151994-05-01
Page 17
SAB 80C517A/83C517A-5
Figure 1
Block Diagram
Semiconductor Group161994-05-01
Page 18
SAB 80C517A/83C517A-5
Functional Description
The SAB 80C517A is based on 8051 architecture. It is a fully compatible member of the
Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced
SAB 80C517. The SAB 80C517A is therefore compatible with code written for the
SAB 80C517.
Having an 8-bit CPU with extensive facilities for bit-handling and binary BCD arithmetics the
SAB 80C517A is optimized for control applications. With a 18 MHz crystal, 58 % of the
instructions are executed in 666.67 ns.
Being designed to close the performance gap to the 16-bit microcontroller world, the
SAB 80C517A’s CPU is supported by a powerful 32-/16-bit arithmetic unit and a more flexible
addressing of external memory by eight 16-bit datapointers.
Memory Organisation
According to the SAB 8051 architecture, the SAB 80C517A has separate address spaces for
program and data memory. Figure 2 illustrates the mapping of address spaces.
Figure 2
Memory Map
Semiconductor Group171994-05-01
Page 19
SAB 80C517A/83C517A-5
Program Memory ('Code Space')
The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal
ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA
whether program fetches below address 8000H are done from internal or external memory.
As a new feature the SAB 83C517A-5 offers the possibility of protecting the internal ROM
against unauthorized access. This protection is implemented in the ROM-Mask.Therefore, the
decision ROM-Protection 'yes' or 'no' has to be made when delivering the ROM-Code. Once
enabled, there is no way of disabling the ROM-Protection.
Effect: The access to internal ROM done by an externally fetched MOVC instruction
is disabled. Nevertheless, an access from internal ROM to external ROM is possible.
To verify the read protected ROM-Code a special ROM-Verify-Mode is implemented. This
mode also can be used to verify unprotected internal ROM.
The data memory space consists of an internal and an external memory space. The
SAB 80C517A contains another 2 Kbyte on On-Chip RAM above the 256-bytes internal RAM
of the base type SAB 80C517. This RAM is called XRAM in this document.
External Data Memory
Up to 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16-bit
indirect addressing. For 8-bit addressing MOVX instructions in combination with registers R0
and R1 can be used. A 16-bit external memory addressing is supported by eight 16-bit
datapointers. Registers XPAGE and SYSCON are controlling whether data fetches at
addresses F800
Internal Data Memory
The internal data memory is divided into four physically distinct blocks:
to FFFFH are done from internal XRAM or from external data memory.
H
– the lower 128 bytes of RAM including four banks containing eight registers each
– the upper 128 byte of RAM
– the 128 byte special function register area.
– a 2 K
chip at the address range from F800
× 8 area which is accessed like external RAM (MOVX-instructions), implemented on
to FFFFH. Special Function Register SYSCON
H
controls whether data is read or written to XRAM or external RAM.
A mapping of the internal data memory is also shown in figure 2. The overlapping address
spaces are accessed by different addressing modes (see User's Manual SAB 80C517). The
stack can be located anywhere in the internal data memory.
Architecture for the XRAM
The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the
contents is undefined, while it remains unchanged during and after a reset or HW Power Down
if the power supply is not turned off.
The additional On-Chip RAM is logically located in the "external data memory" range at the
upper end of the 64 Kbyte address range (F800
-FFFFH). It is possible to enable and disable
H
(only by reset) the XRAM. If it is disabled the device shows the same behaviour as the parts
without XRAM, i.e. all MOVX accesses use the external bus to physically external data
memory.
Semiconductor Group191994-05-01
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SAB 80C517A/83C517A-5
Accesses to XRAM
Because the XRAM is used in the same way as external data memory the same instruction
types must be used for accessing the XRAM.
Note:
If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the
cycle which the reset is detected at (MOVX is a 2-cycle instruction):
Reset detection at cycle 1: The new value will not be written to XRAM. The old value
is not affected.
Reset detection at cycle 2: The old value in XRAM is overwritten by the new value.
Accesses to XRAM using the DPTR
There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR
for indirect addressing. The instructions are:
MOVX A,@DPTR (Read)
MOVX@DPTR, A (Write)
Normally the use of these instructions would use a physically external memory. However, in the
SAB 80C517A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM
address space (DPTR F800
Accesses to XRAM using the Registers R0/R1
The 8051 architecture provides also instructions for accesses to external data memory range
which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions
are:
H
).
MOVX A,@Ri (Read)
MOVX@Ri, A (Write)
In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as
page register which selects pages of 256-byte. However, the distinction, whether Port 2 is
used as general purpose I/O or as "page address" is made by the external system design. From
the device’s point of view it cannot be decided whether the Port 2 data is used externally as
address or as I/O data!
Hence, a special page register is implemented into the SAB 80C517A to provide the possibility
of accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same
function for the XRAM as Port 2 for external data memory.
Semiconductor Group201994-05-01
Page 22
Special Function Register XPAGE
SAB 80C517A/83C517A-5
Addr. 91
The reset value of XPAGE is 00
XPAGE can be set and read by software.
The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri
instructions. If the address formed from XPAGE and Ri is less than the XRAM address range,
then an external access is performed. For the SAB 80C517A the contents of XPAGE must be
greater or equal than F8H in order to use the XRAM. Of course, the XRAM must be enabled if
it shall be used with MOVX @Ri instructions.
Thus, the register XPAGE is used for addressing of the XRAM; additionally its contents are
used for generating the internal XRAM select. If the contents of XPAGE is less than the XRAM
address range then an external bus access is performed where the upper address byte is
provided by P2 and not by XPAGE!
Therefore, the software has to distinguish two cases, if the MOVX @Ri instructions with paging
shall be used:
a) Access to XRAM: The upper address byte must be written to XPAGE
H
.
H
or P2; both writes selects the XRAM address range.
XPAGE
b) Access to external memory: The upper address byte must be written to P2; XPAGE
will be loaded with the same address in order to deselect
the XRAM.
Semiconductor Group211994-05-01
Page 23
SAB 80C517A/83C517A-5
Control of XRAM in the SAB 80C517A
There are two control bits in register SYSCON which control the use and the bus operation
during accesses to the additional On-Chip RAM (XRAM).
Special Function Register SYSCON
Addr. 0B1
BitFunction
XMAP0Global enable/disable bit for XRAM memory.
XMAP1Control bit for RD
Reset value of SYSCON is xxxx xx01B.
The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM).
If this bit is set, the XRAM is disabled, all MOVX accesses use external memory via the external
bus. In this case the SAB 80C517A does not use the additional On-Chip RAM and is compatible
with the types without XRAM.
——————XMAP1XMAP0SYSCON
H
XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled.
XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are performed by the external bus (reset state).
/WR signals during accesses to XRAM; this bit has no
effect if XRAM is disabled (XMAP0 = 1) or if addresses exceeding the
XRAM address range are used for MOVX accesses.
XMAP1 = 0: The signals RD
to XRAM.
XMAP1 = 1: The signals RD
XRAM.
and WR are not activated during accesses
and WR are activated during accesses to
Semiconductor Group221994-05-01
Page 24
SAB 80C517A/83C517A-5
XMAP0 is hardware protected by an unsymmetric latch. An unintentional disabling of XRAM
could be dangerous since indeterminate values would be read from external bus. To avoid this
the XMAP-bit is forced to '1' only by reset. Additionally, during reset an internal capacitor is
loaded. So after reset state XRAM is disabled. Because of the load time of the capacitor
XMAP0-bit once written to '0' (that is, discharging capacitor) cannot be set to '1' again by
software. On the other hand any distortion (software hang up, noise, ...) is not able to load this
capacitor, too. That is, the stable status is XRAM enabled. The only way to disable XRAM after
it was enabled is a reset.
The clear instruction for XMAP0 should be integrated in the program initialization routine before
XRAM is used. In extremely noisy systems the user may have redundant clear instructions.
The control bit XMAP1 is relevant only if the XRAM is accessed. In this case the externa RD
and WR
debug purposes it might be useful to have these signals and the addresses at Ports 0.2
available. This is performed if XMAP1 is set.
The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register
SYSCON and on the state of pin EA
the following characteristics:
a) Use of P0 and P2 pins during the MOVX access.
b) Activation of the RD
c) Use of internal or external XDATA memory.
The shaded areas describe the standard operation as each 80C51 device without on-chip
XRAM behaves.
signals at P3.6 and P3.7 are not activated during the access, if XMAP1 is cleared. For
. The table 1 lists the various operating conditions. It shows
Bus:The pins work as external address/data bus. If (internal) XRAM is accessed, the
data written to the XRAM can be seen on the bus in debug mode.
I/0:The pins work as Input/Output lines under control of their latch.
and WR pin during the access.
Semiconductor Group231994-05-01
Page 25
Semiconductor Group241994-05-01
Table 1:
Behaviour of P0/P2 and / during MOVX accesses
RD WR
MOVX
@DPTR
MOVX
@Ri
DPTR < XRAM
address
range
DPTR ≥ XRAM
address
range
XPAGE < XRAM
addr. page
range
XPAGE ≥ XRAM
addr. page
range
0010X1
a) P0/P2ÝBus
RD WR
b) / active
c) ext. memory is
used
a) P0/P2ÝBUS
WR
( -Data only)
RD WR
b) / inactive
c) XRAM is used
a) P0ÝBus
P2ÝI/0
RD WR
b) / active
c) ext. memory is
used
a) P0/P2ÝBUS
WR
( -Data only)
P2ÝI/0
RD WR
b) / inactive
c) XRAM is used
EA
= 0
XMAP1, XMAP0
a) P0/P2ÝBus
RD WR
b) / active
c) ext. memory is
used
a) P0/P2ÝBUS
WR
( -Data only)
RD WR
b) / active
c) XRAM is used
a) P0ÝBus
P2ÝI/0
RD WR
b) / active
c) ext. memory is
used
a) P0/P2ÝBUS
WR
( -Data only)
P2ÝI/0
RD WR
b) / active
c) XRAM is used
a) P0/P2ÝBus
RD WR
b) / active
c) ext. memory is
used
a) P0/P2ÝBus
RD WR
b) / active
c) ext. memory is
used
a) P0ÝBus
P2ÝI/0
RD WR
b) / active
c) ext. memory is
used
a) P0ÝBus
P2ÝI/0
RD WR
b) / active
c) ext. memory is
used
0010X1
a) P0/P2ÝBus
RD
b) / active
c) ext. memory is
used
a) P0/P2ÝI/0
b) / inactive
c) XRAM is used
a) P0ÝBus
P2ÝI/0
b) / active
c) ext. memory is
used
a) P0/P2ÝI/0
b) / inactive
c) XRAM is used
WR
RD WR
RD WR
RD WR
EA
= 1
XMAP1, XMAP0
a) P0/P2ÝBus
RD WR
b) / active
c) ext. memory is
used
a) P0/P2ÝBUS
WR
( -Data only)
RD WR
b) / active
c) XRAM is used
a) P0ÝBus
P2ÝI/0
RD WR
b) / active
c) ext. memory is
used
a) P0ÝBUS
WR
( -Data only)
P2ÝI/0
RD WR
b) / active
c) XRAM is used
a) P0/P2ÝBus
RD WR
b) / active
c) ext. memory is
used
a) P0/P2ÝBus
RD WR
b) / active
c) ext. memory is
used
a) P0ÝBus
P2ÝI/0
RD WR
b) / active
c) ext. memory is
used
a) P0ÝBus
P2ÝI/0
RD WR
b) / active
c) ext. memory is
used
SAB 80C517A/83C517A-5
modes compatible to 8051 - family
Page 26
SAB 80C517A/83C517A-5
Multiple Datapointers
As a functional enhancement to standard 8051 controllers, the SAB 80C517A contains eight
16-bit datapointers. The instruction set uses just one of these datapointers at a time. The
selection of the actual datapointer is done in special function register DPSEL (data pointer
select, addr. 92
All registers, except the program counter and the four general purpose register banks, reside
in the special function register area. The 81 special function registers include arithmetic
registers, pointers, and registers that provide an interface between the CPU and the on-chip
peripherals. There are also 128 directly addressable bits within the SFR area. All special
function registers are listed in table 1 and table 2.
In table 1 they are organized in numeric order of their addresses. In table 2 they are organized
in groups which refer to the functional blocks of the SAB 80C517A.
In the SAB 80C517A a new high performance / high-speed 12-channel 10-bit A/D-Converter is
implemented. Its successive approximation technique provides 7
µs con-version time (f
MHz). The conversion principle is upward compatible to the one used in the SAB 80C517. The
main functional blocks are shown in figure 4.
The comparator is a fully differential comparator for a high power supply rejection ratio and very
low offset voltages. The capacitor network is binary weighted providing genuine 10-bit
resolution.
OSC
= 16
The table below shows the sample time T
on f
f
OSC
and a new prescaler (see also Bit ADCL in SFR ADCON 1).
OSC
[MHz]Prescalerf
and the conversion time T C, which are dependend
S
[MHz]Sample Time
ADC
Conversion Time
(incl. sample time)
T
S
[µs]
T
[µs]
C
12÷ 81.52.679.33
÷ 160.755.3318.66
16÷ 82.02.07.0
÷ 161.04.014.0
18÷ 8– – –
÷ 161.1253.5512.4
Semiconductor Group331994-05-01
Page 35
SAB 80C517A/83C517A-5
Figure 4
Block Diagram A/D Converter
Semiconductor Group341994-05-01
Page 36
SAB 80C517A/83C517A-5
Compare/Capture Unit (CCU)
The compare/capture unit is a complex timer/register array for applications that require high
speed I/O pulse width modulation and more timer/counter capabilities.
The CCU contains
– one 16-bit timer/counter (timer2) with 2-bit prescaler, reload capability and a max. clock
frequency of f
OSC/12
– one 16-bit timer (compare timer) with 8-bit prescaler, reload capability and a max. clock
frequency of f
OSC/2
– fifteen 16-bit compare registers.
– five of which can be used as 16-bit capture registers.
– up to 21 output lines controlled by the CCU.
– nine interrupts which can be generated by CCU-events.
Figure 5 shows a block diagram of the CCU. Eight compare registers (CM0 to CM7) can
individually be assigned to either timer 2 or the compare timer. Diagrams of the two timers are
shown in figures 6 and 7. The four compare/capture registers, the compare/reload/capture
register and the comset/comclr register are always connected to timer 2. Depending on the
register type and the assigned timer three different compare modes can be selected.
Table 3 illustrates possible combinations and the corresponding output lines.
Figure 5
Block Diagram of the Compare/Capture Unit
Semiconductor Group371994-05-01
Page 39
SAB 80C517A/83C517A-5
Compare
In compare mode, the 16-bit values stored in the dedicated compare registers are compared
to the contents of the timer 2 register or the compare timer register. If the count value in the
timer registers matches one of the stored value, an appropriate output signal is generated at
the corresponding pin(s) and an interrupt is requested. Three compare modes are provided:
Mode 0: Upon a match the output signal changes from low to high.
It returns to low level at timer overflow.
Mode 1: The transition of the output signal can be determined by software.
A timer overflow signal does not affect the compare-output.
Mode 2: In compare mode 2 the concurrent compare output pins on Port 5 are used
as follows (see figure 9)
– When a compare match occurs with register COMSET, a high level
appears at the pins of port 5 whose corresponding bits in the mask
register SETMSK (address 0A5
– When a compare match occurs in register COMCLR, a low level
appears at the pins of port 5 whose corresponding bits in the mask
register CLRMSK (address 0A6
Additionally the Port 5 pins used for compare mode 2 may also be
directly written to by write instructions to SFR P5. Of course, the pins
can also be read under program control.
) are set.
H
) are set.
H
Compare registers CM0 to CM7 use additional compare latches when operated in mode 0.
Figure 8 shows the function of these latches. The latches are implemented to prevent from loss
of compare matches which may occur when loading of the compare values is not correlated
with the timer count. The compare latches are automatically loaded from the compare registers
at every timer overflow.
Capture
This feature permits saving of the actual timer/counter contents into a selected register upon
an external event or a software write operation. Two modes are provided to 'freeze' the current
16-bit value of timer 2 registers into a dedicated capture register.
Mode 0:Capture is performed in response to a transition at the corresponding
port 1 pins CC0 to CC3.
Mode 1:Write operation into the low-order byte of the dedicated capture register
causes the timer 2 contents to be latched into this register.
Semiconductor Group381994-05-01
Page 40
SAB 80C517A/83C517A-5
Reload of Timer 2
A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the
8-bit registers CRCL and CRCH. There are two modes from which to select:
Mode 0: Reload is caused by a timer overflow (auto-reload).
Mode 1: Reload is caused in response to a negative transition at pin T2EX (P1.5),
which can also request an interrupt.
Timer/Counters 0 and 1
These timer/counters are fully compatible with timer/counter 0 or 1 of the SAB 8051 and can
operate in four modes:
Mode 0: 8-bit timer/counter with 32:1 prescaler
Mode 1: 16-bit timer/counter
Mode 2: 8-bit timer/counter with 8-bit auto reload
Mode 3: Timer/counter 0 is configured as one 8-bit timer;
timer/counter 1 in this mode holds its count.
External inputs INT0
0 and 1 to facilitate pulse width measurements.
and INT1 can be programmed to function as a gate for timer/counters
Semiconductor Group391994-05-01
Page 41
SAB 80C517A/83C517A-5
Figure 6
Block Diagram of Timer 2
Semiconductor Group401994-05-01
Page 42
f
OSC
SAB 80C517A/83C517A-5
/2
/2/4/8/16/32/64/128
3-Bit Prescaler
Control (CTCON)
Compare Timer
16-Bit Compare Timer
16-Bit Reload (CTREL)
Figure 7
Block Diagram of the Compare Timer
Overflow
CTF
16
To Compare
Circuitry
To Interrupt
Circuitry
MCB00783
Figure 8
Compare-Mode 0 with Registers CM0 to CM7
Semiconductor Group411994-05-01
Page 43
SAB 80C517A/83C517A-5
Figure 9
Compare-Mode 2 (Port 5 only)
Semiconductor Group421994-05-01
Page 44
SAB 80C517A/83C517A-5
Interrupt Structure
The SAB 80C517A has 17 interrupt vectors with the following vector addresses and request
flags.
Compare match interrupt of
Compare Register COMCLR
Each interrupt vector can be individually enabled/disabled. The response time to an interrupt
request is more than 3 machine cycles and less than 9 machine cycles.
External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable)
at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering
on a negative or a positive transition. The external interrupts 2 to 6 are combined with the
corresponding alternate functions compare (output) and capture (input) on port 1.
For programming of the priority levels the interrupt vectors are combined to pairs or triples.
Each pair or triple can be programmed individually to one of four priority levels by setting or
clearing one bit in special function register IP0 and one in IP1. Figure 9 shows the interrupt
request sources, the enabling and the priority level structure.
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Page 45
SAB 80C517A/83C517A-5
Figure 10
Interrupt Structure of the SAB 80C517A
Semiconductor Group441994-05-01
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SAB 80C517A/83C517A-5
Figure 10
Interrupt Structure of the SAB 80C517A (cont'd)
Semiconductor Group451994-05-01
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SAB 80C517A/83C517A-5
Figure 10
Interrupt Structure of the SAB 80C517A (cont'd)
Semiconductor Group461994-05-01
Page 48
SAB 80C517A/83C517A-5
Multiplication/Division Unit
This on-chip arithmetic unit provides fast 32-bit division, 16-bit multiplication as well as shift
and normalize features. All operations are integer operation.
The MDU consists of six registers used for operands and results and one control register.
Operation of the MDU can be divided in three phases:
Operation of the MDU
To start an operation, register MD0 to MD5 (or ARCON) must be written to in a certain sequence according to table 5 or 6. The order the registers are accessed determines the type of
the operation. A shift operation is started by a final write operation to register ARCON (see also
the register description).
Semiconductor Group471994-05-01
Page 49
SAB 80C517A/83C517A-5
I/O Ports
The SAB 80C517A has seven 8-bit I/O ports and two input ports (8-bit and 4-bit wide).
Port 0 is an open-drain bidirectional I/O port, while ports 1 to 6 are quasi-bidirectional I/O ports
with internal pull-up resistors. That means, when configured as inputs, ports 1 to 6 will be
pulled high and will source current when externally pulled low. Port 0 will float when configured
as input.
Port 0 and port 2 can be used to expand the program and data memory externally. During an
access to external memory, port 0 emits the low-order address byte and reads/writes the data
byte, while port 2 emits the high-order address byte. In this function, port 0 is not an open-drain
port, but uses a strong internal pull-up FET. Port 1, 3, 4, 5 and port 6 provide several alternate
functions. Please see the "Pin Description" for details.
Port pins show the information written to the port latches, when used as general purpose port.
When an alternate function is used, the port pin is controlled by the respective peripheral unit.
Therefore the port latch must contain a "one" for that function to operate. The same applies
when the port pins are used as inputs. Ports 1, 3, 4 and 5 are bit- addressable.
The SAB 80C517A has two dual-purpose input ports. The twelve port lines at port 7 and port
8 can be used as analog inputs for the A/D converter. If input voltages at P7 and P8 meet the
specified digital input levels (V
and V
IL
) the port can also be used as digital input port.
IH
In Hardware Power Down Mode the port pins and several control lines enter a floating state.
For more details see the section about Hardware Power Down Mode.
Semiconductor Group481994-05-01
Page 50
SAB 80C517A/83C517A-5
Power Saving Modes
The SAB 80C517A provides – due to Siemens ACMOS technology – four modes in which power consumption can be significantly reduced.
– The Slow Down Mode
The controller keeps up the full operating functionality, but is driven with one eighth
of its normal operating frequency. Slowing down the frequency remarkable reduces
power consumption.
– The Idle Mode
The CPU is gated off from the oscillator, but all peripherals are still supplied with the
clock and continue working.
– The Power Down Mode
Operation of the SAB 80C517A is stopped, the on-chip oscillator and the RC-oscillator
are turned off. This mode is used to save the contents of the internal RAM with a very
low standby current.
– The Hardware Power Down Mode
Operation of the SAB 80C517A is stopped, the on-chip oscillator and the RC-Oscillator
are turned off. The pin HWPD
controls this mode. Port pins and several control lines
enter a floating state. The Hardware Power Down Mode is independent of the state of
pin PE
/SWD.
Hardware Enable for Software controlled Power Saving Modes
A dedicated Pin PE
/SWD) of the SAB 80C517A allows to block the Software controlled power
saving modes. Since this pin is mostly used in noise-critical application it is combined with an
automatic start of the Watchdog Timer.
/SWD =
PE
V
(logic high level): Using of the power saving modes is not possible.
IH
The watchdog timer starts immediately after reset.
The instruction sequences used for entering of
power saving modes will not affect the normal operation
of the device.
/SWD =
PE
When left unconnected, Pin /PE
V
(logic low level):All power saving modes can be activated by software.
IL
/SWD is pulled high by a weak internal pullup. This is done to
provide system protection on default.
The logic-level applied to pin PE
/SWD can be changed during program execution to allow or to
block the use of the power saving modes without any effect on the on-chip watchdog circuitry.
Semiconductor Group491994-05-01
Page 51
SAB 80C517A/83C517A-5
Requirements for Hardware Power Down Mode
There is no dedicated pin to enable the Hardware Power Down Mode. Nevertheless for a
correct function of the Hardware Power Down Mode the oscillator watchdog unit including its
internal RC oscillator is needed. Therefore this unit must be enabled by pin OWE (OWE =
high). However, the control pin PE
disables only the use of software controlled power saving modes.
Software controlled power saving modes
All of these modes are entered by software. Special function register PCON (power control
register, address is 87
Slow Down Mode
During slow down operation all signal frequencies that are derived from the oscillator clock, are
divided by eight, also the clockout signal and the watchdog timer count.
) is used to select one of these modes.
H
/SWD has no control function in this mode. It enables and
The slow down mode is enabled by setting bit SD. The controller actually enters the slow down
mode after a short synchronisation period (max. 2 machine cycles).
The slow down mode is disabled by clearing bit SD.
Idle Mode
During idle mode all peripherals of the SAB 80C517A (except for the watchdog timer) are still
supplied by the oscillator clock. Thus the user has to take care which peripheral should
continue to run and which has to be stopped during Idle.
The procedure to enter the idle mode is similar to the one entering the power down mode. The
two bits IDLE and IDLS must be set by two consecutive instructions to minimize the chance of
unintentional activating of the idle mode.
There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enabled interrupt. This interrupt will
be serviced and the instruction to be executed following the RETI instruction will be the
one following the instruction that set the bit IDLS.
– The other way to terminate the idle mode, is a hardware reset. Since the oscillator is
still running, the hardware reset must be held active only for two machine cycles for
a complete reset.
Normally the port pins hold the logical state they had at the time idle mode was activated. If
some pins are programmed to serve their alternate functions they still continue to output during
idle mode if the assigned function is on. The control signals ALE and hold at logic high levels
PSEN
Semiconductor Group501994-05-01
(see table 8).
Page 52
SAB 80C517A/83C517A-5
Power Down Mode
Power Down Mode
The power down mode is entered by two consecutive instructions directly following each other.
The power down mode is entered by two consecutive instructions directly following each other.
The first instruction has to set the flag PDE (power down enable) and must not set PDS (power
The first instruction has to set the flag PDE (power down enable) and must not set PDS (power
down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will
down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will
automatically be cleared after having been set.
automatically be cleared after having been set.
The instruction that sets bit PDS is the last instruction executed before going into power down
The instruction that sets bit PDS is the last instruction executed before going into power down
mode. The only exit from power down mode is a hardware reset.
mode. The only exit from power down mode is a hardware reset.
The status of all output lines of the controller can be looked up in table 8.
The status of all output lines of the controller can be looked up in table 8.
Hardware Controlled Power Down Mode
Hardware Controlled Power Down Mode
controls this mode. If it is on logic high level (inactive) the part is running in the
The pin HWPD
The pin HWPD
normal operating modes. If pin HWPD
normal operating modes. If pin HWPD
Power Down Mode; this is independent of the state of pin PE
Power Down Mode; this is independent of the state of pin PE
is sampled once per machine cycle. If it is found active, the device starts a complete
HWPD
HWPD
internal reset sequence. The watchdog timer is stopped and its status flag WDTS is cleared
internal reset sequence. The watchdog timer is stopped and its status flag WDTS is cleared
exactly the same effects as a hardware reset. In this phase the power consumption is not yet
exactly the same effects as a hardware reset. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled. At the
reduced. After completion of the internal reset both oscillators of the chip are disabled. At the
same time the port pins and several control lines enter a floating state as shown in table 8. In
same time the port pins and several control lines enter a floating state as shown in table 8. In
this state the power consumption is reduced to the power down current IPD. Also the supply
this state the power consumption is reduced to the power down current IPD. Also the supply
voltage can be reduced. Table 8 also lists the voltages which may be applied at the pins during
voltage can be reduced. Table 8 also lists the voltages which may be applied at the pins during
Hardware Power Down Mode without affecting the low power consumption.
Hardware Power Down Mode without affecting the low power consumption.
is sampled once per machine cycle. If it is found active, the device starts a complete
controls this mode. If it is on logic high level (inactive) the part is running in the
gets active (low level) the part enters the Hardware
gets active (low level) the part enters the Hardware
/SWD.
/SWD.
Termination of HWPD Mode:
Termination of HWPD Mode:
is held active. If HWPD goes to high
This power down state is maintained while pin HWPD
This power down state is maintained while pin HWPD
level (inactive state) an automatic start up procedure is performed:
level (inactive state) an automatic start up procedure is performed:
– First the pins leave their floating condition and enter their default reset state
– First the pins leave their floating condition and enter their default reset state
(as they had immediately before going to float state).
(as they had immediately before going to float state).
– Both oscillators are enabled (only if OWE = high). The oscillator watchdog’s RC
– Both oscillators are enabled (only if OWE = high). The oscillator watchdog’s RC
oscillator starts up very fast (typ. less than 2 microseconds).
oscillator starts up very fast (typ. less than 2 microseconds)
– Because the oscillator watchdog is active it detects a failure condition if the
– Because the oscillator watchdog is active it detects a failure condition if the
on-chip oscillator hasn’t yet started. Hence, the watchdog keeps the part in reset
on-chip oscillator hasn’t yet started. Hence, the watchdog keeps the part in reset
and supplies the internal clock from the RC oscillator.
and supplies the internal clock from the RC oscillator.
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases
the part from reset with oscillator watchdog status flag not set.
the part from reset with oscillator watchdog status flag not set
When automatic start of the watchdog was enabled (PE
When automatic start of the watchdog was enabled (PE
the Watchdog Timer will start, too (with its default reload value for time-out period).
the Watchdog Timer will start, too (with its default reload value for time-out period).
pin overrides the Hardware Power Down function, i.e. if reset gets active
– The Reset
– The Reset
during Hardware Power Down it is terminated and the device performs the normal
during Hardware Power Down it is terminated and the device performs the normal
reset function. (Thus, pin Reset
reset function. (Thus, pin Reset
pin overrides the Hardware Power Down function, i.e. if reset gets active
has to be inactive during Hardware Power Down Mode).
has to be inactive during Hardware Power Down Mode).
is held active. If HWPD goes to high
/SWD connected to VCC),
/SWD connected to VCC),
Semiconductor Group511994-05-01
Page 53
SAB 80C517A/83C517A-5
Table 8
Status of all pins during Idle Mode, Power Down Mode and Hardware Power
Down Mode
PinsIdle Mode
Last instruction
executed from
internal
ROM
external
ROM
Power Down Mode
Last instruction
executed from
internal
ROM
external
ROM
Hardware Power Down
StatusVoltage range
P0DatafloatDatafloat
P1Data alt
outputs
Data alt
outputs
Data last
outputs
Data last
outputs
floating
P2DataAddressDataDataoutput
P3Data alt
outputs
P4Data alt
outputs
P5Data
alt output
P6Data
alt output
Data alt
outputs
Data alt
outputs
Data
alt output
Data
alt output
Data
last output
Data last
outputs
Data
last output
Data
last output
Data
last output
Data
last output
Data
last output
Data
last output
outputs
disabledV
input
function
at pin
≤ VIN ≤ V
SS
CC
P7
P8
EAactive inputV
PE/SWDactive input
pull-up
IN
= V
V
IN
V
IN
= V
V
IN
= VCC or
SS
= VCC or
SS
disabled
XTAL1active outputpin may not be
driven
XTAL2disabled
≤V
V
SS
IN
≤ V
CC
input
functions
Semiconductor Group521994-05-01
Page 54
SAB 80C517A/83C517A-5
Table 8
Status of all pins during Idle Mode, Power Down Mode and Hardware Power
Down Mode (cont’d)
PinsIdle Mode
Last instruction
executed from
internal
ROM
external
ROM
PSEN
ALE
VAREF
VAGND
OWE
RESET
Power Down Mode
Last instruction
executed from
internal
ROM
external
ROM
Hardware Power Down
StatusVoltage range
at pin
floating
V
SS
≤ VIN≤ V
CC
outp. disabled input
functions
active supply pins
active input,
V
AGND
≤ V
V
IN
CC
= V
≤ V
CC
IN
must be
high pull-up
disabl.
active input
VIN = V
CC
must be high
RO
floating
output
VSS ≤ VIN≤ V
CC
Semiconductor Group531994-05-01
Page 55
SAB 80C517A/83C517A-5
Serial Interfaces
The SAB 80C517A has two serial interfaces. Both interfaces are full duplex and receive
buffered. They are functionally identical with the serial interface of the SAB 8051 when working
as asynchronous channels. Serial interface 0 additionally has a synchronous mode. Table 9
shows possible configurations and the according baud rates.
Table 9
Baud Rate Generation
8-Bit
synchronous
channel
8-Bit
UART
ModeMode 0
Baudrate
=1
f
O SC
2 MHz
=
f
OSC
1MHz
1.33 MHz
16 MHz
f
OSC
=
1.5 MHz
18 MHz
derived fromf
OSC
ModeMode 1 Mode B
Baudrate
f
=
OSC
12 MHz
=
f
OSC
16 MHz
=
f
OSC
18 MHz
1 Baud –
62.5 kBaud
1 Baud –
83 kBaud
1 Baud –
93.7 kBaud
183 Baud –
375 kBaud
244 Baud –
500 kBaud
2375
562.5
derived fromTimer 110-Bit
Baudrate
Generator
Baud–
kBaud
–
–
–
–
–
366 Baud –
375 kBaud
244 Baud –
500 kBaud
549 Baud –
562.5 kBaud
10-Bit
Baudrate
Generator
Mode Mode 2Mode 3Mode A
9-Bit
UART
Baudrate
derived
from
=
f
OSC
12 MHz
=
f
OSC
16 MHz
=
f
OSC
18 MHz
2Timer 110-Bit
f
OSC/
187.5 kBaud/
375 kBaud
250 Baud/
500 kBaud
281.2 kBaud/
562.5 kBaud
1 Baud –
62.5 kBaud
1 Baud –
83.3 kBaud
1 Baud –
93.7 kBaud
Baudrate
Generator
183 Baud –
75 kBaud
244 Baud –
500 kBaud
275 Baud
562.5 kBaud
183 Baud –
75 kBaud
244 Baud –
500 kBaud
549 Baud –
562.5 kBaud
10-Bit
Baudrate
Generator
Semiconductor Group541994-05-01
Page 56
Serial Interface 0
Serial Interface 0 can operate in 4 modes:
Mode 0: Shift register mode:
Serial data enters and exits through R × D0. T × D0 outputs the shift
clock 8 data bits are transmitted/received (LSB first). The baud rate is fixed at
1/12 of the oscillator frequency.
Mode 1: 8-bit UART, variable baud rate:
10-bit are transmitted (through T × D0) or received (through R × D0): a start
bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit
goes into RB80 in special function register S0CON. The baud rate is
variable.
Mode 2: 9-bit UART, fixed baud rate:
11-bit are transmitted (through T × D0) or received (through R × D0): a start
bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1).
On transmission, the 9th data bit (TB80 in S0CON) can be assigned to the
value of 0 or 1. For example, the parity bit (P in the PSW) could be moved
into TB80 or a second stop bit by setting TB80 to 1. On reception the 9th
data bit goes into RB80 in special function register S0CON, while the stop
bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the
oscillator frequency.
SAB 80C517A/83C517A-5
Mode 3:9-bit UART, variable baud rate:
11-bit are transmitted (through T × D0) or received (through R × D0): a start
bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1). In
fact, mode 3 is the same as mode 2 in all respects except the baud rate.
The baud rate in mode 3 is variable.
Variable Baud Rates for Serial Interface 0
Variable baud rates for modes 1 and 3 of serial interface 0 can be derived from either timer 1
or a dedicated Baudrate Generator.
The baud rate is generated by a free running 10-bit timer with programmable reload register.
Mode 1.3 baud rate = 2
Mode 1.3 baud rate =
SMOD
* f OSC
64*(210-S0REL)
The default value after reset in the reload registers S0RELL and S0RELH provide a baud rate
of 4.8 kBaud (SMOD = 0) or 9.6 kBaud (SMOD = 1) at 12 MHz oscillator frequency. This guarantees full compatibility to the SAB 80C517.
Semiconductor Group551994-05-01
Page 57
Serial Interface 1
baud
k
f
Serial interface 1 can operate in two asynchronous modes:
Mode A: 9-bit UART, variable baud rate.
11 bits are transmitted (through T × D1) or received (through R × D1):
a start bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1).
On transmission, the 9th data bit (TB81 in S1CON) can be assigned to the
value of 0 or 1. For example, the parity bit (P in the PSW) could be moved
into TB81 or a second stop bit by setting TB81 to 1. On reception the 9th
data bit goes into RB81 in special function register S1CON, while the stop
bit is ignored.
Mode B: 8-bit UART, variable baud rate.
10 bits are transmitted (through T × D1) or received (through R × D1):
a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the
stop bit goes into RB81 in special function register S1CON.
SAB 80C517A/83C517A-5
Variable Baud Rates for Serial Interface 1.
Variable baud rates for modes A and B of serial interface 1 are derived from a dedicated baud
rate generator.
rate cloc
The baud rate clock (baud rate = ) is generated by an 10-bit free running timer
16
with programmable reload register.
OSC
Mode A, B baudrate =
32* (2
10
- SREL)
Semiconductor Group561994-05-01
Page 58
SAB 80C517A/83C517A-5
Watchdog Units
The SAB 80C517A offers two enhanced fail safe mechanisms, which allow an automatic
recovery from hardware failure or software upset:
– programmable watchdog timer (WDT), variable from 512 µs up to appr. 1.1 s time-out
period @12 MHz. Upward compatible to SAB 80515 watchdog.
– oscillator watchdog (OWD), monitors the on-chip oscillator and forces the micro-
controller into reset state, in case the on-chip oscillator fails, controls the restart from
the Hardware Power Down Mode and provides clock for a fast internal reset after power-on.
Programmable Watchdog Timer
The WDT can be activated by hardware or software.
Hardware initialization is done when pin PE
SAB 80C517A then starts program execution with the WDT running. Since Pin PE
only sampled during Reset (and hardware power down at parts with stepping code AD and
later) dynamical switching of the WDT is not possible.
Software initialization is done by setting bit SWDT.
A refresh of the watchdog timer is done by setting bits WDT and SWDT consecutively.
A block diagram of the watchdog timer is shown in figure 11.
When a watchdog timer resest occurs, the watchdog timer keeps on running, but a status flag
WDTS is set. This flag can also be cleared by software.
/SWD (Pin 4) is held high during RESET. The
/SWD is
Figure 11
Block Diagram of the Programmable Watchdog Timer
Semiconductor Group571994-05-01
Page 59
SAB 80C517A/83C517A-5
Oscillator Watchdog
The unit serves three functions:
– Monitoring of the on-chip oscillator’s function.
The watchdog supervises the on-chip oscillator’s frequency; if it is lower than the
frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is
supplied by the RC oscillator and the device is forced into reset; if the failure condition
disappears (i.e. the on-chip oscillator has again a higher frequency than the RC oscillator),
the part executes a final reset phase of appr. 0.25 ms in order to allow the oscillator
to stabilize; then the oscillator watchdog reset is released and the part starts
program execution again.
– Restart from the Hardware Power Down Mode.
If the Hardware Power Down Mode is terminated the oscillator watchdog has to control
the correct start-up of the on-chip oscillator and to restart the program. The oscillator
watchdog function is only part of the complete Hardware Power Down sequence; however,
the watchdog works identically to the monitoring function.
– Fast internal reset after power-on.
In this function the oscillator watchdog unit provides a clock supply for the reset before
the on-chip oscillator has started. In this case the oscillator watchdog unit also
works identically to the monitoring function.
If the oscillator watchdog unit is to be used it must be enabled (this is done by applying high
level to the control pin OWE).
Figure 12 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC
oscillator which provides the reference frequency of the on-chip oscillator. The RC oscillator
can be enabled/disabled by the control pin OWE. If it is disabled the complete unit has no
function.
Semiconductor Group581994-05-01
Page 60
SAB 80C517A/83C517A-5
Figure 12
Functional Block Diagram of the Oscillator Watchdog
Semiconductor Group591994-05-01
Page 61
SAB 80C517A/83C517A-5
Fast internal reset after power-on
The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after
power-on.
Normally members of the 8051 family (like the SAB 80C517) enter their default reset state not
before the on-chip oscillator starts. The reason is that the external reset signal must be
internally synchronized and processed in order to bring the device into the correct reset state.
Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 1 ms).
During this time period the pins have an undefined state which could have severe effects e.g.
to actuators connected to port pins.
In the SAB 80C517A the oscillator watchdog unit avoids this situation. However, the oscillator
watchdog must be enabled. In this case, after power-on the oscillator watch-dog’s RC
oscillator starts working within a very short start-up time (typ. less than 2 micro-seconds). In
the following the watchdog circuitry detects a failure condition for the on-chip oscillator
because this has not yet started (a failure is always recognized if the watchdog’s RC oscillator
runs faster than the on-chip oscillator). As long as this condition is valid the watchdog uses the
RC oscillator output as clock source for the chip rather than the on-chip oscillator’s output.This
allows correct resetting of the part and brings also all ports to the defined state.
Delay time between power-on and correct reset state:
Typ.: 18
Max.: 34
µs
µs
Instruction Set
The SAB 80C517A / 83C517A-5 has the same instruction set as the industry standard 8051
microcontroller.
A pocket guide is available which contains the complete instruction set in functional and
hexadecimal order. Furtheron it provides helpful information about Special Function Registers,
Interrupt Vectors and Assembler Directives.
Literature Information
TitleOrdering No.
Microcontroller Family SAB 8051 Pocket GuideB158-H6497-X-X-7600
Semiconductor Group601994-05-01
Page 62
Absolute Maximum Ratings
SAB 80C517A/83C517A-5
Ambient temperature under bias................................................................. – 40 to 110˚ C
o
CC
C
+0.5 V
Storage temperature................................................................................... – 65 to 150
Voltage on V
pins with respect to ground (V
CC
Voltage on any pin with respect to ground (V
) ...................................... – 0.5 V to 6.5 V
SS
) ........................................ – 0.5 to V
SS
Input current on any pin during overload condition..................................... – 10mA to +10mA
Absolute sum of all input currents during overload condition...................... |100mA
|
Power dissipation........................................................................................ 1 W
NoteStresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
>
V
or
V
periods may affect device reliability. During overload conditions (V
V
)
theVoltage on V
SS
pins with respect to ground (VSS) must not exeed the values
CC
IN
CC
<
IN
definded by the absolute maximum ratings.
DC Characteristics
V
= 5 V + 10 %, – 15 %;
CC
V
= 0 V
SS
T
= 0 to 70
A
T
= – 40 to 85oC for the SAB 80C517A-T3/83C517A-5-T3
A
T
= – 40 to 110 oC for the SAB 80C517A-T4/83C517A-5-T4
A
o
C for the SAB 80C517A/83C517A-5
ParameterSymbolLimit ValuesUnitTest Condition
min.max.
Input low voltage
(except EA
, RESET, HWPD)
Input low voltage (EA)V
V
IL
IL1
– 0.50.2 VCC –
0.1
– 0.50.2 V
CC
–
V–
V–
0.3
Input low voltage (HWPD,
RESET
)
Input high voltage (except
RESET, XTAL2 and HWPD
Input high voltage to XTAL2 V
Input high voltage to RESET
V
IL2
– 0.50.2 V
CC
+ 0.1
V
IH
0.2 V
CC
V
+ 0.5V–
CC
+ 0.9
IH1
V
IH2
0.7 V
0.6 V
VCC + 0.5V–
CC
VCC + 0.5V–
CC
V–
and HWPD
Semiconductor Group611994-05-01
Page 63
SAB 80C517A/83C517A-5
DC Characteristics (cont’d)
ParameterSymbolLimit ValuesUnitTest condition
min.max.
Output low voltage
(ports 1, 2, 3, 4, 5, 6)
Output low voltage
(ports ALE, PSEN
, RO)
Output high voltage
(ports 1, 2, 3, 4, 5, 6)
Output high voltage
(port 0 in external bus mode,
ALE, PSEN
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed
on the V
discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during
bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line
may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
of ALE and ports 1, 3, 4, 5 and 6. The noise is due to external bus capacitance
OL
2) Capacitive loading on ports 0 and 2 may cause the V
below the0.9 V
fall
3) I
4) I
(Power down mode) is measured with:
PD
EA = RESET = V
PE/SWD = OWE = V
V
or V
CC
= V
AGND
SS
(active mode) is measured with:
SS
. No certain pin connection for the other pins.
CC;
; all other pins are disconnected. Hardware Powerdown IPD : OWE =VCC
XTAL2 driven with t
EA = PE/SWD = V
all other pins are disconnected. I
specification when the address lines are stabilizing.
= – 40 to 85o C for the SAB 80C517A-T3/83C517A-5-T3
T
A
= – 40 to 110 oC for the SAB 80C517A-T4/83C517A-5-T4
T
A
= VSS ± 0.2 V;
AGND
= 0 V
SS
o
C for the SAB 80C517A/83C517A-5
ParameterSymbolLimit valuesUnitTest condition
min.typ.max.
Analog input capacitanceC
Sample time
I
T
S
2570pF
1)
4 t
CY
µs
2)
(inc. load time)
Conversion time
T
C
14 t
CY
1)
µs
3)
(inc. sample time)
Total unadjusted errorTUE± 2LSBV
V
supply currentI
AREF
REF
± 20µA
V
4)
AREF
AGND
= V
= V
CC
SS
ADCL
1)
tCY = (8*2
2)
This parameter specifies the time during the input capacitance CI, can be charged/discharged by the
external source. It must be guaranteed, that the input capacitance CI,, is fully loaded within this time.
4TCY is 2 µs at the f
voltage have no effect on the conversion result.
3)
This parameter includes the sample time TS. 14TCY is 7 µs at f
4)
The differencial impedance rD of the analog reference source must be less than 1 KΩ at reference supply
voltage.
)
/f
OSC
; (tCY = 1/f
= 16 MHz. After the end of the sample time TS, changes of the analog input
OSC
ADC
; f
ADC
= f
OSC
/(8*2
ADCL
))
= 16 MHz.
OSC
Semiconductor Group641994-05-01
Page 66
SAB 80C517A/83C517A-5
AC Characteristics
= 5 V + 10 %, – 15 %;V SS = 0 V
V
CC
= 0 to 70
T
A
= – 40 to 85 oC for the SAB 80C517A-T3/83C517A-5-T3
T
A
= – 40 to110 o C for the SAB 80C517A-T4/83C517A-5-T4
T
A
for port 0, ALE and PSEN outputs = 100 pF; C
(C
L
ParameterSymbolLimit V aluesUnit
18 MHz ClockVariable Clock
min.max.min.max.
o
C for the SAB 80C517A/83C517A-5
for all other outputs = 80 pF)
L
1/t
= 3.5 MHz to 18 MHz
CLCL
Program Memory Characteristics
ALE pulse widtht
Address setup to ALEt
Address hold after ALEt
ALE to valid instructiont
ALE to PSEN
PSEN
PSEN
pulse widtht
to valid instruction t
Input instruction hold
LHLL
AVLL
LLAX
LLIV
t
LLPL
PLPH
PLIV
t
PXIX
after PSEN
Input instruction float
t
PXIZ
after PSEN
Address valid after
t
PXAV*)
PSEN
Address to valid instr int
AVIV
71–2 t
26–t
26–t
CLCL
CLCL
–122–4t
31–t
CLCL
132–3 t
–92–3t
– 40–ns
CLCL
– 30–ns
– 30–ns
– 100ns
CLCL
– 25–ns
– 35–ns
CLCL
– 75ns
CLCL
0–0ns
–46–t
48–t
– 8–ns
CLCL
–218–5t
– 10ns
CLCL
– 60ns
CLCL
Address float to PSEN
*)
Interfacing the SAB 80C517A to devices with float times up to 45 ns is permissible.
This limited bus contention will not cause any damage to port 0 drivers.
t
AZPL
0–0–ns
Semiconductor Group651994-05-01
Page 67
SAB 80C517A/83C517A-5
AC Characteristics (cont’d)
ParameterSymbolLimit V aluesUnit
18 MHz ClockVariable Clock
1/t
min.max.min.max.
External Data Memory Characteristics
= 3.5 MHz to 18 MHz
CLCL
pulse widtht
RD
WR
pulse widtht
Address hold after ALEt
RD
to valid data int
Data hold after RD
Data float after RD
ALE to valid data int
Address to valid data int
ALE to WR or RDt
WR or RD high to ALE
high
Address valid to WRt
RLRH
WLWH
LLAX2
RLDV
t
RHDX
t
RHDZ
LLDV
AVDV
LLWL
t
WHLH
AVWL
233–6 t
233–6 t
81–2 t
–128–5 t
– 100–ns
CLCL
– 100–ns
CLCL
– 30–ns
CLCL
– 150ns
CLCL
0–0–ns
–51–2 t
–294–8 t
–335–9 t
1172173 t
1696t
CLCL
92–4 t
– 503 t
CLCL
– 40t
– 130–ns
CLCL
CLCL
– 60ns
CLCL
– 150ns
CLCL
– 165ns
CLCL
+50ns
CLCL
+40ns
Data valid to WR
t
QVWX
11–t
– 45–ns
CLCL
transition
Data setup before WRt
Data hold after WR
Address float after RD
QVWH
t
WHQX
t
RLAZ
239–7 t
16–t
CLCL
– 150–ns
CLCL
– 40–ns
–0–0ns
Semiconductor Group661994-05-01
Page 68
ALE
t
SAB 80C517A/83C517A-5
LHLL
PSEN
Port 0
Port 2
Program Memory Read Cycle
t
AVLLPLPH
A0 - A7Instr.INA0 - A7
t
AVIV
t
t
LLPL
t
LLIV
t
PLIV
t
AZPL
t
LLAX
A8 - A15A8 - A15
t
t
t
PXIZ
PXIX
PXAV
MCT00096
Data Memory Read Cycle
Semiconductor Group671994-05-01
Page 69
ALE
PSEN
SAB 80C517A/83C517A-5
t
WHLH
WR
t
AVLL
t
LLAX2
Port 0
A0 - A7 from
Ri or DPLfrom PCL
t
AVWL
Port 2
Data Memory Write Cycle
t
LLWL
t
QVWX
t
WLWH
t
QVWH
Data OUT
t
WHQX
A0 - A7
A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH
Instr.IN
MCT00098
Semiconductor Group681994-05-01
Page 70
SAB 80C517A/83C517A-5
AC Characteristics (cont'd)
ParameterSymbolLimit V aluesUnit
Variable clock
Frequ. = 3.5 MHz to 18 MHz
min.max.
External Clock Drive
Oscillator periodt
High timet
Low timet
Rise timet
Fall timet
CLCL
CHCX
CLCX
CLCH
CHCL
Oscillator frequency1/t
CLC
55.6285ns
20t
20t
–
–
CLCL-tCHCX
CLCL-tCHCX
20ns
20ns
ns
ns
3.518MHz
External Clock Cycle
Semiconductor Group691994-05-01
Page 71
SAB 80C517A/83C517A-5
AC Characteristics (cont'd)
ParameterSymbolLimit V aluesUnit
System Clock Timing
ALE to CLKOUTt
CLKOUT high timet
CLKOUT low timet
CLKOUT low to ALE
high
LLSH
SHSL
SLSH
t
SLLH
18 MHz clock
1/t
Variable Clock
= 3.5 MHz to 18 MHz
CLCL
min.max.min.max.
349–7 t
71–2 t
516–10 t
1696t
CLCL
– 40–ns
CLCL
– 40–ns
CLCL
– 40–ns
CLCL
– 40t
+40ns
CLCL
System Clock Timing
Semiconductor Group701994-05-01
Page 72
SAB 80C517A/83C517A-5
ROM Verification Characteristics
= 25˚C ± 5˚C; VCC = 5 V ± 10%; VSS = 0 V
T
A
ParameterSymbolLimit V aluesUnit
min.
max.
ROM Verification Mode 1 (Standard Verify Mode for not Read Protected ROM)
Address to valid datat
ENABLE to valid datat
Data float after ENABLEt
AVQV
ELQV
EHOZ
Oscillator frequency1/t
CLCL
–
–
048 t
48 t
48 t
CLCL
CLCL
CLCL
46MHz
ns
ns
ns
ROM Verification Mode 1
Semiconductor Group711994-05-01
Page 73
SAB 80C517A/83C517A-5
ROM Verification Mode 2 (New Verify Mode for Protected and not Protected ROM)
ROM Verification Mode 2
Semiconductor Group721994-05-01
Page 74
SAB 80C517A/83C517A-5
Application Circuitry for Verifying the Internal ROM
Semiconductor Group731994-05-01
Page 75
AC Testing: Input, Output Waveforms
AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at
V
IHmin
for a logic ’1’ and V
ILmax
for a logic ’0’.
SAB 80C517A/83C517A-5
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and
begins to float when a 100 mV change from the loaded V
OH/VOL
level occurs. IOL/I
≥± 20 mA.
OH
AC Testing: Float Waveforms
Recommended Oscillator Circuits
Semiconductor Group741994-05-01
Page 76
SAB 80C517A/83C517A-5
GPM05623
Plastic Package, P-MQFP-100-2 (SMD)
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
Dimensions in mm
Figure 1
P-MQFP-100-2 Package Outlines
Semiconductor Group751994-05-01
Page 77
Plastic Package, P-LCC-84-2 (SMD)
(Plastic Leaded Chip Carrier)
SAB 80C517A/83C517A-5
Figure 2
P-LCC-84-2 Package Outlines
GPM05623
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
Dimensions in mm
Semiconductor Group761994-05-01
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