Datasheet SAA7707H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7707H

Car radio Digital Signal Processor
(CDSP)

Preliminary specification
Supersedes data of 1996 May 22
File under Integrated Circuits, IC01

1997 May 30

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

CONTENTS

1 FEATURES

1.1 Hardware

1.2 Software
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 Signal path for level information

8.2 Level ADC switch mode integrator (pin CINT)

8.3 Internal ground reference for the level ADC
(pin V

DACNL

)

8.4 Common mode reference voltage for RDS
ADC, ADC level and buffers (pin V

refRDS

)

8.5 Signal path for audio/MPX and stereo decoder

8.6 Mono/stereo switching

8.7 The automatic lock system

8.8 Input sensitivity for FM

8.9 Common mode reference voltage for MPX
ADC and buffers (pin V

refMPX

)

8.10 Supply voltages for the switch capacitor DACs
of the FMMPX ADC and FMRDS ADC
(pins V

DACNM

and V

DACPM

)

8.11 Noise level

8.12 TAPE/AUX de-multiplex

8.13 Signal-to-noise considerations

8.14 Channel separation correction

8.15 Input selection switches

8.16 Analog inputs supply

8.17 Digitally controlled sampling clock (DCS)

8.18 Survey of the DCS clock settings in different
modes

8.19 Synchronization with the core

8.20 Interference absorption circuit

8.21 IAC testing

9 ANALOG OUTPUTS

9.1 Digital-to-Analog Converters

9.2 Upsample filter

9.3 Volume control

9.4 Power-on mute

9.5 Power-off plop suppression

9.6 Internal reference buffer amplifier of the DAC
(pin V

ref

)

9.7 Internal DAC current reference

9.8 Analog outputs supply

9.9 Clock circuit and oscillator

9.10 Crystal oscillator supply

9.11 External control pins
10 I2S-BUS DESCRIPTION

10.1 I2C-bus control (SCL and SDA pins)

10.2 I2S-bus description

10.3 Communication with external digital audio
sources (DCC + CD-WS/CL/Data pins)

10.4 Communication with external processors and
other devices (EXWS/CL/EXDAT1 and
EXDAT2)

10.5 Relationship between external input and
external output

10.6 RDS decoder (RDSCLK and RDSDAT)

10.7 Clock and data recovery

10.8 Timing of clock and data signals

10.9 Buffering of RDS data

10.10 Buffer interface

10.11 DSP reset

10.12 Power supply connection and EMC

11 LIMITING VALUES
12 THERMAL CHARACTERISTICS
13 DC CHARACTERISTICS
14 AC CHARACTERISTICS
15 I2C-BUS CONTROL AND COMMANDS

15.1 Characteristics of the I2C-bus

15.2 Bit transfer

15.3 START and STOP conditions

15.4 Data transfer

15.5 Acknowledge

15.6 I2C-bus format

16 SOFTWARE DESCRIPTION
17 APPLICATION INFORMATION
18 PACKAGE OUTLINE
19 SOLDERING

19.1 Introduction

19.2 Reflow soldering

19.3 Wave soldering

19.4 Repairing soldered joints

20 DEFINITIONS
21 LIFE SUPPORT APPLICATIONS
22 PURCHASE OF PHILIPS I2C COMPONENTS

1997 May 30 2

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

1 FEATURES

1.1 Hardware

• Bitstream 3rd-order Sigma-Delta Analog-to-Digital
Converters (ADCs) with anti-aliasing broadband input
filters

• Digital-to-Analog Converters (DACs)with four times
oversampling and noise shaping

• Digital stereo decoder

• Improved digital Interference Absorption Circuit (IAC)

• RDS processing with optional 16-bit buffer via separate

channel (two-tuner radio possible)

• Auxiliary analog CD input (CD-walkman, speech,
economic CD-changer, etc.)

• Two separate full I

2

S-bus CD and DCC high

performance interfaces

• Expandable with additional Digital Signal Processors
(DSPs) for sophisticated features through an I2S-bus
gateway

• Audio output short-circuit protected

• I2C-bus controlled

• Analog tape input

• Operating ambient temperature from −40 to +85 °C.

1.2 Software

• Improved FM weak signal processing

• Integrated 19 kHz MPX filter and de-emphasis

• Electronic adjustments: FM/AM level, FM channel

separation and Dolby level

• Baseband audio processing (treble, bass, balance,
fader and volume)

• Dynamic loudness or bass boost

• Stereo one-band parametric equalizer

• Audio level meter for an automatic leveller

(in combination with microcontroller)

• Tape equalization (DCC analog playback)

• Music Search detection for Tape (MSS)

• Pause detection for RDS updates

• Dolby-B tape noise reduction

• Adjustable dynamics compressor

• CD and DCC de-emphasis processing

• Signal level, noise and multi-path detection for RDS

2

(I

C-bus command)

• Improved AM reception.

2 APPLICATIONS

• Car radio

• Car audio systems.

3 GENERAL DESCRIPTION

The SAA7707H performs all the signal functions in front of
the power amplifiers and behind the AM and FMMPX
demodulation of a car radio or the tape input.
These functions are:

• Interference absorption

• Stereo decoding

• RDS decoding

• FM and AM weak signal processing (soft mute, sliding

stereo, etc.)

• Dolby-B tape noise reduction

• The audio controls (volume, balance, fader, tone and

dynamics compression).

Some functions have been implemented in hardware
(stereo decoder, RDS decoder and IAC) and are not freely
programmable. Digital audio signals from external sources

2

with I

S-bus formats are accepted. There are four
independent analog output channels. This enables, in
special system configurations, separate tone and
equalization control for front and rear speakers.

The CDSP contains a basic program that enables a set
with:

• AM/FM reception

• Sophisticated FM weak signal functions

• Music Search detection for Tape (MSS)

• Dolby-B tape noise reduction system

• CD play with compressor function

• Separate bass and treble tone control and fader/balance

control.

For high-end sets with special and more sophisticated
features, an additional Digital Signal Processor (DSP) can
be connected. Examples of such features are:

• Noise-dependent volume control

• 10-band graphic equalizer

• Audio spectrum analyzer on display

• Signal delay for concert hall effects.

1997 May 30 3

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD(tot)

I

DDD(tot)

P

tot

S/N level ADC signal-to-noise

V

iFS

THD total harmonic distortion

V

imc(rms)

RES DAC resolution − 18 − bits
(THD + N)/S total harmonic distortion plus

DR dynamic range of DAC f

DS digital silence of DAC f

f

xtalDSP

total DC supply voltage all supply pins 4.75 5 5.5 V
total DC supply current maximum activity of the

DSP; f

= 36 MHz

xtal

total power dissipation maximum activity of the

DSP; f

= 36 MHz

xtal

RMS value;

ratio

unweighted;

− 160 200 mA

− 0.8 1.1 W

48 54 − dB

B=0to29kHz;
maximum input

ADC signal-to-noise ratio not multiplexed;

81 85 − dB
B = 19 kHz;
V

= 1 V (RMS)

i

multiplexed;

72 76 − dB
unweighted;
B = 19 kHz; 1 V (RMS)

ADC signal-to-noise ratio for
FM-RDS

ADC full-scale input voltage V

pins 62 and 71 to 75
maximum conversion input

RMS value; B = 6 kHz;
unweighted; f

= 4.75 to 5.5 V 1.05V

DDA1

f

= 1 kHz;

i

=57kHz

c

Vi= 1 V (RMS)

56 −−dB

DDA1

1.1V

DDA1

1.15V

DDA1

V

−−71 −61 dB

− 0.03 0.09 %

THD < 1% 1.1 −−V

voltage level pins 62 and
71 to 75 (RMS value)

R

noise-to-signal ratio for DAC
and operational amplifiers

>5kΩAC;

L

Rfb= 2.7 kΩ; fi= 1 kHz;
R

=18kΩ;

ref

V

= 2.8 V (p-p);

oFS

−−70 −60 dB

maximum I2S-bus signal

= 1 kHz; −60 dB;

i

92 102 − dB
A-weighted

= 20 Hz to 17 kHz;

i

−−110 −100 dB

A-weighted

crystal frequency DSP part − 36.86 − MHz

5 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA7707H QFP80 plastic quad flat package; 80 leads (lead length 1.95 mm);

body 14 × 29 × 2.8 mm

1997 May 30 4

SOT318-2

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1997 May 30 5

6 BLOCK DIAGRAM

Car radio Digital Signal Processor (CDSP) SAA7707H

Philips Semiconductors Preliminary specification

V

DACPM

V

DACNM

V

refMPX

V

refRDS

MPXRDS

AM
FM

AUXR

TAPER

TAPEL

AUXL

AMAF

FMMPX

FMRDS

V

DACNL

V

CINT

77
78

70
80

62
4
3
72
74
73
71
75
76
79

33 3032 31

TSCAN

SHTCB

RTCB

SSG

67 68

21

ANALOG
SOURCE

SELECTOR

66

V

SSX

V

V

SSA1

DDX

RDSCLK

V

SSD2

V

DECODER

V

SSD1

522

50 51

ADC

ADC

ADC

RDS

RDSDAT

SSD3

V

V

SSD4

INTERFERENCE

ABSORPTION

CIRCUIT

CRYSTAL

OSCILLATOR

64616065

XTALO

SSD5

V

54

XTALI

SSD6

V

SSD7

3455

QUALITY

23

63

CDCLK

SIGNAL

LEVEL

SIGNAL

24

CDWS

V

SSD8

V

41

DECODER

CDDAT

V

DDD3

V

SSD9

V

DDD2

56

29 5

DDD4

V

DDD5

52

53

49

MUTE

44

SAA7707H

DIGITAL

STEREO

DIGITAL

SOURCE

SELECTOR

DIGITALLY

CONTROLLED

SAMPLING

25

DCCWS

DCCDAT

TEST2

DCCCLK

TEST1

V

SSD10

EXDAT

DEEM

STEREO

45

EXSCL

MSS/P

V

DDA

42

PROCESSOR

43

DIGITAL

SIGNAL

EXDAT2

8

27283635585759464748

EXDAT1

V

DDA1

69

EXWS

37

V

DDO

15

QUADRATURE

INTERFACE

V

SSO

V

14

DAC

I2C-BUS

SCL

SSA

6

SDA

V

V

SSD1

A0

DSPRESET

DDD1

7

40
20

13

18
19
16
17

11
12

9

10

21

263938

EXCLK
V

ref

I

ref(int)

FIOL
FVOL
FIOR
FVOR

RIOL
RVOL
RIOR
RVOR

POM

MBH163

Fig.1 Block diagram.

handbook, full pagewidth

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

7 PINNING

SYMBOL PIN I/O DESCRIPTION

V

DACNL

CINT 2 level ADC switch-mode integrator connector
FM 3 I FM level input; via this pin, the level of the received FM radio signal is fed to the

AM 4 I AM level input; via this pin, the level of the received AM radio signal is fed to the

V

SSD1

V

SSA

V

DDD1

V

DDA

RIOR 9 O analog audio current output for rear right speaker
RVOR 10 O analog audio voltage output for rear right speaker
RIOL 11 O analog audio current output for rear left speaker
RVOL 12 O analog audio voltage output for rear left speaker
I

ref(int)

V

SSO

V

DDO

FIOR 16 O analog audio current output for front right speaker
FVOR 17 O analog audio voltage output for front right speaker
FIOL 18 O analog audio current output for front left speaker
FVOL 19 O analog audio voltage output for front left speaker
V

ref

POM 21 activates the Power-on mute; timing is determined with an external capacitor
V

SSD2

CDCLK 23 I clock input for CD digital audio source (I
CDWS 24 I Word Select input for CD digital audio source (I
CDDAT 25 I left/right data input for CD digital audio source (I
DSPRESET 26 I input to reset DSP core (active LOW)
EXDAT1 27 I external input data channel 1 (front) from extra DSP chip (I
EXDAT2 28 I external input data channel 2 (rear) from extra DSP chip (I
V

SSD9

TSCAN 30 scan control (active HIGH)
A0 31 I
RTCB 32 asynchronous reset test control block (active HIGH)
SHTCB 33 shift clock test control block (active HIGH)
V

SSD7

EXDAT 35 O output data for extra external DSP chip (I
EXSCL 36 O output clock for extra external DSP chip (I
EXWS 37 I/O word select input/output for extra external DSP chip (I

1 − internal ground reference voltage for the level ADC

CDSP, the level information is required to enable correct functioning of the weak
signal behaviour

CDSP
5 − ground supply 1 for the DACs digital circuitry
6 − ground supply for the DACs analog circuitry
7 − positive supply 1 for the DACs digital circuitry
8 − positive supply for the DACs analog circuitry

13 I internal reference current source input for the DACs
14 − ground supply for DAC output operational amplifiers
15 − positive supply for DAC output operational amplifiers

20 I voltage input for the internal reference buffer amplifier of the DAC

22 − ground supply 2 for the digital circuitry

2

S-bus)

2

S-bus)

2

S-bus)

2

S-bus)

2

S-bus)

29 − ground supply 9 for the digital circuitry

2

S-bus selection for slave sub-address

34 − ground supply 7 for the digital circuitry

2

S-bus)

2

S-bus)

2

S-bus)

1997 May 30 6

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PIN I/O DESCRIPTION

SCL 38 I serial clock input (I2C-bus)
SDA 39 I/O serial data input/output (I
EXCLK 40 I external reference clock input to generate 4f

used if the I2S-bus inputs are not suitable

V

SSD8

41 − ground supply 8 for the digital circuitry
STEREO 42 FM stereo indication (active HIGH)
MSS/P 43 FM pause detector/MSS detector (active HIGH); also for IAC trigger output
MUTE 44 I MUTE input pin (active LOW); only for FM mode
DEEM 45 de-emphasis; CD and DCC (active HIGH) (I
DCCCLK 46 I DCC digital audio source clock input (I
DCCWS 47 I DCC digital audio source Word Select input (I
DCCDAT 48 I DCC digital audio source left/right data input (I
V
V
V
V
V
V
V
V

DDD3
SSD3
SSD4
DDD4
DDD5
SSD5
SSD6
DDD2

49 − positive supply 3 for the digital circuitry

50 − ground supply 3 for the digital circuitry

51 − ground supply 4 for the digital circuitry

52 − positive supply 4 for the digital circuitry

53 − positive supply 5 for the digital circuitry

54 − ground supply 5 for the digital circuitry

55 − ground supply 6 for the digital circuitry

56 − positive supply 2 for the digital circuitry
TEST1 57 test pin 1 (this pin should be left open-circuit)
V

SSD10

58 − ground supply 10 for the digital circuitry
TEST2 59 test pin 2 (this pin should be left open-circuit)
RDSCLK 60 I/O radio data system bit clock input/output
RDSDAT 61 O radio data system data output
MPXRDS 62 I in FM mode, selects between FMMPX and RDSMPX input signal to the MPX

decimation filter
XTALI 63 I crystal oscillator input; can also be used as forced input in slave mode
XTALO 64 O crystal oscillator output
V

DDX

V

SSX

V

SSG

V

SSA1

V

DDA1

V

refMPX

65 − positive supply crystal circuitry
66 − ground supply crystal circuitry
67 − ground guards for ADCs
68 − analog ground supply for ADCs
69 − analog positive supply for ADCs

70 I common mode reference voltage input for MPX ADC and buffers
AUXL 71 I analog input for auxiliary left signal
AUXR 72 I analog input for auxiliary right signal
TAPEL 73 I analog input for tape left signal
TAPER 74 I analog input for tape right signal
AMAF 75 I analog input for AM audio frequency
FMMPX 76 I analog input for FM multiplex signal

2

C-bus)

2

S-bus)

and fas synchronization; to be

as

2

S-bus)

2

S-bus)

2

S-bus)

1997 May 30 7

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PIN I/O DESCRIPTION

V

DACPM

V

DACNM

FMRDS 79 I analog FMMPX input for RDS decoding
V

refRDS

77 I supply voltage for the DACs switch capacitor of the FMMPX ADC and

FMRDS ADC

78 I ground supply for the DACs switch capacitor of the FMMPX ADC and

FMRDS ADC

80 I common mode reference voltage input for RDS ADC, level ADC and buffers

1997 May 30 8

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

DDX

SSX

SSG

SSA1

DDA1

AUXL
71

refMPX

V
70

V

V

V

V

V

69

68

67

66

65

64

XTALO
XTALI

63
62

MPXRDS

61

RDSDAT

60

RDSCLK

59

TEST2
V

58

SSD10

57

TEST1
V

56

DDD2

V

55

SSD6

V

54

SSD5

V

53

DDD5

V

52

DDD4

V

51

SSD4

V

50

SSD3

V

49

DDD3

48

DCCDAT

47

DCCWS
DCCCLK

46

DEEM

45
44

MUTE

43

MSS/P
STEREO

42

V

41

SSD8

handbook, full pagewidth

V

DACNL

V

SSD1
V

V

DDD1
V

RIOR

RVOR

RVOL

I

ref(int)
V

V

FVOR

FVOL

V

SSD2

CDCLK

CDWS

CINT

FM
AM

SSA

DDA

RIOL

SSO

DDO

FIOR

FIOL

V

ref

POM

refRDS

V

FMRDS

80

79
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

DACNM

V

78

DACPM

V

77

AMAF

FMMPX
76

75

TAPER

TAPEL

74

73

SAA7707H

AUXR
72

25

26

27

28

29

30

31
A0

TSCAN

CDDAT

EXDAT1

DSPRESET

SSD9

V

EXDAT2

Fig.2 Pin configuration.

1997 May 30 9

32

RTCB

33

SHTCB

34

SSD7

V

35

EXDAT

36

EXSCL

37

EXWS

38

SCL

39

SDA

40

MBH162

EXCLK

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

8 FUNCTIONAL DESCRIPTION

8.1 Signal path for level information

An FM and AM level input is implemented for FM weak
signal processing [for AM, FM and RDS search purposes
(absolute level and multi-path)]. A DC input signal is
converted by a bitstream 1st-order Sigma-Delta
analog-to-digital converter and then filtered by a
decimation filter.

The input signal has to be obtained from the radio part.
Two different circuits for AM and FM reception are
possible:

1. A circuit with two separate input signals, one for FM
level and one for AM level

2. A combined circuit with AM and FM level information
on the FM level input. The AM level input can then be
connected to another signal, which can be converted
in the non-radio mode.

The input is selected via the input selector control register.
The input signal for level control must be in the range of

0 to 5 V. The 11-bit level ADC converts this input voltage
in steps with a resolution better than 10 mV over the 5 V
range. The tolerance on the gain is less than 10%.
The MSB is always logic 0, to represent a positive level.

The decimation filter reduces the bandwidth of the
incoming signal to a frequency range of 0 to 29 kHz, with
a resulting sampling frequency (f

) of 76 kHz.

s

The response curve is illustrated in Fig.3.
The level information is sub-sampled by the DSP core to

obtain a field strength and a multi-path indication.
These values are stored in the coefficient or data RAM.
They can be read and used in other microcontroller
programs via the I2C-bus.

8.2 Level ADC switch mode integrator (pin CINT)

The level ADC has an internal current summation point of
the input level and the switch capacitor DAC. When used
as an integrator, an external capacitor of 1000 pF should
be connected between this pin and the analog ground at
pin V

. The summation voltage is used as an input for

SSA1

the analog-to-digital comparator level.

8.3 Internal ground reference for the level ADC
(pin V

DACNL

)

This pin serves as the internal ground reference for the
switch capacitor DAC and the level ADC and has to be
connected to the analog ground (pin V

SSA1

).

10

handbook, full pagewidth

α

(dB)

0

−10

−20

−30

−40

−50

−60

0

2010 30 40 50 60 70

Fig.3 Frequency response of the level ADC and decimation filter.

f (kHz)

MBH164

80

1997 May 30 10

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

8.4 Common mode reference voltage for RDS
ADC, ADC level and buffers (pin V

refRDS

)

The middle reference voltage of the RDS ADC can be
filtered via this pin. This middle reference voltage is used
as a positive reference for the level ADC of the switch
capacitor DAC and as half supply reference for the RDS
ADC, the switch capacitor DACs and buffers. An external
capacitor (connected to V

) prevents crosstalk

SSA1

between the switch capacitor DACs of the RDS ADC, level
ADC and buffers, and improves the power supply rejection
ratio.

8.5 Signal path for audio/MPX and stereo decoder

The SAA7707H has four analog audio source inputs; two
single-multiplex channel inputs for AM and FM radio and
two stereo inputs for tape and auxiliary. The auxiliary input
can be used for functions such as an analog CD changer
or speech applications. The stereo inputs are multiplexed
so that they can share the same filters as the multiplexed
FM signal. The selection between the AM, FM, TAPE and
AUX input is made via the input selector control register.

The input signal behind the source selector is digitized by
a bitstream 3rd-order Sigma-Delta ADC. The first
decimation filter reduces the sample rate. This is followed
by the sample-and-hold switch of the IAC and the 19 kHz
regeneration circuit. From here, the wide-band noise
detector signal HP2 (High-Pass 2) with a frequency range
of 60 to 240 kHz is derived. A second decimation filter
reduces the output of the IAC to a lower sample rate.

This filter has two outputs, one for the multiplex signal with
a frequency range of 0 to 60 kHz (low-pass) and one for
the small-band noise detector signal HP1 (High-Pass 1)
with a frequency range of 60 to 120 kHz. The overall
low-pass frequency response of the decimation filters is
illustrated in Fig.4.

In the FM mode, the RDS ADC can be used as an input for
the MPX decimation filter. This can be selected via the
RDSMPX input at pin 62.

The outputs from this signal path to the DSP, which are all
at a sample frequency of 38 kHz, are as follows:

• Pilot presence indication: Pilot-I. This 1-bit signal is

LOW for a pilot frequency deviation of less than 4 kHz
and HIGH for a pilot frequency deviation greater than
4 kHz. It is AND locked on a pilot tone.

• Pilot quality indication: Pilot-Q. This 10-bit signal

contains information about the signal quality and is
derived from the quadrature component of the pilot-I
signal.

• ‘Left’ and ‘Right’: This is the 18-bit output of the stereo
decoder after the matrix decoding. For AM reception,
the ‘Right’ signal contains the AM-mono signal. For tape
or auxiliary signals, the output of the stereo decoder
contains sum and difference signals, but with other
crosstalk properties than on FM. Therefore, a different
matrix correction, as shown in Table 1, has to be applied
to these signals in the DSP program. The overall
frequency response of the demultiplexed signal at the
output of the stereo decoder is illustrated in Fig.5.

Table 1 Overview of the signals to the CDSP

MODE LEFT RIGHT

AM 0 mono

1

FM

TAPE/AUX

⁄2(R − L) R + L

1

⁄2(R + L) × 4/π R + L

Apart from the aforementioned theoretical response, the
non-flat frequency response of the ADC must also be
compensated for in the DSP program.

8.6 Mono/stereo switching

After division, the Digitally Controlled Sampling (DCS)
clock generates a clock signal with a frequency which is a
multiple of 19 kHz plus or minus a few Hertz. For mono
reception, the DCS circuit generates a preset frequency of
n × 19 kHz ±2 Hz. For stereo reception, the frequency is
exactly n × 19 kHz (DCS locked to n × pilot tone).
The detection of the pilot and the stereo indication is
performed in the DSP program.

8.7 The automatic lock system

The VCO operates at 19 kHz ±2 Hz exactly for no-pilot.
For stereo reception, the phase error is zero for a pilot tone
with a frequency of exactly 19 kHz. Therefore, no switch is
required to preset the clock to 19 kHz. With auxiliary
sources (tape, CD, etc.), the DCS circuit has to be preset
to a fixed value.

8.8 Input sensitivity for FM

The FM input sensitivity is optimally designed for an FM
front-end with an output voltage of 200 mV (RMS) at a
modulation depth of 22.5 kHz of a 1 kHz tone. Due to the
full-scale 1.2 V (RMS) handling capacity of the ADC, the
maximum allowed modulation depth of a transmitter, for a
THD of 10%, is 135 kHz. Full performance is possible for
transmitters with a modulation depth of up to 110 kHz.

1997 May 30 11

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

10

handbook, full pagewidth

α

(dB)

−110

−130

−150

0

−10

−30

−50

−70

−90

0

10050 150 200 250 300 350

Fig.4 Overall frequency response multiplex ADC and decimation filters.

MBH165

f (kHz)

500400 450

20

handbook, full pagewidth

α

(dB)

0

−20

−40

−60

−80

−100

0

2010 30 40 50 60 70

Fig.5 Transfer of MPX signal at the output of the stereo decoder.

1997 May 30 12

f (kHz)

MBH166

80

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

8.9 Common mode reference voltage for MPX ADC
and buffers (pin V

refMPX

)

The middle reference voltage of the MPX ADC can be
filtered via this pin. This middle reference voltage is used
as a half supply voltage reference for the MPX ADC,
switch capacitor DACs and buffers. An external capacitor
(connected to V

) prevents crosstalk between the

SSA1

switch capacitor DACs and buffers and improves the
power supply rejection ratio.

8.10 Supply voltages for the switch capacitor DACs
of the FMMPX ADC and FMRDS ADC
(pins V

DACNM

and V

DACPM

)

These pins are used as ground and positive supply voltage
reference for the MPX ADC, RDS ADC and the switch
capacitor DACs. For optimum performance they must be
connected directly to V

10

handbook, full pagewidth

α

(dB)

0

−10

−30

SSA1

and V

DDA1

.

8.11 Noise level

The High-Pass 1 (HP1 or narrow-band noise level filter)
output of the second MPX decimation filter, in a frequency
band from 60 to 120 kHz, is detected with an envelope
detector and decimated to a frequency of 38 kHz.

The response time of the detector is 100 ms.
Another option is the High-Pass 2 (HP2 or wide-band
noise level filter). This output from the first MPX decimation
filter is in a frequency band from 60 to 240 kHz. It has the
same properties as the HP1 and is also decimated to
38 kHz. Which signal is used (HP1 or HP2) is determined
by the input selector control register. The noise level can
be detected and filtered in the DSP core and can be used
to optimize the FM weak-signal processing. The transfer
curves of both filters before decimation are illustrated in
Fig.6.

MBH167

−50

−70

−90

−110

−130

−150

0

(1) Narrow-band noise level filter.
(2) Wide-band noise level filter.

10050 150 200 250 300 350

Fig.6 Frequency response of noise level before decimation.

1997 May 30 13

(1)(2)

f (kHz)

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

8.12 TAPE/AUX de-multiplex

The auxiliary and tape inputs also use the stereo decoder.
Because of this, the left and right channels are multiplexed
with a 38 kHz square wave to obtain a signal similar to the
FM multiplexed signal. Auxiliary inputs can be e.g.
TV-sound, remote players (tape deck, CD-changer with
analog output etc.). The signal-to-noise ratio from such
sources is limited by the ADC in the SAA7707H (>75 dB).
The decimation filter of the ADC attenuates the harmonic
signals from this stereo encoder. For an optimum channel
separation, the 38 kHz switch signal has to be phase
corrected to compensate for the delay of the ADC and
decimation filters. This can be adjusted with the 3-bit group
delay compensation in the IAC control register. Signal
frequencies above 19 kHz at the input of the multiplexer
are converted to the audio base-band and are therefore
not allowed.

8.13 Signal-to-noise considerations

Due to the pre-emphasis of FM broadcasts, the theoretical
signal-to-noise ratio is approximately 3 dB higher for FM
stereo in comparison with multiplexed inputs.

To avoid aliasing into the tape channel, the tape noise from
the pre-amplifier must be attenuated before
analog-to-digital conversion with a 1st-order 10 kHz
low-pass filter. The frequency response is equalized after
the stereo decoder in the DSP program before the Dolby
decoder software. Using this filter, the signal-to-noise ratio
of this channel is degraded by 3 dB. This results in a
signal-to-noise ratio that is overall 6 dB lower than a tape
input with respect to FM stereo.

8.14 Channel separation correction

The channel separation is approximately 50 dB at 1 kHz
and 35 dB at 15 kHz. Because the frequency response of
the ADC has some deviation from the flat curve around
38 kHz, a perfect channel separation cannot be obtained.
Therefore, the de-multiplexed signal is corrected for
crosstalk in the DSP program.

8.15 Input selection switches

A schematic diagram of the input selection is illustrated in
Fig.5. The input selection is controlled by bits in the input
selector control register. The relationship between these
bits and the switches is indicated in Table 2.

Table 2 Analog input selection

2

I

C-BUS SELECTION

BIT

AM/FM

AUX/

RADIO

TAPE/

AUX

SFM SAM SAUX SAUX

SWITCH

00x1000
10x0100

x100010
x110001

8.16 Analog inputs supply

The analog input circuit has its own separate power supply
connections to allow maximum filtering. These pins are
V

for the analog ground and V

SSA1

power supply. V

is the connection to the guard ring

SSG

for the analog

DDA1

which isolates the analog part from the digital filters.
This pin has to be connected to the analog ground.

8.17 Digitally controlled sampling clock (DCS)

The crystal clock generates a continuous clock signal for
the internal DSP core. In the radio mode, the stereo
decoder, the RDS decoder, the ADCs and the level
decimation filters have to run synchronously with the
19 kHz pilot. Therefore, a clock signal with a controlled
frequency with a multiple of 19 kHz
(9.728 MHz = 512 × 19 kHz) is required.

In the SAA7707H, the patented method of a
non-continuous digitally controlled sampling clock has
been implemented. A frequency of 9.728 MHz is
generated by a special dividing mechanism of the master
crystal clock. Since the dividing mechanism is fixed, only a
crystal frequency of 36.86 MHz can be used.

The DCS system is controlled by up/down information
from the stereo decoder. For mono transmissions, the
DCS clock is still controlled by the stereo decoder loop.
The output keeps the DCS free-running at a multiple
frequency of 19 kHz ±2 Hz. In TAPE/AUX and AM mode,
the DCS clock must always be put in preset mode by the
input selector control register.

1997 May 30 14

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

8.18 Survey of the DCS clock settings in different modes

The DCS clock behaves as shown in Table 3.

Table 3 DCS clock/mode

MODE DCS CLOCK

FM stereo locked on 19 kHz pilot of received

FM signal
FM mono free running
AM analog inputs

TAPE/AUX

2

I

C-bus inputs

DCC/CD

8.19 Synchronization with the core

A 38 kHz synchronization signal is derived from the DCS
clock and divided by 256.

If the external I
of the Word Select input signal is used to synchronize with
the core.

2

S-bus DCC CD is selected, the rising edge

fixed preset

fixed preset

8.20 Interference absorption circuit

The Interference Absorption Circuit (IAC) detects and
suppresses ignition interference. This hardware IAC is a
modified and digital version of the analog circuit that has
already been in use for many years.

The input signal to the IAC circuit is derived from the output
signal of the decimation filter. The interference detector
analyses the high frequency content of this MPX signal.
The discrimination between interference pulses and other
signals is performed by a special Philips patented fuzzy
logic-like algorithm and is based on probability
calculations. This logic will send appropriate pulses to an
MPX mute switch.

At Power-on, the nominal setting for an IAC with good
performance characteristics is selected (all IAC control bits
are 0). If an adjustment is needed, the characteristics can
be adapted as described in the application manual.

8.21 IAC testing

The internal IAC trigger signal is visible on the MSS/P pin
(pin 43) if the IAC trigger output bit of the IAC control
register is set. In this mode, the effect of the parameter
settings on the IAC performance can be verified.

1997 May 30 15

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

0

handbook, full pagewidth

FM
AM

TAPER

TAPEL

SAMFM

1
0

0

1

STAPE

0

1
0

CLMPX

1

ADC

ADC

level

AUXR

AUXL

AM/FM

FMMPX

FMRDS

1

SAUX

0

1
0

SAM

1
0

1

SFM

0

1

0

SINTEXT

1

ADC

Fig.7 Schematic diagram of input selection.

0
1

RDS_MPX

MBH168

MPX

RDS

• The SAMFM switch is controlled by the SEL-LEV-AM/FM bit

• The SINTEXT switch is controlled by the SEL-RDS-EXT/INT bit

• The CLMPX switch is controlled by the 38 kHz clock derived from the DCS, but is not active in FM and AM mode.

In the FM radio mode, the MPXRDS pin overrides the following switches when set to logic HIGH:
If SEL-AM/FM = 0 and SEL-AUX/RADIO = 0 and pin MPXRDS = 1, then SFM = 0, SINTEXT = 1 and MPXRDS = 1.

1997 May 30 16

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

9 ANALOG OUTPUTS

9.1 Digital-to-analog converters

Each of the four low-noise high dynamic range DACs
consists of a 15-bit signed magnitude DAC with current
output, followed by a buffer operational amplifier.

The five higher bits (bits 10 to 14) are used to control the
total coarse current ratio of the 32 coarse current sources
via a thermometer decoder. The nine lower bits
(bits 1 to 9) are derived from a 512 transistor matrix, which
acts as a passive 9-bit current divider for one of the coarse
currents. The MSB (bit 15) is used as a sign bit for the
signed magnitude converter and controls the direction of
the total output current. A separate converter is used for
each of the four audio output channels. The value of each
coarse current is adjusted by the current through the
external resistor connected to pin 13 (I

ref(int)

).

Each converter output is connected to the inverting input
of one of the four internal CMOS operational amplifiers.
The non-inverting input of this operational amplifier is
connected to the internal reference voltage. Together with
an external resistor, the current-to-audio output voltage
conversion is achieved.

For external digital sources (DCC and CD), a sample
frequency from 32 to 48 kHz is possible. The sample

2

frequency is automatically adjusted to the I

S-bus input by
dividing the external bit clock. This clock is normally
present in a DCC CD application. An internal digital PLL
divides this clock with the integer factor needed to obtain
the 4fas word clock. Master synchronization of this divided
clock signal is obtained with a reset of the divider on the
Word Select signal (trailing edge) of the I2S-bus.

In the application, the I2S-bus signal from the external
source should fulfil the following requirements:

• There is a continuous (is part of the basic I2S-bus

specification) n × 4fas (4 < n < 128) I2S-bus bit clock or

• If the I2S-bus bit clock is not continuous, another n × 4f

(4 < n < 128) continuous clock signal has to be
connected to the EXCLK pin (pin 40). The divide
external clock mode has to be selected using the input
selector control register.

The range of the internal 7-stage programmable divider of
the PLL, to obtain 4fas, is large enough to handle 16-bit
I2S-bus signals as well as master clocks up to 22 MHz
from digital sources (CD, DCC, R-DAT and EBU interface)
without any clock regeneration.

as

9.2 Upsample filter

To reduce spectral components above the audio band, a
fixed 4 times oversampling and interpolating 18-bit digital
IIR filter is used. It is realized as a bit serial design and
consists of two consecutive filters. The data path in these
filters is 22 bits, to prevent overflow and to maintain a
theoretical signal-to-noise ratio greater than 105 dB.
The filters give an attenuation of at least 29 dB. The filter
is followed by a 5 bit 1st-order noise shaper, to expand the
dynamic range to more than 105 dB.

The band around multiples of the sample frequency of the
DAC (4f

) is not affected by the digital filter. A capacitor

as

can be added in parallel with the output resistor at the DAC
output to further attenuate this out-of-band noise to an
acceptable level.

The overall frequency spectrum at the DAC audio output
without external capacitor/low-pass filter for the audio
sampling frequencies (fas) of 38 kHz is illustrated in Fig.8.
The detailed spectrum around fas is illustrated in Fig.9 for
an fas of 38 kHz, 44.1 kHz and 48 kHz. The pass-band
bandwidth (at −3 dB) is1⁄2fas.

The word clock for the upsample filter (4fas) is derived from
the audio source timing. If the internal audio source is
selected, the sample frequency is fixed at 38 kHz.

The PLL is used in a free-running mode to ensure that jitter
on the I2S-bus signals (due to asynchronous clocking of
the I2S-bus signals by the DSP core) will not influence the
total harmonic distortion of the audio signal on the analog
DAC part. This will, however, only operate if there is no
jitter on the bit clock or when a crystal clock is used.

9.3 Volume control

The total volume control has a dynamic range of more than
100 dB. With the signed magnitude noise-shaped 15-bit
DAC and the internal 18 bit registers of the DSP core, a
useful digital volume control range of 100 dB is possible by
calculating the corresponding coefficients. The step size is
freely programmable and an additional analog volume
control is not needed in this design. The signal-to-noise
ratio of the audio output, at full-scale, is determined by the
total 15 bits of the converter.

The noise at low outputs is fully determined by the noise
performance of the DAC. Since it is a signed magnitude
type, the noise at digital silence is also low.
The disadvantage is that the total THD is higher than
conventional DACs. The typical signal and noise levels as
a function of the output level and the typical signal-to-noise
plus THD as a function of the output level are illustrated in
Fig.10.

1997 May 30 17

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

9.4 Power-on mute

To avoid any uncontrolled noise at the audio outputs after
Power-on of the IC, the reference current source of the
DAC is switched off. The capacitor connected to pin 21
(POM) determines the time after which this current has a
soft switch-on. Consequently, at Power-on, the current
audio signal outputs are always muted. The voltage output
signals will show a small jump at switch-on due to the
asymmetrical voltage supply of the output operational
amplifiers. These types of disturbances must be
eliminated via the application set-up. The output has to be
set to digital silence before the POM pin is at logic HIGH.
This is achieved via the DSP program control and/or a zero
volume setting. The pin is internally connected to V

DDO

with a high-ohmic resistor.

9.5 Power-off plop suppression

To avoid plops in a power amplifier, the supply voltage of
the analog part of the DAC can be fed via a Schottky diode
and an extra capacitor. In this situation, the output voltage
will decrease gradually, allowing the power amplifier some
extra time to switch off without audible plops.

9.6 Internal reference buffer amplifier of the DAC
(pin V

ref

)

Using two internal resistors, half of the supply voltage
(V

) is obtained and coupled to an internal buffer.

DDO

This reference voltage is used as a DC voltage for the
output operational amplifiers and as a reference voltage
for the DAC. In order to obtain the lowest noise and to have
the best ripple rejection, a filter capacitor has to be added
between this pin and ground.

9.7 Internal DAC current reference

As a reference for the current at the DAC current source,
a current is drawn from pin 13 (I
The voltage at this pin is1⁄2V

DDO

) to the V

ref(int)

(typically 2.5 V).

SSO

ground.

The maximum DAC current is equal to 4.5 times this
current. When a reference resistor of 18 kΩ is used, the
reference current from the DAC is 125 µA. This results in
a peak current from the four current outputs of

4.5 × 125 = 562.5 µA.

The operational amplifiers have the V

SSO

and V

DDO

pins
as ground and positive supply. These pins also provide the
supply for the reference circuits. The analog DAC part
uses the V

SSA

and V

pins as ground and positive

DDA

supply. The upsample filter and digital part of the DAC
share the V

SSD1

and V

as ground and positive supply

DDD1

connections.

9.9 Clock circuit and oscillator

The SAA7707H has an on-board crystal clock oscillator.
The schematic of this Pierce oscillator is illustrated in
Fig.11. The active element needed to compensate for the
loss resistance of the crystal is the block ‘Gm’. This block
is placed between the XTAL (output) and the OSC (sense)
pins. The gain of the oscillator is internally controlled by the
AGC block; this prevents excessive power loss in the
crystal. The higher harmonics are then as low as possible.

The signal on the XTAL pin is amplified and divided by two.
This 18.43 MHz signal is then used as the DSP clock
signal (PH2). For the high frequency, as used in the
SAA7707H, normally only third overtone crystals are
available. With an external LC notch filter at the
fundamental frequency, oscillation at this frequency can
be avoided.The crystal frequency is chosen in such a way
that the harmonics are outside the normal FM band.
The crystal frequency used is 36.86 MHz.

9.10 Crystal oscillator supply

The power supply connections for the oscillator are
separate from the other supply lines. This is to minimize
the feedback from the ground bounce of the chip to the
oscillator circuit. The V
supply and the V

DDX

pin (pin 66) is used as ground

SSX

pin (pin 65) as positive supply.

9.11 External control pins

For external control, two input pins have been
implemented. The status of these pins can be changed by
applying a logic level, and is recorded in the internal status
register. The functions of each pin are as follows:

•

MUTE (pin 44). Mute input (0 = MUTE)

• DEEM (pin 45). This pin activates the de-emphasis for

CD and DCC. (1 = de-emphasis on).

9.8 Analog outputs supply

For an optimum signal-to-noise performance, supply ripple
rejection and to suppress switch-off plops, the output
operational amplifiers, the analog part of the DACs and the
upsample filter plus digital part have separate power
supply connections.

1997 May 30 18

To control external devices, two output pins are
implemented. The status of these pins is controlled by the
DSP program. The functions of each pin are as follows:

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

• STEREO (pin 42): Indicates whether an FM broadcast is in stereo (1 = stereo)

• MSS/P (pin 43): Indicates a pause in FM or tape search mode (1 = pause). This is also the IAC trigger output for IAC

alignment if the corresponding I2C-bus bit is set.

handbook, full pagewidth

5
0

−5

α

(dB)

−15

−25

−35

−45

−55

−65

0

10

handbook, full pagewidth

α

(dB)

0

10050 150 200 250 300 350

Fig.8 Overall frequency spectrum audio output (fas= 38 kHz).

MBH169

f (kHz)

MBH170

500400 450

−10

−20

−30

−40

−50

0

10000 20000 30000

Fig.9 Detailed frequency spectrum of audio output.

1997 May 30 19

f (Hz)

40000
464200 11605 23211 34815
505280 12632 25263 37895

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

handbook, full pagewidth

100

S/(N+THD)

and

S/N (dB)

80

60

40

20

0

(1) Signal-to-noise.
(2) Signal-to-noise + total harmonic distortion.

MBH171

(1)

(2)

0−10−20−30−40−50−60−70−80−90−100

output level (dB)

Fig.10 Typical signal-to-noise level and signal-to-noise plus THD as a function of output level.

handbook, full pagewidth

AGC

ON CHIP

OFF CHIP

G

m

63 64

R

bias

C x 1 C x 2

XTALOSC

/2

PH2

65 66
V

DDX

Fig.11 Schematic diagram of the oscillator circuit.

V

SSX

MBH172

1997 May 30 20

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

10 I2S-BUS DESCRIPTION

2

10.1 I

C-bus control (pins SCL and SDA)

For external control of the SAA7707H, a standard I2C-bus
is implemented. There are two different types of control
instructions:

• Instructions to control the DSP program, programming
the coefficient RAM and reading the values of
parameters (level, multi-path etc.)

• Instructions controlling the DATA flow, such as source
selection, IAC control and clock speed.

10.2 I

2

S-bus description

For communication with external digital sources and/or
additional external processors, the I2S-bus digital interface
is used. It is a serial 3-line bus, having one line for Serial
Data (SD), one line for Serial Clock (SCK) and one line for
the Word Select (WS). For external processors, the CDSP
acts as a master transmitter; for external digital sources
the CDSP acts as a slave. The communication with the
external processor and external digital sources are
separated, to allow both features at the same time.

Figure 12 shows an extract of the Philips I2S-bus
specification interface report regarding the general timing
and format of the I2S-bus. Word select logic 0 means left
channel word; word select logic 1 means right channel
word.

The serial data is transmitted in twos complement with the
MSB first. One clock period after the negative edge of the
Word Select line, the MSB of the left channel is
transmitted. Data is synchronized with the negative edge
of the clock and latched at the positive edge.

As inputs from an external processor for the four audio
channels, two data lines have been implemented.

The Word Select line automatically determines the
SAA7707H sampling frequency.

Using the Digital Source Selector (see Fig.1), one of the
three possible input sources is selected. The selected
audio data channels are input to two 18-bit wide memory
mapped I/O registers of the DSP named Input Left and
Input Right.

Except for the 4f

pulse to control the upsample filter

as

(see Section 9.2), other synchronization signals such as
internal Word Select are derived from the I2S-bus input
signals.

The input bit clock is used as a bit clock for the external
processor. As a consequence, a clock pulse input signal
with less than 18 bits will result in a communication with an
external processor of the same number of bits. In this
event, the trailing bits of the 18-bit input registers will be
zero.

If the I2S-bus driver outputs of the external digital source
ICs have 3-state outputs, they can all be connected on one
single I2S-bus input.

10.4 Communication with external processors and other devices (EXWS/CL/EXDAT1 and EXDAT2)

For communication with external processors, delay lines
or other I

2

S-bus controllable devices, a complete

dual-channel 18-bit output bus is implemented.
The SAA7707H acts as the master transmitter and the

external device has to be synchronized with the Word
Select line.

As input for the processed data, two data input lines have
been implemented that are processed synchronously with
the data output to the external processor (see Table 4).
This enables, in total, a feedback of two stereo audio
channels.

10.3 Communication with external digital audio sources (DCC + CD-WS/CL/Data pins)

For communication with external digital audio sources, two
additional I

2

S-bus inputs are available. They each have
clock, data and Word Select input lines with a maximum
useful data length of 18 bits. The external source is master
and supplies the clock. The input selection and port
selection is controllable via the input selector control
register. The DSP program is synchronized with the
external source via the Word Select signal.

The input allows a variety of clock frequencies, sample
frequencies and word lengths.

1997 May 30 21

For this communication, the DSP core has the following
18-bit memory mapped I/O registers available:

Table 4 DSP core I/O registers

INPUT OUTPUT

EXDAT1 left/right
EXDAT2 left/right

EXDAT left/right

The DSP program moves data from the two external

2

I

S-bus data output registers to the external processor and
reads it back from the two or four external I2S-bus data
input registers. The hardware of the bus can be enabled by
the input control register.

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

To minimise electro magnetic interference (EMI), the
output has to be disabled if the output is not used.

The timing diagram of the communication is illustrated in
Fig.13.

10.5 Relationship between external input and external output

The stereo decoder output has an internal I
with 32 clock pulses per channel for 18 valid and 14 zero
data bits. Providing that the stereo decoder output is used,
the communication with the external processor will also
have 32 clock pulses per channel for 18 valid and 14 zero
data bits.

When an external digital source is selected, the number of
valid bits and clock pulses of this source determines the
output to the external processor. This relationship is
shown in Table 5.

Table 5 Relationship between external input and

external output.

INPUT

CLOCK

BITS

>32 ≥18 32 18
≥18 and ≤32 ≥18 as input 18
≥18 and ≤32 <18 as input 18

<18 <18 as input as input

INPUT

DATA

BITS

OUTPUT

CLOCK

BITS

2

S-bus format

OUTPUT

DATA

BITS

In this way, it can be performed without interruption of the
audio program. The MPX signal from the main tuner of the
car radio can be connected to this RDS input via the
built-in source selector.

The input selection is controlled by the input selector
control register.

For FM stereo reception, the clock of the total chip is
locked to the stereo pilot (19 kHz multiple). For FM mono,
the DCS loop keeps the DCS clock around the same
19 kHz multiple. In all other cases, such as AM reception
or tape, the DCS circuit has to be set to a preset position.
Under these conditions, the RDS system is always clocked
by the DCS clock in a 38 kHz (4 × 9.5 kHz) based
sequence.

10.8 Timing of clock and data signals

The timing of the clock and data output is derived from the
incoming data signal. Under stable conditions, the data will
remain valid for 400 µs after the clock transition.
The timing of the data change is 100 µs before a positive
clock change. This timing is suitable for positive and
negative triggered interrupts on a microcontroller.
The RDS timing is illustrated in Fig.14.

During poor reception, it is possible that errors in phase
may occur. Consequently the duty cycle of the clock and
data signals will vary from a minimum of 0.5 times to a
maximum of 1.5 times the standard clock periods.
Normally, errors in phase do not occur on a cyclic basis.

10.6 RDS decoder (RDSCLK and RDSDAT)

The RDS decoder recovers the additional inaudible RDS
information transmitted by FM radio broadcasting.
The (buffered) data is provided as an output for further
processing by a suitable decoder. The operational
functions of the decoder are in accordance with EBU
specification

The RDS decoder has three different functions:

1. Clock and data recovery from the MPX signal

2. Buffering of 16 bits, if selected

3. Interfacing with the microcontroller.

10.7 Clock and data recovery

The RDS chain has a separate input. This enables RDS
updates during tape play and also the use of a second
receiver for monitoring the RDS information of signals from
another transmitter (double tuner concept).

1997 May 30 22

EN 50067

.

10.9 Buffering of RDS data

The repetition frequency of RDS data is approximately
1187 Hz. This results in an interrupt on the microcontroller
every 842 µs. In a second mode, the RDS interface has a
double 16-bit buffer.

10.10 Buffer interface

The RDS interface buffers 16 data bits. Each time 16 bits
are received, the data line is pulled down and the buffer is
overwritten. The control microcontroller has to monitor the
input data line at least every 13.5 ms. This mode is
selected by the input selector control register.
The interface signals from the RDS decoder and the
microcontroller in the buffer mode are illustrated in Fig.15.
When the buffer is filled with 16 bits, the data line is pulled
down.

The data line will remain LOW until reading from the buffer
is started, by pulling down the clock line. The first data bit
is clocked out.

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

After 16 clock pulses, the buffer is read and the data line is
set HIGH until the buffer is filled again. The microcontroller
stops communication by pulling the clock line HIGH.

The data is written out just after the clock HIGH-to-LOW
transition. The data is valid when the clock is HIGH.

When a new 16-bit buffer is filled before the other buffer is
read from, that buffer will be overwritten and the old data
will be lost.

10.11

DSP reset

The reset pin (DSP) is active LOW and has an internal
pull-up resistor. To allow a proper switch-on of the supply
voltage, a capacitor should be connected between this pin
(pin 26) and V

. The value of the capacitor is such that

SSD

the SAA7707H will remain in reset as long as the power
supply is not stabilized. A more or less fixed relationship
between the DSP reset and the POM (pin 21) time
constant is obligatory. The voltage on the POM pin
determines the current flowing in the DACs. At 0 V
(at pin 21), the DAC currents are zero and therefore the
DACs output voltages are also zero. At 5 V, the DAC
currents are at their nominal (maximum) value.

Long before the DAC outputs reach their nominal output
voltages, the DSP must be in the working mode (to reset
the output register) therefore, the

DSP time constant must
be shorter than the POM time constant. For advised
capacitors, see Figs. 24 and 25.

The DSP reset has the following functions:

• The bits of the IAC control register are set to logic 0

• The bits of the input selector control register are set to

logic 0

• The program counter is set to address $0000.
When the level on the DSP is at logic HIGH, the DSP

program starts to run.

10.12 Power supply connection and EMC

The digital part of the SAA7707H has 5 positive supply
lines (V
(V

SSD1

DDD1

to V

to V

SSD10

) and 10 ground connections

DDD5

). To minimize radiation, the SAA7707H
should be put on a double-layer PCB with, on one side, a
large ground plane. The ground supply lines should have
a short connection to this ground plane. A coil/capacitor
network in the positive supply line can be used as a high
frequency filter.

handbook, full pagewidth

SCK

WS

SD

SCK

SD

WS

MSB

LEFT

T

cy

tLC≥0.35 T

tsr≥0.2 T thr≥0

tHC≥0.35 T

Fig.12 I2S-bus timing and format.

VIH (70%)
VIL (20%)

VIH (70%)
VIL (20%)

MSB

RIGHT

MBH173

1997 May 30 23

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

handbook, full pagewidth

CL

WS

EXDAT1
EXDAT2

INPUT

EXDAT

OUTPUT

t

HC

t

LC

t

d1

t

r

t

f

t

s2

t

f

t

d2

t

3

t

r

t

r

t

f

Fig.13 Timing diagram of the CDSP to external processor.

EXSCL

EXWS

EXDAT1
EXDAT2

t

a

EXDAT

MBH174

handbook, full pagewidth

RDSDAT

RDSCLK

t

s

T

cy

Fig.14 RDS timing diagram in direct output mode.

1997 May 30 24

t

HC

t

LC

t

d

MBH175

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

handbook, full pagewidth

RDSDAT

RDSCLK

t

w

block ready start reading data

D0 D1 D2 D13 D14 D15

t

LC

t

T

cy

HC

MBH176

Fig.15 Interface signals RDS decoder and microcontroller.

11 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
∆V

I

IK

I

OK

I

O

I

DDD

I

SSD

DDD

DDD

DC supply voltage −0.5 +6.5 V
voltage difference between any two

V

pins

DDX

DC input clamp diode current VI< −0.5 V or VI>V
DC output clamp diode current output type 4 mA;

VO< −0.5 V or VO>V

DC output sink or source current output type 4 mA;

−0.5V<VO<V

DDD

+ 0.5 V −±10 mA

DDD

+ 0.5 V

DDD

+ 0.5 V

− 550 mV

−±20 mA

−±20 mA

DC supply current per pin −±50 mA

DC ground supply current per pin −±50 mA
LTCH latch-up protection CIC specification/test method 100 − mA
P
P
T
T
V

o
tot
amb
stg
ESD

power dissipation per output − 100 mW

total power dissipation − 1600 mW

operating ambient temperature −40 +85 °C

storage temperature −65 +150 °C

electrostatic handling for all pins note 1 3000 − V

note 2 300 − V

Notes

1. Human body model: C = 100 pF; R = 1500 Ω; 3 pulses positive plus 3 pulses negative.

2. Machine model: C = 200 pF; L = 2.5 µH; R = 25 Ω; 3 pulses positive plus 3 pulses negative.

1997 May 30 25

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

12 THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

from junction to ambient in free air and V
the QFP80 soldered to a PCB copper plate of 36 cm

R

th j-a

from junction to ambient in free air and V
the QFP80 not connected to a PCB copper plate

13 DC CHARACTERISTICS

V

= 4.75 to 5.5 V; T

DDD

= −40 to +85 °C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital part

D

IGITAL INPUTS AND OUTPUTS; NOTE 1

V

DDD(tot)

I

DDD(tot)

total DC supply voltage all V
total DC supply current maximum activity

pins 4.75 5.0 5.5 V

DDD

of the DSP;
f

= 36 MHz

xtal

P

tot

total power dissipation maximum activity

of the DSP;
f

= 36 MHz

xtal

V

IH

HIGH level input voltage;
pins 23 to 25, 27, 28,
30 to 33, 38 to 40,
44 to 48, 60 and 62

HIGH level input voltage;
pin 26

V

IL

LOW level input voltage;
pins 23 to 28, 30 to 33,
38 to 40, 44 to 48, 60
and 62

V

hys

V

OH

hysteresis voltage pin 26 − 0.33V
HIGH level output

voltage; pins 23,

V

= 4.75 V;

DDD

IO= −4mA
35 to 37, 42, 43, 48, 57,
60 and 61

V

OL

LOW level output
voltage;

V

= 4.75 V;

DDD

IO=4mA
pins 23, 35 to 37, 39, 42,
43, 48, 57, 60 and 61

I

LI

input leakage current;

VI=0orV
pins 24, 25, 27, 28, 38
and 44 to 47

 3-state output leakage

I

OZ

VO= 0 or V
current; pins 23, 35 to 37,
39, 42, 48, 57 and 60

lead fingers 50, 51, 54 and 55 of

SSD

lead fingers 50, 51, 54 and 55 of

SSD

2

− 160 200 mA

− 0.8 1.1 W

0.7V

DDD

0.8V

DDD

−−0.2V

4.25 −− V

−−0.5 V

DDD

DDD

−−±1µA

−−±5µA

35 K/W

42 K/W

−− V

−− V

DDD

− V

DDD

V

1997 May 30 26

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

pu

R

pd

t

r

t

f

t

r

t

f

internal pull-up resistor to
V

pin 26

DDD

internal pull-down
resistor to V

SSD

pins

30 to 33, 40 and 62
input rise time V
input fall time V
output rise time for

LOW-to-HIGH transition

output fall time for
HIGH-to-LOW transition

17 − 134 kΩ

Vi=V

DDD

= 5.5 V − 6 200 ns

DDD

= 5.5 V − 6 200 ns

DDD

V

= 4.75 V;

DDD

T

=85°C;

amb

17 − 134 kΩ

−−1.43 + 0.24CLns

pins 23, 48 and 60

V

T

DDD
amb

= 4.75 V;

=85°C;

−−4.75 + 0.28CLns

pins 43 and 61

V

T

DDD
amb

= 4.75 V;

=85°C;

−−4.75 + 0.28CLns

pins 35 to 37, 42

and 57

V

T

DDD
amb

= 5.5 V;

= −40 °C;

0.351 + 0.097CL−− ns

pins 23, 48 and 60

V

T

DDD
amb

= 5.5 V;

= −40 °C;

1.302 + 0.101CL−− ns

pins 43 and 61

V

T

DDD
amb

= 5.5 V;

= −40 °C;

1.302 + 0.101CL−− ns

pins 35 to 37, 42

and 57

V

T

DDD
amb

= 4.75 V;

=85°C;

−−1.82 + 0.31CLns

pins 23, 48 and 60

V

T

DDD
amb

= 4.75 V;

=85°C;

−−6.44 + 0.36CLns

pins 43 and 61

V

T

DDD
amb

= 4.75 V;

=85°C;

−−6.44 + 0.36CLns

pins 35 to 37, 42

and 57

V

T

DDD
amb

= 5.5 V;

= −40 °C;

0.386 + 0.097CL−− ns

pins 23, 48 and 60

V

T

DDD
amb

= 5.5 V;

= −40 °C;

0.971 + 0.115CL−− ns

pins 43 and 61

V

T

DDD
amb

= 5.5 V;

= −40 °C;

0.971 + 0.115CL−− ns

pins 35 to 37, 42

and 57

1997 May 30 27

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog part

ANALOG INPUTS:V
V

DDA1

DDA1

analog supply voltage
for ADC

V

refMPX

common mode
reference voltage MPX
ADC pin 70

V

refRDS

common mode
reference voltage RDS
ADC pin 80

Z

O

output impedance at pins
70 and 80

V

DACPM

positive reference
voltage for MPX ADC
and RDS ADC

I

VDACPM

positive reference current
for MPX ADC

V

DACNM

negative reference
voltage for MPX ADC
and RDS ADC

I

VDACNM

negative reference
current MPX ADC

V

DACNL

negative reference
voltage level A/D

I

VDACNL

negative reference
current for level ADC

V

IosMPX

V

IosRDS

input offset voltage MPX − 140 − mV
input offset voltage RDS − 140 − mV

ANALOG OUTPUTS:V
V

DDD1

digital supply voltage for
upsample filter and
digital DAC

V

DDA1

analog supply voltage
for DAC

V

DDO

operational amplifier
supply voltage

V

Z

ref

15-20

input voltage on pin 20 with respect to

impedance between
pins 15 and 20

Z

14-20

impedance between
pins 14 and 20

V

13

input voltage on pin 13 with respect to

=5V;T

DDD=VDDA=VDDO

amb

=25°C

with respect to

pins 68 and 69

with respect to

pins 68 and 69

=5V;T

amb

=25°C

pins 14 and 15

pins 14 and 15

4.75 5.0 5.5 V

0.47V

0.47V

DDA1

DDA1

0.5V

0.5V

DDA1

DDA1

0.53V

0.53V

DDA1

DDA1

V

V

− 600 −Ω

4.75 5.0 5.5 V

−−20 −µA

−0.3 0 +0.3 V

− 20 −µA

−0.3 0 +0.3 V

− 5 −µA

4.75 5.0 5.5 V

4.75 5.0 5.5 V

4.75 5.0 5.5 V

0.47V

DDO

0.5V

DDO

0.53V

DDO

V

12 18 25 kΩ

12 18 25 kΩ

0.46V

DDA

0.5V

DDA

0.54V

DDA

V

1997 May 30 28

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

O(DAC; max)

V

O(os)

V

O(rms)

V

O(av)

R

POM

Crystal oscillator: T

V

DD(osc)

Current per supply pin or pin group: T

I

DDD1

I

DDA

I

DDO

I

DDD

I

DDX

I

DDA1

maximum output current
from DACs

reference

resistance to

490 570 650 µA

pin 14 = 18 kΩ
DC offset voltage at DAC

output
AC output voltage of

operational amplifier
outputs at maximum

with respect to

pin 20

RL> 5kΩ;

Rfb= 2.7 kΩ;

note 2

− 5 − mV

0.94 1.09 1.24 V

signal pins 10, 12, 17
and 19 (RMS value)

average DC output
voltage at pins 10, 12,
17 and 19

RL>5kΩ;

Rfb= 2.7 kΩ;

note 2

2.25 2.5 2.75 V

pull-up resistor to pin 15 64 128 260 kΩ

=25°C

amb

oscillator supply voltage 4.75 5.0 5.5 V

=25°C; VDD= 5 V (typ.); 5.5 V (max.)

amb

digital supply current

− 20 50 µA

DACs pin 7
analog supply current

− 48 mA

DAC pin 8
supply current for

no load − 24 mA
operational amplifiers
pin 15

supply current for digital

− 137.5 165 mA
circuitry and periphery
pins 49, 52, 53 and 56

supply current for crystal

− 1.5 3 mA
circuit pin 65

supply current for ADCs

− 15 20 mA
pin 69

Notes

1. The values for the capitative load CL are given in pF.

2. RL is the AC impedance of the external circuitry at 1 kHz, connected to the audio outputs in the application. There is
also no DC current flowing through RL.

1997 May 30 29

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

14 AC CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog DC inputs (LEVEL-FM, AM): V

DDD=VDDA1

S/N signal-to-noise ratio ADC RMS value;

=5V; T

amb

=25°C

48 54 − dB
not weighted;
B = 0 to 29 kHz;
maximum input

RMS value;

52 58 − dB
not weighted; audio
mode; B = 0 to 19 kHz;
maximum input

R
V
V

i
FS
I(os)

input resistance 200 400 − kΩ
full-scale input voltage V
DC offset voltage at

= 4.75 to 5.5 V 1.05V

DDA1

with respect to V

DACNL

DDA1

1.1V

DDA1

1.15V

DDA1

V

−−60 mV

minimum input voltage

V

iADR

input voltage level R

=5kΩ−0.3 − +7.5 V

ext

α decimation filter attenuation 20 −−dB/Dec
f

co

f

sr

pass-band cut-off frequency at −3dB − 29 − kHz
sample rate after

decimation

radio mode − 38 76 kHz
audio mode − 38 76 kHz

Analog AC inputs: pins MPX, AM, TAPE and AUX

V

i(con, rms)

maximum conversion input

THD < 1% 1.1 −−V

voltage level (RMS value)

R

i

THD total harmonic distortion f

S/N

ADC

input resistance 48 60 72 kΩ

= 1 kHz; Vi= 1 V (RMS) −−71 −61 dB

i

f

= 1 kHz; Vi= 1 V (RMS) − 0.03 0.09 %

i

signal-to-noise ratio for
ADC

not multiplexed;
B = 19 kHz;

81 85 − dB

Vi= 1 V (RMS)
multiplexed; unweighted;

72 76 − dB
B = 19 kHz;
V

= 1 V (RMS)

i

S/N

AM

signal-to-noise ratio for AM B = 5 kHz;

68 72 − dB
Vi= 200 mV (RMS);
(M = 30%)

S/N

FM(mon)

signal-to-noise-ratio for FM
mono

Vi= 200 mV (RMS);
(∆f = 22.5 kHz);

69 72 − dB

B = 19 kHz; unweighted;
(M = 30%)

S/N

FM(st)

signal-to-noise-ratio for FM
stereo

Vi= 200 mV (RMS);
(∆f = 22.5 kHz);

60 63 − dB

B = 19 kHz; unweighted;
(M = 30%)

1997 May 30 30

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

S/N

TAPE

S/N

AUX

α19 carrier and harmonic

α38 carrier and harmonic

α57 carrier and harmonic

α76 carrier and harmonic

IM

α10

IM

α3

α57(VF) traffic radio suppression f
α67 subsidiary communication

α114 adjacent channel

α190 adjacent channel

V

pilot(rms)

HYS hysteresis level of pilot

f

i

α

cs

f

resFM

|∆G

| channel unbalance

v

signal-to-noise-ratio for
TAPE (+10 kHz RC)

B = 19 kHz;
Vi= 1 V (RMS);
unweighted

signal-to-noise-ratio for
AUX

B = 19 kHz;
Vi= 1 V (RMS);
unweighted

=19kHz − 81 − dB

i

suppression at the output

pilot signal f
no modulation − 98 − dB

with and without modulation
(for 19 kHz including notch)

suppression at the output

subcarrier; f
no modulation − 91 − dB

= 38 kHz − 83 − dB

i

with and without modulation

= 57 kHz − 83 − dB

i

suppression at the output

subcarrier; f
no modulation − 96 − dB

with and without modulation

suppression at the output

subcarrier; f
no modulation − 94 − dB

= 76 kHz − 84 − dB

i

with and without modulation
intermodulation f

intermodulation f

= 10 kHz;

mod

f

= 1 kHz; note 1

spur

= 13 kHz;

mod

f

= 1 kHz; note 1

spur

= 57 kHz; note 2 − 110 − dB

i

f

= 67 kHz; note 3 − 110 − dB

i

authority (SCA)

= 114 kHz; note 4 − 110 − dB

f

i

interference

= 190 kHz; note 4 − 110 − dB

f

i

interference
pilot threshold voltage at

pin 42

stereo ON − 35.6 − mV
stereo OFF − 35.5 − mV

voltage
input frequency range MPX −3 dB; ADC via bitstream

test output

FM stereo channel
separation

fi= 1 kHz 40 45 − dB
f

= 10 kHz 25 30 − dB

i

audio frequency responseFMat −3 dB via DSP at DAC

output

left/right TAPE, AUX, FM
and AM

70 74 − dB

72 76 − dB

77 −−dB

76 −−dB

− 0 − dB

0 − 55 kHz

16 −−kHz

−−0.5 dB

1997 May 30 31

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

α

cs

f

res

α

ct

PSRR power supply ripple

Analog AC inputs: RDS

V

i(rms)

R

i

α

pilot

α nearby selectivity RDS neighbouring channel at

α

mux

∆f

osc

channel separation TAPE
and AUX

fi= 1 kHz 40 45 − dB
f

= 10 kHz 25 30 − dB

i

f

= 1 kHz, software

i

− 50 − dB

compensated

frequency response TAPE

at −3dB 18 −−kHz

and AUX
crosstalk between inputs fi= 1 kHz 65 −−dB

= 15 kHz 50 −−dB

f

i

2

S-bus;

= 1 kHz;

= 100 mV (peak);

= 22µF;

= 22µF;

=10µF

= 1 kHz;

= 100 mV (peak);

=22µF

35 45 − dB

29 39 − dB

rejection for MPX and RDS
ADCs

power supply ripple
rejection for ADC level

input voltage level

output via I
ADC input shorted;
f

ripple

V

ripple

C

VrefMPX

C

VrefRDS

C

VDACPM

output via DAC;
ADC input shorted;
f

ripple

V

ripple

C

VrefRDS

THD < 1% 1.1 −−V

(RMS value)
input resistance RDS ADC 48 60 72 kΩ
pilot attenuation RDS 50 −−dB

61 −−dB
200 kHz distance

multiplex attenuation RDS mono 70 −−dB

stereo 40 −−dB

allowable frequency
deviation 57 kHz RDS

maximum crystal
deviation of 100 ppm

−−6Hz

Analog outputs: V

DDD=VDDA=VDDO =

PSRR power supply ripple

rejection DACs

∆V

o(DAC)

maximum deviation in
output level (plus or minus)
of the 4 DAC current
outputs

α

ct

crosstalk between all
outputs in the audio band

G

O

DC open loop gain of

5 V; T

input via I
f
V
C

with respect to the
average of the 4 outputs;
tolerance Ro< 0.1%;
full-scale output

two outputs digital silence
other two maximum
volume; f

=25°C

amb

2

= 1 kHz;

ripple

= 100 mV (peak);

ripple

=22µF

Vref

audio

S-bus;

= 10 kHz

operational amplifiers

1997 May 30 32

35 42 − dB

−−0.38 dB

−−−60 dB

− 85 − dB

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Z

o

f

ug

I

o(sc)

RES DAC resolution − 18 − bits
(THD + N)/S DAC total harmonic

DR dynamic range V

DS digital silence V

IM intermodulation

f

s(max)

B bandwidth of DAC f
C

L

R

L

AC output impedance of

RL> 5kΩ; note 5 − 1.5 −Ω

operational amplifiers
unity gain frequency

open loop − 4.5 − MHz

operational amplifiers
short-circuit current output output short-circuited to

ground

f

= 1 kHz;

i

distortion plus
noise-to-signal ratio of
DAC and operational
amplifiers

Vo= 2.8 V (p-p)
(full-scale)

= 1 kHz; at −60 dB;

f

i

A-weighted

= 4.46 V (p-p);

ref(o)

fi= 1 kHz; at −60 dB;
A-weighted

= 4.46 V (p-p);

ref(o)

fi= 20 Hz to 17 kHz;
A-weighted

digital silence noise level at
output

distortion/comparator
maximum sample

RMS value; B = 20 kHz,
A-weighted

f

= 60 Hz and 7 kHz;

i

ratio 4 : 1
f

= 36.9 MHz 48 −−kHz

xtal

frequency

−3dB −

s=fs

allowed load capacitance
on DAC voltage outputs

allowed load resistor on
DAC voltage outputs

− 10 25 mA

−−70 −60 dB

−−38 −28 dBA

92 102 − dBA

−−110 −100 dBA

− 515µV

−−70 −55 dB

1

⁄2f

s

− kHz

−−2.5 nF

2 −−kΩ

Crystal oscillator at: V

f

α

xtal

f

crystal frequency − 36.860 − MHz
spurious frequency

DDX

=5V; T

amb

=25°C

attenuation

I

64

G

m

V

xtal

C

L

R

xtal

output current pin 64 −−1mA
transconductance at start-up 4 8 − mS
voltage across crystal − 500 − mV
load capacitance note 6 − 10 − pF
allowed resistance loss of

crystal

Cp= 5 pF; Cx1=10pF;
Cx2=10pF

1997 May 30 33

20 −−dB

− 20 100 Ω

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing at: V

f

xtal

δf

xtal/fxtal

DDD=VDDA=VDDA1=VDDX

crystal frequency − 36.860 − MHz
frequency adjustment

=5V; T

amb

=25°C

−30 − +30 ppm

tolerance

/∆T drift over temperature range −30 − +30 ppm

δf

xtal

f

i(max)

maximum input frequency

100 −−kHz

of I2C-bus clock

2

S-bus inputs and outputs (see Fig.18)

I

t

r

t

f

t

HC

t

LC

t

dWS

t

h

t

s

t

d

t

a

rise time V

fall time V

clock output HIGH time 112 −−ns
clock output LOW time 112 −−ns
Word Select delay time 0 −−ns
data hold time 0 −−ns
data set-up time 25 −−ns
data delay time 0 − 5ns
data out access time −−5 + 0.5CLns

T
V

T

T
V

T

amb

amb

amb

amb

DDD

DDD

DDD

DDD

= 4.75 V;

=85°C

= 5.5 V;

= −40 °C

= 4.75 V;

=85°C

= 5.5 V;

= −40 °C

−−4.75 +

0.28C

1.302 +

0.101C

−−ns

L

−−6.44 +

0.36C

0.971 +

0.115C

−−ns

L

L

L

RDS; (see Figs.14 and 15)
f

clk

t

s

T

cy

t

HC

t

LC

t

h

t

w

t

pb

t

HC

t

LC

nominal clock frequency RDS-clock − 1187.5 − Hz
clock set-up time 100 −−µs
periodic time − 842 −µs
clock HIGH time 220 − 640 µs
clock LOW time 220 − 640 µs
data hold time 100 −−µs
wait time 1 −−µs
periodic time 2 −−µs
clock HIGH time 1 −−µs
clock LOW time 1 −−µs

Other

f

EXCLK

input frequency on pin 40 −−22 MHz

ns

ns

1997 May 30 34

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

Notes to the AC characteristics

1. Intermodulation suppression (BFC: Beat Frequency Components).
a) α2=V
b) α3=V
c) Measured with 91% mono signal; f

2. Traffic radio (VF) suppression.
a) α57(VF) = V
b) Measured with 91% stereo signal; f
c) 5% traffic subcarrier (f = 57 kHz; f

3. SCA (Subsidiary Communication Authorization).
a) α67 = V
b) Measured with 81% mono signal; f
c) 10% SCA subcarrier (fs= 67 kHz, unmodulated).

4. ACI (Adjacent Channel Interference).
a) α114 = V
b) α190 = V
c) Measured with 90% mono signal; f

unmodulated).

5. RL is the AC impedance of the external circuitry at 1 kHz connected to the audio outputs in the application. There is
also no DC current flowing through RL.

6. The load capacitance is the sum of the series connection of C × 1 and C × 2 (see Fig.11) and the parasitic parallel
capacitor of the crystal Cp.

o(signal)
o(signal)

o(signal)

o(signal)
o(signal)

(at 1 kHz)/V
(at 1 kHz)/V

(at 1 kHz)/V

o(signal)

(at 1 kHz)/V

(at 1 kHz)/V
(at 1 kHz)/V

o(spurious)
o(spurious)

o(spurious)

o(spurious)

o(spurious)
o(spurious)

(at 1 kHz); fs=(2×10 kHz) − 19 kHz.
(at 1 kHz); fs=(3×13 kHz) − 38 kHz.

= 10 or 13 kHz; 9% pilot signal.

mod

(at 1 kHz ±23 Hz).

= 1 kHz; 9% pilot signal.

mod

= 23 Hz AM, m = 0.6).

mod

(at 9 kHz); fs=(2×38 kHz) − 67 kHz.

= 1 kHz; 9% pilot signal.

mod

(at 4 kHz); fs= 110 kHz − (3 × 38 kHz).
(at 4 kHz); fs= 186 kHz − (5 × 38 kHz).

= 1 kHz; 9% pilot signal; 1% spurious signal (fs= 110 kHz or 186 kHz,

mod

1997 May 30 35

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

15 I2C-BUS CONTROL AND COMMANDS

2

15.1 Characteristics of the I

C-bus

The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to V

via a pull-up resistor when connected

DDD

to the output stages of a microcontroller. Data transfer can
only be initiated when the bus is not busy.

15.2 Bit transfer

One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse, as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 100 kHz (see Fig.16).

15.3 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P) (see Fig.17).

15.4 Data transfer

A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’.

acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data
line HIGH, to enable the master to generate a STOP
condition (see Fig.19).

15.6 I

15.6.1 A

2

C-bus format

DDRESSING

Before any data is transmitted on the I2C-bus, the device
that should respond is addressed first. The addressing is
always done with the first byte transmitted after the START
procedure.

15.6.2 S

LAVE ADDRESS (A0 PIN)

The CDSP acts as a slave receiver or slave transmitter.
Therefore, the clock signal SCL is only an input signal.
The data signal SDA is a bi-directional line. The CDSP
slave address is shown in Table 6.

Table 6 Slave address

MSB LSB

001110A0R/

W

The sub-address bit A0 corresponds to the hardware
address pin A0, which allows the device to have 1 of 2
different addresses. The A0 input is also used in test mode
as a serial input of the test control block.

The device that controls the message is the ‘master’ and
the devices that are controlled by the master are the
‘slaves’ (see Fig.18).

15.5 Acknowledge

The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge-related clock pulse.
A slave receiver that is addressed must generate an
acknowledge after the reception of each byte. Also, a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter.

The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge-related clock pulse. Set-up and hold times
must be taken into account. A master receiver must signal
an end-of-data to the transmitter by not generating an

1997 May 30 36

15.6.3 CDSP

WRITE CYCLES

The I2C-bus configuration for a WRITE cycle is illustrated
in Fig.22. The WRITE cycle is used to write in the IAC
register, the input selector control register and to initialize
or update coefficient values in XRAM or YRAM. The data
is transferred from the I2C-bus register to the DSP register
once every DSP cycle.

The I2C-bus interface circuitry in the SAA7707H requires
that the LOW period of the SCL line following the
acknowledge bit is at least 1/fs (in seconds); where fs is the
audio sampling frequency (in Hertz). This requirement
must be met for a single write operation and an
auto-incremental operation, but only applies to the
acknowledge bit following each DATA-L
(see Figs 20 and 21).

The data length is 2 or 3 bytes, depending on the
accessed memory. If the Y-memory is addressed the data
length is 2 bytes, If the X-memory is addressed the length
is 3 bytes. The slave receiver detects the address and
adjusts the byte length accordingly.

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

15.6.4 CDSP READ CYCLES

The I2C-bus configuration for a READ cycle is illustrated in Fig.23. The READ cycle is used to read data values from
XRAM or YRAM. The data is transferred from the DSP register to the I2C-bus register at execution of the MPI instruction
in the DSP program. Therefore, an MPI instruction should be added at least once every DSP cycle.

h

SDA

SCL

handbook, full pagewidth

SDA

SCL

data line

stable;

data valid

S

START condition

change

of data

allowed

MBC621

Fig.16 Bit transfer on the I2C-bus.

P

STOP condition

SDA

SCL

MBC622

Fig.17 START and STOP conditions.

1997 May 30 37

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

handbook, full pagewidth

SDA

SCL

START

CONDITION

MSB acknowledgement

signal from receiver

byte complete;

interrupt within receiver

7812

ACK

Fig.18 Data transfer on the I2C-bus.

acknowledgement

signal from receiver

clock line held low while
interrupts are serviced

9

1 2 3 - 8 9

ACK

MBH177

PS

STOP

CONDITION

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

S

START

CONDITION

Fig.19 Acknowledge on the I2C-bus.

1997 May 30 38

not acknowledge

acknowledge

MBH178

9821

clock pulse for

acknowledgement

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

handbook, full pagewidth

SDA

SCL

1-7 8 9 1-7 8 9 1-7 8 9

DATA-M DATA-LDATA-H ACK

ACKACK

minimum required LOW period

Fig.20 Minimum required SCL LOW period; single write.

≥1/f

P

STOP

condition

s

MGK426

1997 May 30 39

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k

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1997 May 30 40

SDA

, full pagewidth

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

SCL

1-7 8 9 1-7 8 9 1-7 8 9

DATA-M DATA-LDATA-H ACK

ACKACK

minimum required LOW period

Fig.21 Minimum required SCL LOW period; auto-incremental write.

≥1/f

1-7 8 9 1-7 8 9 1-7 8 9

DATA-M DATA-LDATA-H ACK ACKACK

s

MGK427

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1997 May 30 41

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

A
C
K

R/W

A
C
K

0111000

0 ADDR H ADDR L DATA H DATA M

S

address

A
C
K

A
C
K

auto increment if repeated n-groups of 3 (2) bytes

Fig.22 Master transmitter writes to CDSP registers.

R/W

A
C
K

auto increment if repeated n-groups of 3 (2) bytes

A

C

K

R/W

A
C
K

0111000

0 011 1100

S

address

A

0ADDR H ADDR L DATA H

C

S

K

Fig.23 Master transmitter reads from CDSP registers.

A
C
K

A

DATA M DATA L

C
K

A
C

DATA L

A
C
K

K

MGD568

A
C
K

MGA808 - 1

P

P

16 SOFTWARE DESCRIPTION

A detailed description of the software feature, complete with operating instructions, is provided in the application manual.

17 APPLICATION INFORMATION

The application diagram illustrated in Figs. 24 and 25 must be considered as one of the examples of a (limited) application of the SAA7707H.

2

For example, in the application shown, the I

S-bus inputs of the DCC and CD are not used.

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

handbook, full pagewidth

+5 V

LEVEL (AM, FM)

CDIN-R

CDIN-L

CASS-R

CASS-L

RADIO-F (AM)

MPX (FM)

+5 V

+5 V

C14

470 nF

C15

470 nF

C16

470 nF

C17

470 nF

R1

1 kΩ

4.7 kΩ

4.7 kΩ

4.7 kΩ

4.7 kΩ

4.7 kΩ

3.3 kΩ

3.3 kΩ

R2

R3

R4

R5

R6

R7

R7

C13

C4

C7

C8

C9

C10

C11

C12

C1

4.7 µF
BLM21A10

L2

C2
100 µF

10 µF

1 nF

330

pF

330

pF

3.3
nF

3.3
nF

330

pF

150

pF

C18

10 µH

220 µH

C3
100 nF

C5

C6

22 µF

220

nF

C19

L1

L3

22 µF

1 µF

77
78
70

80
62

4

3
72
71
74
72
75
76
79

+5 V

C20

1 nF

V

DACPM

V

DACNM

V

refMPX

V

refRDS

MPXRDS
AM

FM
AUXR
AUXL
TAPER
AUXR
AMAF
FMMPX
FMRDS

MBH179

21

CINT

DACNL

V

RTCB

SHTCB30TSCAN

32

33

C22

+5 V

C21

100 nF

SSG

SSA1

V

DDA1

V

V

SAA7707H

RDSCLK

60

R9

R11

100 Ω

100 Ω

C23

220

R10

pF

100 Ω

RDSCLK RDSDAT

220

pF

522

SSD1VSSD2

V

RDSDAT

61

C24

BLM21A10

R12
100 Ω

5067 68 69 51

54 55

SSD3

SSD4

V

V

V

DDX

V

XTALO

65 64 63

100

nF

L4

+5 V (e.g.)

L5

4.7 µH
C25

4.7 nF

SSD5VSSD6

R13

100 kΩ

X1

36.86 MHz

C26
10 pF

34 41

SSD7VSSD8

V

XTALI

C27
10 pF

29

SSD9

V

SSX

V

66

CDCLK

23

Fig.24 Application diagram (continued in Fig.25).

1997 May 30 42

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

ook, full pagewidth

+5 V

C31

100 nF

56

DDD2

V

DCWS25CDDAT48DCCDAT47DCCWS46DCCCLK

24

BLM32A07

49

DDD3

V

L6

52

V

DDD4

RDSMUTE PAUSE

C33

100 pF
C32
100 µF

53

DDD5

V

TEST257TEST1

R16
220 Ω

4544

MUTE

DEEM

SAA7707H

SSD10

V

58

42 43

MSS/P

STEREO

EXDAT

EXSCL

35

36

R17
220 Ω

C34
100 pF

7

V

EXDAT2

EXDAT1

28 27 3759

C28

100 pF

DDD1

R14

220 Ω

8

DDA

V

EXWS

D1
BAT54

15

DDO

V

SCL

38 39

SDA

R15
220 Ω

+5 V

C35
100 nF

14

SSO

V

A0

31

C36
22 µF

6

SSA

V

EXCLK

DSPRESET
26

C29
100 pF

POM
FIOL

FVOL

FIOR

FVOR

RIOL

RVOL

RIOR

RVOR

V

I

ref(int)

C30
220 nF

MICROCONTROLLER

21

C42
22 µF

C38

2.2 nF

100 Ω

C39

2.2 nF

100 Ω

C40

2.2 nF

100 Ω

C41

2.2 nF

100 Ω

R23

R24

R25

R26

18

R18

2.7 KΩ

19

16

R19

2.7 KΩ

17

11

R20

12

2.7 KΩ

9

R21

10

2.7 KΩ

40
20

ref

13

R22
18 kΩ

C37

4.7 µF

C44 2.2 µF

C43
10 nF

C46 2.2 µF

C45
10 nF

C48 2.2 µF

C47
10 nF

C50 2.2 µF

C49
10 nF

FRONT-LEFT

FRONT-RIGHT

REAR-LEFT

REAR-RIGHT

SCL SDA

Fig.25 Application diagram (continued from Fig.24).

1997 May 30 43

MBH180

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

18 PACKAGE OUTLINE

QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

Z

E

e

w M

p

A

A

H

E

E

2

A

A

1

64 41

65

pin 1 index

80

1

40

b

25

24

detail X

L

p

L

SOT318-2

(A )

3

θ

w M

b

e

p

Z

D

D

H

D

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.2

0.25

0.05

2.90

2.65

0.25

UNIT A1A2A3b

cE

p

0.45

0.25

0.30

0.14

(1)

(1) (1)(1)

D

20.1

19.9

eH

H

14.1

13.9

24.2

0.8 1.95

23.6

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT318-2

1997 May 30 44

D

B

E

18.2

17.6

v M

A

v M

B

LL

p

1.0

0.6

0.20.2 0.1

EUROPEAN

PROJECTION

Z

D

1.0

0.6

Zywv θ

E

o

1.2

7

o

0.8

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

19 SOLDERING

19.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

19.2 Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

19.3 Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

19.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 May 30 45

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

20 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

21 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2

22 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1997 May 30 46

Philips Semiconductors Preliminary specification

Car radio Digital Signal Processor (CDSP) SAA7707H

NOTES

1997 May 30 47

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Tel. [phone], Fax. [phone]
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Brazil: see South America
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51 James Bourchier Blvd., 1407 SOFIA,
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]

Slovakia: see Austria
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South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547027/1200/02/pp48 Date of release: 1997 May 30 Document order number: 9397 750 02261