Datasheet saa7335 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA7335

DSP for CD and DVD-ROM
systems

Preliminary specification
File under Integrated Circuits, IC01

1997 Aug 11

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

FEATURES

• Compatibility with CD-I, CD-ROM, MPEG-video
DVD-ROM and DVD-video applications

• Designed for very high playback speeds

• Typical CD-ROM operation up to n = 12, DVD-ROM to

n = 1.9, maximum rates (tbf)

• Matched filtering, quad-pass error correction
(C1-C2-C1-C2), overspeed audio playback function
included (up to 3 kbytes buffer)

• Lock-to-disc playback, Constant Angular Velocity
(CAV), pseudo-Constant Linear Velocity (CLV) and CLV
motor control loops

• Interface to 32 kbytes SRAM for DVD error correction
and de-interleave

• Sub-code/ header processing for DVD and CD formats

• Programmable HF equalizer

• In DVD mode it is still compatible with Philips block

decoders

2

• Sub-CPU interface can be parallel or fast I

• On-chip clock multiplier.

GENERAL DESCRIPTION

This device is a high-end combined Compact Disc (CD)
and Digital Versatile Disc (DVD) compatible decoding
device. The device operates with an external 32 kbytes
S-RAM memory for de-interleaving operations. The device
provides quad-pass error correction for CD-ROM
applications (C1-C2-C1-C2) and operates in lock-to-disk,
CAV, pseudo CLV and CLV modes.

C-bus

SAA7335

In DVD modes double-pass C1-C2 error correction is used
which is capable of correcting up to 5 C1 frame errors and
16 C2 frame errors.

The SAA7335 contains all the functions required to
decode an EFM or EFM+ HF signal directly from the laser
pre-amplifier, including analog front-end, PLL data
recovery, demodulation and error correction. The spindle
motor interface provides both motor control signals from
the demodulator and, in addition, contains a tachometer
loop that accepts tachometer pulses from the motor unit.

The SAA7335 has two independent microcontroller
interfaces. The first is a serial I
standard 8-bit multiplexed parallel interface. Both of these
interfaces provide access to a total of 32 × 8-bit registers
for control and status.

This data sheet contains an descriptive overview of the
device together with electrical and timing characteristics.
For a detailed description of the device refer to the user
guide

“SAU/UM96018”

.

Supply of this CD/DVD IC does not convey an implied
license under any patent right to use this IC in any CD or
DVD application.

2

C-bus and the second is a

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V
I

DDD

V
I

DDA

f

xtal

T
T

DDD

DDA

amb
stg

digital supply voltage 4.5 5.0 5.5 V
digital supply current − 70 300 mA
analog supply voltage 4.5 5.0 5.5 V
analog supply current − 70 300 mA
crystal input frequency 4 25 tbf MHz
operating ambient temperature −20 − +70 °C
storage temperature −55 − +125 °C

1997 Aug 11 2

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA7335GP LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1

BLOCK DIAGRAM

handbook, full pagewidth

ADCHF input

PLL BIT

DETECTOR

DEMODULATOR

EFM/EFM+

SRAM

32 KBYTES

DECODER

I2S-BUS

OUTPUT

INTERFACE

block
decoder
output

clock input

CLOCK

GENERATOR

SPINDLE

MOTOR CONTROL

motor control

SAA7335

Fig.1 Simplified block diagram.

SUB-CPU

INTERFACE

MGK242

1997 Aug 11 3

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

PINNING

SYMBOL PIN TYPE DESCRIPTION

V

SSA1

I

ref

REFLo 3 I analog low reference input for ADC
REFHi 4 I analog high reference input for ADC
VREF 5 I analog negative input
HFIN 6 I analog positive input
V

SSA2

AGCOUT 8 O analog test pin output
V

DDA2

V

DDD1

V

SSD1

OTD 12 I off track detect input
MOTO1 13 O 3-state motor control output
n.c. 14 − not connected, reserved
MOTO2/T3 15 I/O motor control output/tachometer 3 input
n.c. 16 − not connected, reserved
T1 17 I tachometer 1 input
T2 18 I tachometer 2 input
V

DDD2

V

SSD2

TEST1 21 I test input 1
TEST2 22 I test input 2
POR 23 I power-on reset input
MUXSWICH 24 I use clock multiplier input
n.c. 25 − not connected, reserved
CL1 26 O divided clock output
BCAIN 27 I BCA input
SDA 28 I/O sub-CPU I
SCL 29 I sub-CPU I
INT 30 O sub-CPU interrupt output (open-drain)
V

DDD3

V

SSD3

da7 33 I/O sub-CPU data bus bit 7 input/output (parallel)
da6 34 I/O sub-CPU data bus bit 6 input/output (parallel)
da5 35 I/O sub-CPU data bus bit 5 input/output (parallel)
n.c. 36 − not connected, reserved
da4 37 I/O sub-CPU data bus bit 4 input/output (parallel)
n.c. 38 − not connected, reserved
da3 39 I/O sub-CPU data bus bit 3 input/output (parallel)
da2 40 I/O sub-CPU data bus bit 2 input/output (parallel)

1 supply analog ground 1
2 I analog current reference input for ADC

7 supply analog ground 2

9 supply analog supply voltage 2
10 supply digital supply voltage 1
11 supply digital ground 1

19 supply digital supply voltage 2
20 supply digital ground 2

2

C-bus serial data input/output

2

C-bus serial clock input

31 supply digital supply voltage 3
32 supply digital ground 3

SAA7335

1997 Aug 11 4

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SYMBOL PIN TYPE DESCRIPTION

da1 41 I/O sub-CPU data bus bit 1 input/output (parallel)
n.c. 42 − not connected, reserved
da0 43 I/O sub-CPU data bus bit 0 input/output (parallel)
V

DDD4

V

SSD4

WRi 46 I sub-CPU write enable input (active LOW)
RDi 47 I sub-CPU read enable input (active LOW)
ALE 48 I sub-CPU address latch enable input
CSi 49 I sub-CPU chip select input (active HIGH)
STOPCLOCK 50 O stop clock output
n.c. 51 − not connected, reserved
V4 52 O serial subcode output (for CD)
EBUOUT 53 O digital audio output
SYNC 54 O I
FLAG 55 O I
DATA 56 O I
BCLK 57 I/O I
WCLK 58 I/O I
V

DDD5

V

SSD5

RAMRW 61 O RAM read/write control output
n.c. 62 − not connected, reserved
RAMDA7 63 I/O RAM data bus bit 7 input/output
RAMDA6 64 I/O RAM data bus bit 6 input/output
RAMDA5 65 I/O RAM data bus bit 5 input/output
RAMDA4 66 I/O RAM data bus bit 4 input/output
RAMDA3 67 I/O RAM data bus bit 3 input/output
RAMDA2 68 I/O RAM data bus bit 2 input/output
n.c. 69 − not connected, reserved
RAMDA1 70 I/O RAM data bus bit 1 input/output
RAMDA0 71 I/O RAM data bus bit 0 input/output
V

DDD6

V

SSD6

RAMAD0 74 O RAM address bit 0 output
RAMAD1 75 O RAM address bit 1 output
RAMAD2 76 O RAM address bit 2 output
RAMAD3 77 O RAM address bit 3 output
RAMAD4 78 O RAM address bit 4 output
RAMAD5 79 O RAM address bit 5 output
RAMAD6 80 O RAM address bit 6 output
V

DDD7

44 supply digital supply voltage 4
45 supply digital ground 4

2

S-bus sector sync output

2

S-bus correction flag output

2

S-bus serial data output

2

S-bus bit serial clock input/output

2

S-bus word clock input/output
59 supply digital supply voltage 5
60 supply digital ground 5

72 supply digital supply voltage 6
73 supply digital ground 6

81 supply digital supply voltage 7

SAA7335

1997 Aug 11 5

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SYMBOL PIN TYPE DESCRIPTION

V

SSD7

RAMAD7 83 O RAM address bit 7 output
RAMAD8 84 O RAM address bit 8 output
RAMAD9 85 O RAM address bit 9 output
n.c. 86 − not connected, reserved
RAMAD10 87 O RAM address bit 10 output
RAMAD11 88 O RAM address bit 11 output
RAMAD12 89 O RAM address bit 12 output
RAMAD13 90 O RAM address bit 13 output
RAMAD14 91 O RAM address bit 14 output
V

DDD8

V

SSD8

CRIN 94 I analog crystal input
CROUT 95 O analog crystal output
CFLG 96 O correction statistics output
MEAS1 97 O front-end telemetry output
V

DDD9

V

SSD9

V

DDA1

82 supply digital ground 7

92 supply digital supply voltage 8
93 supply digital ground 8

98 supply digital supply voltage 9
99 supply digital ground 9

100 supply analog supply voltage 1

SAA7335

1997 Aug 11 6

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

handbook, full pagewidth

V

SSA1

I

ref

REFLo

REFHi

VREF

HFIN

V

SSA2

AGCOUT

V

DDA2

V

DDD1

V

SSD1

OTD

MOTO1

n.c.

MOTO2/T3

n.c.

T1
T2

V

DDD2

V

SSD2

TEST1
TEST2

POR

MUXSWICH

n.c.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DDA1VSSD9VDDD9

V

100

MEAS1

CFLG

99989796959493929190898887868584838281

CROUT

CRIN

SSD8VDDD8

V

RAMAD14

RAMAD13

RAMAD12

RAMAD11

SAA7335

RAMAD10

n.c.

RAMAD9

RAMAD8

RAMAD7

SSD7VDDD7

RAMAD6

V

8079787776

RAMAD5

RAMAD4

RAMAD3

RAMAD2

SAA7335

75

RAMAD1
RAMAD0

74

V

73

SSD6

V

72

DDD6

71

RAMDA0
RAMDA1

70

n.c.

69

RAMDA2

68
67

RAMDA3
RAMDA4

66

RAMDA5

65

RAMDA6

64
63

RAMDA7
n.c.

62

RAMRW

61

V

60

SSD5

V

59

DDD5

WCLK

58

BCLK

57

DATA

56

FLAG

55

SYNC

54

EBUOUT

53

V4

52
51

n.c.

26

CL1

SDA

BCAIN

31323334353637383940414243444546474849

SCL

INT

DDD3

V

SSD3

V

da7

da6

da5

n.c.

da4

30

29

28

27

Fig.2 Pin configuration.

1997 Aug 11 7

n.c.

da3

da2

da1

n.c.

da0

DDD4

V

SSD4

V

WRi

RDi

ALE

50

CSi

STOPCLOCK

MGK241

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

FUNCTIONAL DESCRIPTION
Analog front-end

This block converts the HF input to the digital domain using
an 8-bit ADC proceeded by an AGC circuit to obtain the
optimum performance from the convertor. This block is
clocked by ADCCLK which is set by the external crystal
frequency plus a flexible clock multiplier and divider block.

PLL and bit detector

This subsystem recovers the data from the channel
stream. The block corrects asymmetry, performs noise
filtering and equalisation and finally recovers the bit clock
and data from the channel using a digital PLL.

The equalizer and the data slicer are programmable.

Digital logic

All the digital system logic is clocked from the master ADC
clock (ADCCLK) described above.

Advanced bit detector

The advanced bit detector offers improved data recovery
for multi-layer discs and contains two extra detection
circuits to increase the margins in the bit recovery block:

1. Adaptive slicer: adds a second stage slicer with higher
bandwidth

2. Run length 2 push-back: all T2 run lengths are pushed
back to T3, thereby automatically determining the
erroneous edge and shifting the transitions on that
edge.

Demodulator

F

RAME SYNC PROTECTION CD MODE

This circuit detects the frame synchronization signals.
Two synchronization counters are used in the SAA7335:

SAA7335

1. The coincidence counter: this is used to detect the
coincidence of successive syncs. It generates a sync
coincidence signal if 2 syncs are 588 ±1 EFM clocks
apart.

2. The main counter: this is used to partition the EFM
signal into 17-bit words. This counter is reset when:

a) A sync coincidence is generated
b) A sync is found within ±6 EFM clocks of its

expected position.

The sync coincidence signal is also used to generate the
lock signal which will go active HIGH when 1 sync
coincidence is found. It will reset to LOW when, during
61 consecutive frames, no sync coincidence is found.

FRAME SYNC PROTECTION DVD MODE
This circuit detects the frame synchronization signals.

Two synchronization counters are used in the SAA7335:

1. The coincidence counter: this is used to detect the
coincidence of successive syncs. It generates a sync
coincidence signal if 2 syncs are 1488 ±3 EFM+
clocks apart.

2. The main counter: this is used to partition the EFM+
signal into 16-bit words. This counter is reset when:

a) A sync coincidence is generated
b) A sync is found within ±10 EFM+ clocks of its

expected position.

The sync coincidence signal is also used to generate the
lock signal which will go active HIGH when 1 sync
coincidence is found. It will reset to LOW when, during
61 consecutive frames, no sync coincidence is found.

EFM/EFM+ demodulation

The 14-bit EFM (16-bit EFM+) data and subcode words
are decoded into 8-bit symbols.

1997 Aug 11 8

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

Microcontroller interface

The SAA7335 has two microcontroller interfaces, one
serial I2C-bus and one parallel (8051 microcontroller
compatible).

The two communication modes may be operated at the
same time, the modes are described below:

1. Parallel mode: protocol compatible with 8052
multiplexed bus:

a) da0 to da7 = address/data bus
b) ALE = Address Latch Enable, latches the address

information on the bus
WRi = active LOW write signal for write to

c)

SAA7335

d) RDi = active LOW read signal for read from

SAA7335

e) CSi = active HIGH Chip Select signal (this signal

gates the RDi and WRi signals).

2. I2C-bus mode: I2C-bus protocol where SAA7335
behaves as slave device where:

a) SDA = I2C-bus data
b) SCL = I2C-bus clock
c) I2C-bus slave address (write mode) = 3EH
d) I2C-bus slave address (read mode) = 3FH
e) Maximum data transfer rate = 400 kbits/s.

M

ICROCONTROLLER INTERFACE (I

2

C-BUS MODE)

SAA7335

The sequence for a write data command (1 data byte) is as
follows:

• Send START condition

• Send address 3EH (write)

• Write command address byte

• Write data byte

• Send STOP condition.

The sequence for a read data command (that reads 1 data
byte) is as follows:

• Send START condition

• Send address 3EH (write)

• Write status address byte

• Send STOP condition

• Send START condition

• Send address 3FH (read)

• Read data byte

• Send STOP condition.

R

EADING AND WRITING DATA TO THE SAA7335

The SAA7335 has 32 × 8-bit configuration and status
registers as shown in Table 1. Not all locations are
currently defined and some remain reserved for future
upgrades. These can be written to or read from via the
microcontroller interface using either the serial or parallel
control bus.

Bytes are transferred over the interface in single bytes of
which there are two types; write data commands and read
data commands.

1997 Aug 11 9

1997 Aug 11 10

REGISTER MAP

Table 1 SAA7335 microcontroller register map

ADDRESS

DEC HEX 7 6 5 4 3 2 1 0

0 0 PLL_LOCK W Lock Oride Pha_Oset PLL_Force_L

1 1 PLL_SET W SliceBW Integ_F0 PLLBW_F1 LP_BW_F3

2 2 PLL_FREQ W PLL frequency (8 MSBs)

3 3 PLL_EQU W PLL frequency (2 LSBs) equalizer tap α 1 equaliser tap α 2

4 4 PLL_F_MEAS W RL3_EN reserved EFM nominal setting (101110)

5 5 OUTPUT1 W Fmat(3 to 1) WCLK_Op BCLK_Op Fmat (0) SyncSwap (1 and 0)

6 6 OUTPUT2 W EBU_Valid EBU_On EBU control bits 28, 29 EBU control bits (1 to 4)

7 7 OUTPUT3 W WCLK_H_

8 8 SEMA1 W general purpose semaphore register

9 9 SEMA2 W general purpose semaphore register

10 A SEMA3 W general purpose semaphore register

11 B INTEN W hardware pin interrupt enable bits (map to status bits)

12 C MOTOR1 W frequency set point

13 D MOTOR2 W G(2 to 0) Ki Kf

NAME R/W

PLL_Freq_R R PLL measured frequency (bits 9 to 2)

PLL_ASSYM R PLL asymmetry value (8 bits)

PLL_Jit R jitter value (bits 9 to 2)

PLL_Lock_In R reserved Long_Symb F_Lock In_Lock

reserved R −−−−−− − −

reserved R −−−−−− − −

reserved R −−−−−− − −

Descr_On Interp_On CD_ROM_

Left

reserved R −−−−−− − −

R

R

R

Status R Fl_S1 Fl_S2 Fl_S3 PLL lock DVD rdy Mot Ov Tacho reserved

SLICE1 R slice compensation value

EYE_Open R eye opening value

Header_On

BIT

Flag_Pin Kill Data On Kill EBU_On CD_ROM_

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

Scrb_On

SAA7335

1997 Aug 11 11

ADDRESS

DEC HEX 7 6 5 4 3 2 1 0

14 E MOTOR3 W FIFO set point

15 F MOTO4 W PWM_PDM OVF_SW SW2 SW1 motor servo control (3 to 0)

16 10 MTR_INTG_L W motor integrator value (7 to 0)

17 11 MTR_INTG_H W motor integrator value (15 to 8)

18 12 CLOCKPRE W CL1Div BCLKG_En Div1 (2 to 0) Mux 2 Div2 (2 to 0)

19 13 DECMODE W mode reserved read TOC reserved

20 14 reserved W −−−−−− − −

21 15 ANASET W AGC_En gain set gain up gain down AGC_On reserved

22 16 VITSET W slice ON AdDet ON FEndAutoS

23 17 TACHO1 W tachometer multiplier frequency KTacho (7 to 0)

24 18 TACHO2 W tachometer interrupt trip frequency tachometer trip (7 to 0)

25 19 TACHO3 W servo control source Tacho

26 1A BCASET W BCA_Freq (7 to 0)

27 to311B to

1F

NAME R/W

MTR_F R −−−−−− − −

reserved R −−−−−− − −

R

R

SUB_C_STAT R ready busy CRC_OK err (2 to 0) cor fail reserved

SUB_C_DATA R subcode data (7 to 0)

SUB_C_End R no meaning (register read used as a signal)

FIFOFILL_L R number of C1 frames in FIFO

ON

BCA_STAT R Buff_

Loaded

BCA_DATA R BCA data (7 to 0)

reserved R −−−−−− − −

reserved R −−−−−− − −

reserved R −−−−−− − −
reserved −−−−−− − −

sync Buff_ORun

Moto2_T3 Fsam TachoInt_LF reserved

FRes

BIT

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

READING STATUS INFORMATION FROM THE SAA7335
There are several internal status signals which can be made available on the INT line (see Table 2).

Table 2 Internal status signals; note 1

SIGNAL DESCRIPTION

Fl_S1 change in semaphore register 1 detected
Fl_S2 change in semaphore register 2 detected
Fl_S3 change in semaphore register 3 detected
PLLlock channel data PLL lock (not latched) indicates in-lock condition
DVDrdy DVD header or subcode block is available, reset when SUBREADEND register is read
MotOv motor overflow, (not latched) indicates when a motor overflow is occurring
Tacho motor speed is higher (or lower depending on TACHO3 bit 2) than motor set point (defined in

TACHO2) this signal is not latched

Note

1. The status signal to be output is selected by interrupt control register.

Subcode data/DVD header processing

Q-

CHANNEL PROCESSING

The 96-bit Q-channel word is accumulated in an internal
buffer. Sixteen bits are used to perform a Cyclic
Redundancy Check (CRC). Subcode is available via the
V4 output and, in addition, the Q channel code can also be
read via the SUBREADDATA register.

DVD

HEADER

The DVD header processor accumulates a selection of
bytes from the beginning of the DVD sector. Two header
modes are defined, one for reading the normal sector
headers and one for filtering the disk physical format
information (from the control data block in the lead-in area)
This is controlled by the READ_TOC bit in the DECMODE
register.

O

THER SUBCODE CHANNELS

Data of the other subcode channels (Q-to-W) may be read
via the V4 pin, this is only valid in CD modes.

The data on the V4 pin is clocked on the WCLK edges with
a fixed delay and so may be clocked by external circuitry
running off the WCLK edges, i.e. at twice the WCLK
frequency.The subcode data is also available in the EBU
output (DOBM) in a similar format.

Crystal oscillator

The crystal oscillator is a conventional 2 pin design. This
oscillator is capable of operating with ceramic resonators

and with both fundamental and third overtone crystals.
External components should be used to suppress the
fundamental output of the third overtone crystals as shown
in Figs 3 and 4. Typical oscillation frequencies required
are 8.462, 16.9344 or 22.57 MHz depending on the
internal clock settings used and whether or not the clock
multiplier is enabled.

Error corrector

The error corrector can operate in a number of modes; CD
single-pass, CD dual-pass and DVD mode. In the CD
single-pass mode the error corrector performs 2 error
corrections per frame (C1 and C2). In the CD dual-pass
mode up to 4 symbol corrections per frame are possible
(C1-C2 then C1-C2 again). For the DVD mode full depth
PI and PO error correction is performed allowing
5 corrections per PI row and full depth (2t + e)
≤16 correction to be performed per PO column. The error
corrector also contains a flag controller. Flags are
assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read (after de-interleaving) by C2,
to help in the generation of C2 output flags. The C2 output
flags are used by the interpolator for concealment of
non-correctable errors. They are also output via the EBU
signal (DOBM) and the MISC output via the I
CD-ROM applications.

The flags output pin CFLG provides information on the
state of all error correction and concealment flags.

SAA7335

2

S-bus for

1997 Aug 11 12

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

handbook, halfpage

handbook, halfpage

SAA7335

OSCILLATOR

330 Ω

Fig.3 8.4672 MHz fundamental configuration.

SAA7335

8.4672 MHz

100 kΩ

22

22

pF

pF

SAA7335

CRINCROUT

MGK243

OSCILLATOR

CRINCROUT

22.57 MHz

330 Ω

100 kΩ

10
pF

10
pF

3.3 µH

1 nF

MGK244

Fig.4 22.57 MHz overtone configuration.

Interpolation Hold Interpolation

OK Error OK Error Error Error OK OK

Fig.5 Concealment mechanism.

1997 Aug 11 13

MGA372

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

Audio functions

C

ONCEALMENT

A 1-sample linear interpolator becomes active if a single
sample is flagged as erroneous but cannot be corrected.
The erroneous sample is replaced by a level midway
between the preceding and following samples. Left and
right channels have independent interpolators.

If more than one consecutive non-correctable sample is
found the last good sample is held. A 1-sample linear
interpolation is then performed before the next good
sample (see Fig.5).

DAC Interface

The SAA7335 is compatible with a wide range of ROM
block decoders and Digital-to-Analog Converters DACs.
The seven main formats that are supported are given in
Table 3.

SAA7335

Table 3 DAC interface formats (notes 1, 2 and 3)

MODE BITS/WORD FORMAT

2

1 16 Philips I
2 16 EIAJ
3 24 Philips I
4 24 EIAJ
5 32 Philips I
6 32 EIAJ
7 variable Philips I

Notes

1. EIAJ is the abbreviation for Electronic Industries
Associated of Japan.

2. Number of BCLK periods per half WCLK period
(i.e. bits per sample).

3. Clock gating must be DISABLED for format mode 7.

S-bus

2

S-bus

2

S-bus

2

S-bus

handbook, full pagewidth

BCLK

DATA

MISC

WCLK

SYNC

D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14

flag-MSB (1 is unreliable) flag-LSB flag-MSB

left

right

MGK245

Fig.6 Philips I2S-bus data format 1 (16-bit word length).

1997 Aug 11 14

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

handbook, full pagewidth

BCLK

DATA

D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14

MISC

flag-MSB (1 is unreliable) flag-LSB flag-MSB

WCLK

SYNC

Fig.7 EIAJ (‘S’) data format 2 (16-bit word length).

right

SAA7335

left

MGK246

BCLK

handbook, full pagewidth

DATA

MISC

WCLK
SYNC

BCLK

handbook, full pagewidth

DATA

MISC

WCLK
SYNC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14

flag-MSB (1 is unreliable) flag-LSB flag-MSB

left

right

Fig.8 Philips I2S-bus data format 3 (24-bit word length).

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

flag-MSB (1 is unreliable)

right

flag-LSB flag-MSB

D15 D14

left

MGK248

MGK247

Fig.9 EIAJ (‘S’) data format 4 (24-bit word length).

1997 Aug 11 15

1997 Aug 11 16

BCLK
DATA

MISC

WCLK
SYNC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14

flag-MSB (1 is unreliable) flag-LSB flag-MSB

left

right

MGK249

Fig.10 Philips I2S-bus data format 5 (32-bit word length).

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

BCLK
DATA

MISC

WCLK
SYNC

D15 D14 D15 D14D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

flag-MSB (1 is unreliable) flag-LSB flag-MSB

right

left

MGK250

Fig.11 EIAJ (‘S’) data format 6 (24-bit word length).

SAA7335

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

handbook, full pagewidth

BCLK
DATA

FLAG

WCLK
SYNC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

flag-MSB (1 is unreliable) flag-LSB

left

SAA7335

variable number of clocks

D15 D14

flag-MSB

right

MGK251

Fig.12 Philips I2S-bus data format (variable word length).

EBU interface

The biphase-mark digital output signal at pin DOBM is in
accordance with the format defined by the

“IEC 958”

specification.
Three different modes can be selected via the EBU output

control register (address 1010).

F

ORMAT

The digital audio output consists of 32-bit words
(subframes) transmitted in biphase-mark code
(2 transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384 (see Table 4).

S

YNC

The sync word is formed by violation of the biphase rule
and therefore does not contain any data. Its length is
equivalent to 4 data bits. The three different sync patterns
indicate the following situations:

• Sync B: start of a block (384 words), word contains left
sample

• Sync M: word contains left sample (no block start)

• Sync W: word contains right sample.

A

UDIO SAMPLE

Left and right samples are transmitted alternately.

V

ALIDITY FLAG

Audio samples are flagged (bit 28 = logic 1) if an error has
been detected but was non-correctable. This flag remains
the same even if data is taken after concealment.

U

SER DATA

Subcode bits Q-to-W from the subcode section are
transmitted via the user data bit. This data is asynchronous
with the block rate.

C

HANNEL STATUS

The channel status bit is the same for left and right words.
Therefore a block of 384 words contains 192 channel
status bits. The category code is always CD. The bit
assignment is given in Table 5.

1997 Aug 11 17

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

Table 4 EBU word format

WORD BITS FUNCTION

Sync 0 to 3 −
Auxiliary 4 to 7 not used; normally zero
Error flags 4 CFLG error and interpolation flags when bit 3 of EBU control register is set

to logic 1
Audio sample 8 to 27 first 4 bits not used (always zero)
Validity flag 28 valid = logic 0
User data 29 used for subcode data (Q-to-W)
Channel status 30 control bits and category code
Parity bit 31 even parity for bits 4 to 30

Table 5 EBU channel status

WORD BITS FUNCTION

Consumer/professional 0 always zero
Control 1 to 4 copied from bits 3 to 0 of register OUTPUT2, normally should be set to a

copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when

copy permitted; bit 3 is logic 1 when recording has pre-emphasis
Reserved 5 to 7 always zero
Category code 8 to 15 CD; bit 8 = logic 1, all other bits = logic 0
Reserved 16 to 27 always zero
Clock accuracy 28 to 29 set by OUTPUT2 control register bits 5 and 4; 00 = level II, 01 = level III
Remaining 30 to 191 always zero

SAA7335

Spindle motor control

The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal
±8 frame FIFO and disc speed information are used to
calculate the motor control output signals.

Several output modes are supported:

1. Pulse density, 1-line,

2. Pulse density, 2-line (true complement output) (cannot
be used with tachometer control)

3. PWM output, 2-line.

The modes are selected via the motor output configuration
register.

P

ULSE DENSITY MODE

In the pulse density mode the motor output (pin MOTO1)
is the pulse density modulated motor output signal. A 50%

1997 Aug 11 18

duty cycle corresponds with the motor not actuated, higher
duty cycles mean acceleration, lower mean braking.

In this mode, the MOTO2 signal is the inverse of the
MOTO1 signal. Both signals change state only on the
edges of a internal clock signal.

Possible application diagrams are shown in Fig.13.

PWM

MODE,2-LINE

In the PWM mode the motor acceleration signal is put in
pulse-width modulation form on the MOTO1 output and
the motor braking signal is pulse-width modulated on the
MOTO2 output.

Figure 14 illustrates the PWM mode timing and Fig.15
illustrates a typical PWM mode application diagram.

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

OPERATIONAL MODES
The motor servo has a number of operational modes controlled by the motor mode register MOTOR4.

P

OWER LIMIT

To start and stop the spindle motor, a fixed positive or negative voltage is applied to the motor. This voltage can be
programmed as a percentage of the maximum possible voltage via the motor output configuration register (MOTOR4) to
limit current drain during start and stop. The following power limits are possible:

• 100% of maximum (no power limit)

• 75% of maximum

• 50% of maximum

• 37% of maximum.

L

OOP CHARACTERISTICS

The gain and crossover frequencies of the motor control loop can be programmed via the motor gain and bandwidth
register MOTOR2.

MOTO1

MOTO1

22 kΩ

22 kΩ

10 nF

V

DD

V

22 kΩ

SS

+
–

22 kΩ

M

+

SS

–

22 kΩ

22 kΩ

10 nF

V

SS

V

+
–

M

V

DD

Fig.13 Motor pulse density application diagrams.

V

SS

V

22 kΩ

10 nF

SS

MGA363 - 1

MOTO2

1997 Aug 11 19

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

t = 45 µs

rep

MOTO1

MOTO2

Accelerate Brake

t 240 ns

dead

SAA7335

MGA366

Fig.14 Motor 2-line PWM mode timing.

+

M

10 Ω

MOTO1 MOTO2

100 nF

V

SS

MGA365 - 2

Fig.15 Motor 2-line PWM mode application diagram.

1997 Aug 11 20

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

Flags output (CFLG) (open-drain output)

A 1-bit flag signal is available at the CFLG pin, this contains 11 bits running off the ADCCLK, each bit period is 7 ADCCLK
periods. This signal shows the status of the error corrector and interpolator and is updated every frame.

handbook, halfpage

START

bit

data bitspause

MGK252

Fig.16 Flags output format.

Table 6 Definition of flag bits

BIT

NUMBER

VALUE DESCRIPTION

0 1 START bit

1 to 3 000 C1 first or C1 last; note 1

001 C2 first, CD mode reserved, DVD mode; note 1
010 reserved; note 1
011 C2 last; note 1
100 corrector not active; note 1

all others reserved
4 core fail failure flag set because correction impossible; note 2
5 flag fail; note 3

9, 6 to 8 root count (3 to 0) this indicates the number of errors corrected; note 4

10 0 STOP bit

Notes

1. For DVD mode read PI for C1 and PO for C2.

2. This flag refers to the previous correction frame.

3. This flag refers to the previous correction frame (is not valid i.e. always logic 0 in DVD mode).

4. Bit order of root count is 9, then 6 to 8 for root count (3 to 0).

A

BSOLUTE TIME SYNC

The sync signal is the absolute time sync signal. In the CD mode it is the FIFO-passed subcode sync and relates the
position of the subcode sync to the audio data (DAC output). In the DVD mode it indicates the start of a new sector
header.

The flag may be used for special purposes such as synchronization of different players.

1997 Aug 11 21

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

V

DDA

V

i(max)

V

o(max)

I

o(max)

T

amb

T

stg

V

ESD

digital supply voltage −0.3 +6.5 V
analog supply voltage −0.3 +6.5 V
maximum input voltage (any input) note 1 −0.3 VDD+ 0.5 V
maximum output voltage (any output) note 1 − VDD+ 0.5 V
maximum output current (each output) −±10 mA
operating ambient temperature −20 +70 °C
storage temperature −55 +125 °C
electrostatic handling

human body model note 2 −2000 +2000 V
machine model note 3 −200 +200 V

Notes

1. This maximum value has an absolute maximum of 6.5 V independent of the supply voltage.

2. The human body model ESD simulation is equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor, which
produces a single discharge transient. Reference

to MIL-STD 883C method 3015.7)”

.

“Philips Semiconductors Test Method UZW-BO/FQ-A302 (similar

3. The machine model ESD simulation is equivalent to discharging a 200 pF capacitor via a resistor and series inductor
with effective dynamic values of 25 Ω and 2.5 µH, which produces a damped oscillating discharge. Reference

“Philips Semiconductors Test Method UZW-BO/FQ-B302 (similar to EIAJ IC-121 Test Method 20 condition C)”

.

QUALITY

This device will meet the requirements of the
in accordance with

“Quality Reference Handbook (order number 9397 750 00192)”

for all Q & R tests applied to the product.

“Philips Semiconductors General Quality Specification UZW-BO/FQ-0601”

. This details the acceptance criteria

1997 Aug 11 22

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

DC CHARACTERISTICS

V

DDD=VDDA

= 5 to 5.5 V; V

SSD=VSSA

=0V; T

= −20 to +70 °C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDD

V

DDA

I

DD(tot)

digital supply voltage 4.5 − 5.5 V
analog supply voltage 4.5 − 5.5 V
total supply current at 25 MHz clock − 60 − mA

Inputs

D

IGITAL INPUTS (TTL LEVEL); note 1

V

IL

V

IH

V

OL

V

OH

LOW-level input voltage −−0.8 V
HIGH-level input voltage 2.0 −−V
LOW-level output voltage 0.8 −−V

HIGH-level output voltage −−2.4 V
ANALOG INPUTS
V

I(max)(p-p)

maximum input voltage

−−2V

(peak-to-peak value)
V

I(nom)(p-p)

nominal input voltage

− 1 − V

(peak-to-peak value)
DR dynamic range 41 −−dB
B −3 dB bandwidth 0 to 12 dB gain −−−MHz

12 to 20 dB gain −−−MHz

I

I(AGC)

I

I(ADC)

I

I(buf)

I

I(tot)

AGC input current − 1 − mA

ADC input current − 24 − mA

output buffer input current − 3 − mA

total input current −−28 mA

Note

1. These inputs are analog, V

and VIH values are quoted as a guide for digital RGB users.

IL

AC CHARACTERISTICS

V

DDD=VDDA

= 4.5 to 5.5 V; V

SSD=VSSA

=0V; T

= −20 to +70 °C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
I

DDD

V
I

DDA

DDD

DDA

digital supply voltage 4.5 5.0 5.5 V

digital supply current V

=5V − 60 165 mA

DDD

analog supply voltage 4.5 5.0 5.5 V

analog supply current V

=5V − 60 165 mA

DDA

1997 Aug 11 23

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog front-end (V

f

chan

channel frequency −−50 MHz

= 4.5 to 5.5 V); HFIN

DDA

Digital inputs

V

IL

V

IH

I

LI

C

i

LOW-level input voltage −−0.8 V

HIGH-level input voltage 2.0 −− V

input leakage current Vi= 0 to V

DDD

−10 − +10 µA

input capacitance −−10 pF

Open-drain output; pin INT

V

OL

I

OL

C

L

t

o(f)

LOW-level output voltage IOL= 1 mA 0 − 0.4 V

LOW-level output current −−0mA

load capacitance −−50 pF

output fall time CL= 20 pF; note 1 −−15 ns

3-state outputs

V

OL

V

OH

C

L

t

o(r)

t

o(f)

I

LI(Z)

LOW-level output voltage IOL= 0 mA 0 − 0.4 V

HIGH-level output voltage IOH= −8 mA 2.4 −− V

load capacitance −−50 pF

output rise time CL= 20 pF; note 1 −−15 ns

output fall time CL= 20 pF; note 1 −−15 ns

3-state leakage current Vi= 0 to V

DDD

−10 − +10 µA

3-state outputs; pins MOTO1, MOTO2 and DOBM

V

OL

LOW-level output voltage V

= 4.5 to 5.5 V;

DDD

0 − 0.8 V

IOL=10mA

V

OH

HIGH-level output voltage V

= 4.5 to 5.5 V;

DDD

−1 − +2.4 V

IOH= −10 mA

C

L

t

o(r)

t

o(f)

I

LI(Z)

Digital input/outputs (V

I

NPUT/OUTPUT: SDA (INPUT/OPEN-DRAIN I

V

IL

V

IH

V

OL

I

OL

C

SDA

C

SCL

N

marL

N

marH

load capacitance −−50 pF

output rise time CL= 20 pF; note 1 −−10 ns

output fall time CL= 20 pF; note 1 −−10 ns

3-state leakage current Vi= 0 to V

= 4.5 to 5.5 V)

DDD

2

C-BUS OUTPUT)

DDD

−10 − +10 µA

LOW-level input voltage −−1.5 V

HIGH-level input voltage 3.0 −− V

LOW-level output voltage IOL= 2 mA;

I

=3mA

sink

−−0.4 V

LOW-level output current −−− mA

serial data line capacitance −−10 pF

serial clock line capacitance −−10 pF

LOW-level noise margin − 0.1V

HIGH-level noise margin − 0.2V

DDD
DDD

−

−

1997 Aug 11 24

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

s

series resistance on the SDA and

− 300 −Ω

SCL lines
C

bus(max)

maximum bus capacitance per wire − 400 − pF
INPUT: SCL (CMOS INPUT)
V

IL

V

IH

I

LI

C

i

LOW-level input voltage −0.3 − 0.3V

HIGH-level input voltage 0.7V

input leakage current Vi=0−V

DDD

−10 − +10 µA

DDD

− V

DDD

DDD

input capacitance −−10 pF

V

+ 0.3 V

Crystal oscillator input CRIN (external clock)

g

m

R

o

C

i

I

LI

mutual conductance at start-up − 4 − mS

output resistance at start-up − 11 − kΩ

input capacitance −−10 pF

input leakage current −10 − +10 µA
Crystal oscillator output CROUT (see Figs 3 and 4)
f

xtal

C

fb

C

o

2

S-bus timing

I

crystal frequency 4 25 − MHz

feedback capacitance −−5pF

output capacitance −−10 pF

CLOCK OUTPUT SCLK (see Fig.17)
T

cy

t

SCLKH

t

SCLKL

t

su(SCLK)

t

h(SCLK)

output clock period set by CLKPRE1

clock HIGH time −−− ns

clock LOW time −−− ns

set-up time − tbf − ns

hold time − tbf − ns

− 472.4 − ns

register

−−− ns

−−− ns

−−− ns

−−− ns

− tbf − ns

− tbf − ns

− tbf − ns

− tbf − ns

1997 Aug 11 25

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

External RAM timing (see Figs 18 and 20)

t

AV-DV

t

OE-DV

t

W(W)

t

su(A)

t

h(A)

t

su(D-EW)

t

h(D-EW)

t

OE-DA

t

OD-DI

address valid to data valid − tbf − ns

output enable to data valid − tbf − ns

write pulse width − tbf − ns

address set-up before start of write − tbf − ns

address hold after end of write − tbf − ns

data set-up to end of write − tbf − ns

data hold after end of write − tbf − ns

output enable to data active − tbf − ns

output disable to data inactive − tbf − ns
Microcontroller interface timing (see Figs 18 and 20)
I

NPUT ALE

t

su(A-ALE)

t

h(A-ALE)

t

ALEL

address set-up before ALE LOW 25 −− ns

address hold after ALE LOW 25 −− ns

input LOW time 1 × ADC

−− ns

CLK+15

t

ALEH

input HIGH time 1 × ADC

−− ns

CLK+15

t

d(ALEL-WRL)

t

r

t

f

delay time ALE LOW to WR LOW −−− ns

rise time −−− ns

fall time −−240 ns
INPUTS RDI AND WRI
t

IL(R/W)

input LOW time 1 × ADC

−− ns

CLK+15

t

IH(R/W)

input HIGH time 1 × ADC

−− ns

CLK+15

t

r

t

f

rise time −−− ns

fall time −−240 ns
READ MODE
t

d(RLDV)

t

d(RHDX)

delay time RD LOW to DA0 to DA7

valid

delay time RD HIGH to DA0 to DA7

2 × ADC

−− ns

CLK+35
15 −− ns

high-impedance
WRITE MODE
t

su(QVWX)

set-up time WR LOW to

−−− ns

DA0 to DA7
t

h(WHQX)

hold time WR HIGH to DA0 to DA7

3-state

2 × ADC
CLK+25

−− ns

Notes

1. Timing reference voltage levels are 0.8 V and V

DDD

− 0.8 V.

2. Negative set-up time means that data may change after clock transition.

1997 Aug 11 26

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

T

cy

SCLK

t

h(SCLK)

WCLK
DATA
MISC

t

SCKL

t

su(SCLK)

V – 0.8 V

DD

0.8 V

t

SCLKH

V – 0.8 V

DD

0.8 V

MGL507

SAA7335

handbook, full pagewidth

ALE

RDi

DA0

to

DA7

t

su(A-ALE)

t

h(A-ALE)

A0 to A7

Fig.17 I2S-bus timing.

t

ALEL

3

9

t

d(RLDV)

t

IH(R/W)

DATA OUT

t

d(RHDX)

t

ALEH

13

MGK253

Fig.18 Microcontroller interface timing; parallel read mode.

1997 Aug 11 27

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

handbook, full pagewidth

ALE

t

d(ALEL-WRL)

WRi

DA0

to

DA7

t

su(A-ALE)

t

h(A-ALE)

A0 to A7

t

su(QVWX)

t

IH(R/W)

DATA IN

t

h(WHDX)

SAA7335

9

MGK254

handbook, full pagewidth

WE

OE

ADDRESS

DATA

A0

t

su(A)

t

su(D-EW)

Fig.19 Microcontroller interface timing; parallel write mode.

t

W(W)

t

OE-DV

A1 A2 A3 A4

t

t

h(A)

D1

t

su(D-EW)

write cycle write cycleread cycle

OE-DA

X D2 D1

t

AD-DV

t

OD-DI

MBH995

Fig.20 External RAM timing.

1997 Aug 11 28

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

APPLICATION INFORMATION

The complete data path chipset consists of two ICs, the CD decoder (or DSP) device and the block decoder/host
interface manager. In addition to these components a general purpose microcontroller and tracking servo is necessary
to produce a complete controller system for a DVD mechanism. The DSP, block decoder and microcontroller are shown
highlighted in Fig.21. An ADC application circuit is illustrated in Fig.22.

handbook, full pagewidth

MECHANISM/SERVO SUBSYSTEM DECODER/DATA PATH SUBSYSTEM

RAM BUFFER

spindle

motor

laser

SLED/FOCUS

ACTUATORS

(3 BEAM OPTIONAL FOR

PRE-

AMPLIFIER

SERVO CONTROL

PD TRACKING

BACKWARD CD-ROM

COMPATIBILITY)

CD-DSP

DEMODULATION

C1-C2 ERROR CORRECTOR

AUDIO DAC

BLOCK

DECODER

(FOR CD-ROM

COMPATIBILITY)

AND

HOST

INTERFACE

RAM BUFFER

audio L/R

output

PC host

interface

user

key

switches

SYSTEM

CONTROLLER

Fig.21 Basic DVD player block diagram.

MGK255

1997 Aug 11 29

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

handbook, full pagewidth

HF input

AGND1

V

CC

R14

4.7 Ω

C11
47 µF
(50 V)

AGND1

TP1

AGND1

C16X6

2.2 nF

C10

100

nF

97
98
99
100

123456789

R29

10 kΩ

47 µF (50 V)

TP6

C19

R28

100 kΩ

C18

22
nF

C15

47 µF

(50 V)

SAA7335

C17

22
nF

V

CC

R25

4.7 Ω

C14
100 nF

SAA7335

TP5

AGND1

MGK256

Fig.22 ADC application circuit.

1997 Aug 11 30

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

PACKAGE OUTLINE

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

c

y

100

X

75

76

pin 1 index

1

e

w M

b

p

D

H

D

51

50

Z

E

26

25

Z

D

b

B

e

w M

p

v M

v M

A

H

E

E

A

B

A

2

A

A

1

detail X

SAA7335

SOT407-1

(A )

3

L

p

L

θ

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE
VERSION

SOT407-1

A

A1A2A3bpcE

max.

0.20

1.6

0.05

1.5

1.3

0.28

0.16

0.18

0.12

0.25

IEC JEDEC EIAJ

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1)

(1) (1)(1)

D

14.1

13.9

REFERENCES

eH

H

14.1

13.9

0.5

16.25

15.75

1997 Aug 11 31

D

E

16.25

15.75

LL

p

0.75

0.45

0.12 0.10.21.0

EUROPEAN

PROJECTION

Z

1.15

0.85

D

Zywv θ

E

1.15

0.85

o

7

o

0

ISSUE DATE

95-12-19
97-08-04

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

(order code 9398 652 90011).

SAA7335

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Aug 11 32

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

SAA7335

PURCHASE OF CD/DVD DEVICES

Supply of this CD/DVD IC does not convey an implied license under any patent right to use this IC in any CD or DVD
application.

2

PURCHASE OF PHILIPS I

C COMPONENTS

2

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

C components conveys a license under the Philips’ I2C patent to use the

1997 Aug 11 33

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

NOTES

1997 Aug 11 34

Philips Semiconductors Preliminary specification

DSP for CD and DVD-ROM systems

SAA7335

NOTES

1997 Aug 11 35

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547027/1200/01/pp36 Date of release: 1997 Aug 11 Document order number: 9397 750 01764