Datasheet saa7324 DATASHEETS (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

SAA7324

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

Product speciﬁcation Supersedes data of 1999 May 17 File under Integrated Circuits, IC01

2000 Jun 26

Page 2

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION

7.1 Decoder part

7.1.1 Principal operating modes of the decoder

7.1.2 Decoding speed and crystal frequency

7.1.3 Lock-to-disc mode

7.1.4 Standby modes

7.2 Crystal oscillator

7.3 Data slicer and clock regenerator

7.4 Demodulator

7.4.1 Frame sync protection

7.4.2 EFM demodulation

7.5 Subcode data processing

7.5.1 Q-channel processing

7.5.2 EIAJ 3 and 4-wire subcode (CD graphics) interfaces

7.5.3 V4 subcode interface

7.6 FIFO and error corrector

7.6.1 Flags output (CFLG)

7.7 Audio functions

7.7.1 De-emphasis and phase linearity

7.7.2 Digital oversampling filter

7.7.3 Concealment

7.7.4 Mute, full-scale, attenuation and fade

7.7.5 Peak detector

7.8 DAC interface

7.8.1 Internal bitstream digital-to-analog converter (DAC)

7.8.2 External DAC interface

7.9 EBU interface

7.9.1 Format

7.10 KILL circuit

7.11 Audio features off

7.12 The versatile pins interface

7.13 Spindle motor control

7.13.1 Motor output modes

7.13.2 Spindle motor operating modes

7.13.3 Loop characteristics

7.13.4 FIFO overflow

7.14 Servo part

7.14.1 Diode signal processing

7.14.2 Signal conditioning

7.14.3 Focus servo system

7.14.4 Radial servo system

7.14.5 Off-track counting

7.14.6 Defect detection

7.14.7 Off-track detection

7.14.8 High-level features

7.14.9 Driver interface

7.14.10 Laser interface

7.14.11 Radial shock detector

7.15 Microcontroller interface

7.15.1 Microcontroller interface (4-wire bus mode)

7.15.2 Microcontroller interface (I2C-bus mode)

7.15.3 Decoder registers and shadow registers

7.15.4 Summary of functions controlled by decoder

7.15.5 Summary of functions controlled by shadow

7.15.6 Summary of servo commands

7.15.7 Summary of servo command parameters 8 LIMITING VALUES 9 CHARACTERISTICS 10 OPERATING CHARACTERISTICS

11 OPERATING CHARACTERISTICS (I2S-BUS

12 OPERATING CHARACTERISTICS

13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING

15.1 Introduction to soldering surface mount

15.2 Reflow soldering

15.3 Wave soldering

15.4 Manual soldering

15.5 Suitability of surface mount IC packages for

16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS 19 PURCHASE OF PHILIPS I2C COMPONENTS

SAA7324

registers 0 to F

registers

(SUBCODE INTERFACE TIMING)

TIMING)

(MICROCONTROLLER INTERFACE TIMING)

packages

wave and reflow soldering methods

2000 Jun 26 2

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

1 FEATURES

• Integrated bitstream DAC with differential outputs,

operating at 96fs with 3rd-order noise shaper; typical performance of −90 dB signal-to-noise ratio

• Separate serial input and output interfaces allow data

‘loopback’ mode for use of onboard DAC with external Electronic Shock Absorption (ESA) systems

• Up to 4 times speed mode

• Low voltage operation at up to 2 times speed

• Lock-to-disc mode

• Full error correction strategy, t = 2 and e = 4

• Full CD graphics interface

• All standard decoderfunctions implemented digitally on

chip

• FIFO overflow concealment for rotational shock

resistance

• Digital audio interface (EBU), audio and data

• Twoand four timesoversampling integrated digital filter,

including fsmode

• Audio data peak level detection

• Kill interface forexternal DAC deactivation during digital

silence

• All SAA737x (CD7)digital servo and high-level functions

• Low focus noise

• Same playability performance as SAA737x (CD7)

• Automatic closed-loop gain control available for focus

and radial loops

• Pulsed sledge support

SAA7324

• Electronic damping of fast radial actuator during long jump

• Microcontroller loading LOW

• High-level servo control option

• High-level mechanism monitor

• Communication may be via TDA1301/SAA7345

compatible bus or I2C-bus

• On-chip clock multiplier allows the use of 8.4672,

16.9344 or 33.8688 MHz crystals or ceramic resonators.

2 GENERAL DESCRIPTION

The SAA7324 (CD10 II) is a single chip combining the functions of a CD decoder, digital servo and bitstream DAC. The decoder/servo part is based on the SAA737x (CD7) and is software compatible with this design. Extra functions are controlled by use of ‘shadow’ registers (see Section 7.15.3).

Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.

3 ORDERING INFORMATION

TYPE

NUMBER

SAA7324H QFP64 plastic quad ﬂat package; 64 leads (lead length 1.6 mm);

2000 Jun 26 3

NAME DESCRIPTION VERSION

body 14 × 14 × 2.7 mm

PACKAGE

SOT393-1

Page 4

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

xtal

amb

stg

S/N

DAC

Note

1. n = overspeed factor.

supply voltage n = 4 mode; note 1 3.0 3.3 3.6 V

n = 1 or 2 mode; note 1 2.4 − 3.6 V

supply current VDD= 3.3 V − 20 − mA

= 2.4 V − 14 − mA

crystal frequency 4 8.4672 35 MHz ambient temperature −10 − +70 °C storage temperature −55 − +125 °C onboard DAC signal-to-noise ratio 1 kHz; 1fs; see

−85 −90 − dB

Figs 38 and 39

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

5 BLOCK DIAGRAM

handbook, full pagewidth

R1 R2

RIN

SCL SDA RAB

SILD

HFIN

HFREF

ISLICE

ref

TEST1 TEST2 TEST3

12 13

40 39 41 42

2 1 3 6

25 31 44

D1 D2 D3 D4

8 9 10 11 4 14 5 17 33 50 58 52 57

ADC

ref

GENERATOR

MICROCONTROLLER

INTERFACE

DIGITAL

PLL

FRONT-END

EFM

DEMODULATOR

TEST

SRAM

SSA2

SSA1

PRE-

PROCESSING

DDA1

DDA2

CONTROL

PART

SSD2

SSD1

CONTROL

FUNCTION

SAA7324

DDD1(P)

SSD3

CORRECTOR

AUDIO

PROCESSOR

DDD2(C)

OUTPUT STAGES

MOTOR

CONTROL

ERROR

FLAGS

EBU

INTERFACE

SAA7324

LDON

MOTO1

MOTO2

CFLG

DOBM

SUB RCK

24 16 15 26 49

48 47 46 45

TIMING

DECODER

MICRO-

CONTROLLER

INTERFACE

RAM

ADDRESSER

SUBCODE

PROCESSOR

VERSATILE PINS

INTERFACE

63 34 61 62 32

V1 V2/V3 V4 V5 KILL

SELPLL

CRIN

CROUT

CL16

CL11/4

SBSY SFSY

STATUS

RESET

Fig.1 Block diagram.

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PEAK

DETECT

KILL

SERIAL DATA

INTERFACE

SERIAL DATA

(LOOPBACK)

INTERFACE

BITSTREAM

DAC

30 29 28 27

37 35 36

20 21 18 19 22 23

MGS174

EF SCLK WCLK DATA

SCLI WCLI SDI

neg

pos

LN LP RN RP

Page 6

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

6 PINNING

SYMBOL PIN DESCRIPTION

HFREF 1 comparator common mode input HFIN 2 comparator signal input ISLICE 3 current feedback output from data slicer V

SSA1

DDA1

ref

RIN

D1 8 unipolar current input 1 (central diode signal input) D2 9 unipolar current input 2 (central diode signal input) D3 10 unipolar current input 3 (central diode signal input) D4 11 unipolar current input 4 (central diode signal input) R1 12 unipolar current input 1 (satellite diode signal input) R2 13 unipolar current input 2 (satellite diode signal input) V

SSA2

CROUT 15 crystal/resonator output CRIN 16 crystal/resonator input V

DDA2

LN 18 DAC left channel differential negative output LP 19 DAC left channel differential positive output V

neg

pos

RN 22 DAC right channel differential negative output RP 23 DAC right channel differential positive output SELPLL 24 selects whether internal clock multiplier PLL is used TEST1 25 test control input 1 (this pin should be tied LOW) CL16 26 16.9344 MHz system clock output DATA 27 serial d4(1) data output (3-state) WCLK 28 word clock output (3-state) SCLK 29 serial bit clock output (3-state) EF 30 C2 error ﬂag output (3-state) TEST2 31 test control input 2 (this pin should be tied LOW) KILL 32 kill output (programmable; open-drain) V

SSD1

V2/V3 34 versatile I/O: versatile input 2 or versatile output 3 (open-drain) WCLI 35 word clock input (for data loopback to DAC) SDI 36 serial data input (for data loopback to DAC) SCLI 37 serial bit clock input (for data loopback to DAC) RESET 38 power-on reset input (active LOW) SDA 39 microcontroller interface data I/O line (I SCL 40 microcontroller interface clock line input (I

(1)

analog ground 1

analog supply voltage 1 6 reference current output 7 reference voltage for servo ADCs

(1)

analog ground 2

analog supply voltage 2

20 DAC negative reference input 21 DAC positive reference input

(1)

digital ground 1

C-bus; open-drain output)

C-bus)

SAA7324

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

SYMBOL PIN DESCRIPTION

RAB 41 microcontroller interface R/ SILD 42 microcontroller interface STATUS 43 servo interrupt request line/decoder status register output (open-drain) TEST3 44 test control input 3 (this pin should be tied LOW) RCK 45 subcode clock input SUB 46 P-to-W subcode bit 3-states output (3-state) SFSY 47 subcode frame sync output (3-state) SBSY 48 subcode block sync output (3-state) CL11/4 49 11.2896 or 4.2336 MHz (for microcontroller) clock output V

SSD2

(1)

digital ground 2

DOBM 51 bi-phase mark output (externally buffered; 3-state) V

DDD1(P)

(1)

digital supply voltage 1 for periphery

CFLG 53 correction ﬂag output (open-drain) RA 54 radial actuator output FO 55 focus actuator output SL 56 sledge control output V

DDD2(C)

SSD3

57 58

(1) (1)

digital supply voltage 2 for core

digital ground 3

MOTO1 59 motor output 1; versatile (3-state) MOTO2 60 motor output 2; versatile (3-state) V4 61 versatile output 4 V5 62 versatile output 5 V1 63 versatile input 1 LDON 64 laser drive on output (open-drain)

W and load control line input (4-wire bus mode)

R/W and load control line input (4-wire bus mode)

Note

1. All supply pins must be connected to the same external power supply voltage.

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

handbook, full pagewidth

LDONV1V5 64

HFREF

CROUT

1 2

HFIN

ISLICE V

SSA1

DDA1

ref

RIN

SSA2

CRIN 33

MOTO2

SSD3VDDD2(C)

MOTO1

SAA7324H

SL 56

FO 55

RA 54

CFLG 53

DDD1(P)

DOBM

SSD2

CL11/4

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34

SAA7324

SBSY SFSY SUB RCK TEST3 STATUS SILD RAB SCL SDA RESET SCLI SDI WCLI V2/V3 V

SSD1

DDA2

19 LP

neg

pos

22 RN

23 RP

SELPLL

Fig.2 Pin configuration.

7 FUNCTIONAL DESCRIPTION

7.1 Decoder part

7.1.1 PRINCIPAL OPERATING MODES OF THE DECODER The decoding part supports a full audio specification and

can operate at two different disc speeds, from single-speed(n = 1)to4 times speed (n = 4). The factor‘n’ is called the overspeed factor. A simplified data flow through the decoder part is illustrated in Fig.7.

2000 Jun 26 8

MGS175

KILL 49

TEST1

CL16

DATA

WCLK

SCLK

TEST2

7.1.2 DECODING SPEED AND CRYSTAL FREQUENCY The SAA7324 is a two speed decoding device, with an

internal Phase-Locked Loop (PLL) clock multiplier. Depending on the crystal frequency used and the internal clock settings (selectable via decoder register B), the playback speeds shown in Table 1 are possible, where ‘n’ is the overspeed factor (1, 2 or 4).

An internal clock multiplier is present, controlled by SELPLL, and should only be used if a 8.4672 or

16.9344 MHz crystal, ceramic resonator or external clock is present.

Page 9

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.1.3 LOCK-TO-DISC MODE Forelectronicshockabsorptionapplications,theSAA7324

can be put into lock-to-disc mode. This allows Constant Angular Velocity (CAV) disc playback with varying input data rates from the inside-to-outside of the disc.

In the lock-to-disc mode, the FIFO is blocked and the decoder will adjust its output data rate to the disc speed. Hence, the frequency of the I2S-bus (WCLK and SCLK) clocksare dependent on thediscspeed.In the lock-to-disc mode there is a limit on the maximum variation in disc speed that the SAA7324 will follow. Disc speeds must always be within 25% to 100% range of their nominal value. The lock-to-disc mode is enabled/disabled by decoder register E.

7.1.4 STANDBY MODES The SAA7324 may be placed in two standby modes

selected by decoder register B (it should be noted that the device core is still active):

• Standby 1: CD-STOP mode; most I/O functions are switched off

SAA7324

• Standby 2: CD-PAUSE mode; audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active; this is also called a ‘Hot Pause’.

In the standby modes the various pins will have the following values:

• MOTO1 and MOTO2: put in high-impedance, PWM mode (standby 1 and reset: operating in standby 2); put in high-impedance, PDM mode (standby 1 and reset: operating in standby 2)

• SCL and SDA: no interaction; normal operation continues

• SCLK, WCLK, DATA, EF and DOBM: 3-state in both standby modes; normal operation continues after reset

• CRIN, CROUT, CL16 and CL11/4: no interaction; normal operation continues

• V1, V2/V3, V4, V5 and CFLG: no interaction; normal operation continues.

Table 1 Playback speeds

00XX 0XXX 0 n= 1 −− 11.2896 00XX 0XXX 1 −−n = 1 11.2896 01XX 0XXX 0 − n=1 − 5.6448 01XX 0XXX 1 − n=1 − 11.2896 10XX 0XXX 0 n= 2 −− 11.2896 10XX 0XXX 1 −−n = 2 11.2896 11XX 0XXX 0 − n=2 11XX 0XXX 1 − n=2 − 11.2896 00XX 1XXX 0 n = 4 00XX 1XXX 1 −−n = 4 11.2896 01XX 1XXX 0 − n=4 01XX 1XXX 1 − n=4 − 11.2896

Notes

1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).

2. Data capture performance is not optimized for this option.

CRYSTAL FREQUENCY (MHz)

33.8688 16.9344 8.4672

(2)

−− 11.2896

(2)

− 5.6448

CL11 FREQUENCY (MHz)

(1)

2000 Jun 26 9

Page 10

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.2 Crystal oscillator

The crystal oscillator is a conventional 2-pin design operating between 8 and 35 MHz. This oscillator is capable of operating with ceramic resonators and with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown in Figs 3 and 4. Typical oscillation frequencies required are

8.4672, 16.9344 or 33.8688 MHz depending on the

internal clock settings used and whether or not the clock multiplier is enabled.

handbook, halfpage

SAA7324

CROUT

OSCILLATOR

8.4672 MHz

CRIN

33 pF33 pF

MBL181

SAA7324

7.3 Data slicer and clock regenerator

The SAA7324 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 4 times the crystal frequency clock (if SELPLL is set HIGH while using a 16.9344 MHz crystal and register 4 is set to 0XXX), or 8 times the crystal frequency clock (if SELPLLis set HIGH whileusing an 8.4672 MHz crystal, and register 4 is set to 0XXX). The slice level is controlled by an internal current source applied to an external capacitor under the control of the Digital Phase-Locked Loop (DPLL).

Regeneration of the bit clock is achieved with an internal fully digital PLL.No external components are required and the bit clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization. The PLL response is shown in Fig.5.

For certain applications an off-track input is necessary. This is internally connected from theservo part (itspolarity can be changedby the foc_parm1 parameter), but may be input via the V1 pin if selected by register C. If this flag is HIGH, the SAA7324 will assume that its servo part is following on the wrong track, and will flag all incoming HF data as incorrect.

Fig.3 8.4672 MHz fundamental configuration.

handbook, halfpage

SAA7324

CROUT

MBL182

OSCILLATOR

33.8688 MHz

Fig.4 33.8688 MHz overtone configuration.

CRIN

3.3 µH

handbook, halfpage

PLL loop

response

3. PLL, LPF

2. PLL bandwidth

1. PLL integrator

1 nF10 pF10 pF

1, 2 and 3 are all programmable via decoder register 8.

MGS178

Fig.5 Digital PLL loop response.

2000 Jun 26 10

Page 11

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

HF input

SSA

100 nF

1 nF

22 kΩ

100 nF

47 pF

2.2 kΩ

SSA

HFREF

HFIN

ISLICE

100 µA

crystal

clock

SAA7324

DPLL

MGS179

Fig.6 Data slicer showing typical application components (for n = 1).

7.4 Demodulator

7.4.1 FRAME SYNC PROTECTION

A double timing system is used to protect thedemodulator from erroneous sync patterns in the serial data. The master counter is only reset if:

• A sync coincidence is detected; sync pattern occurs

588 ±1 EFM clocks after the previous sync pattern

• A new sync pattern is detected within ±6 EFM clocks of

its expected position.

The sync coincidence signal is also used to generate the PLL lock signal, which is active HIGH after 1 sync coincidence is found, and reset LOW if during 61 consecutiveframesnosync coincidence is found. The PLL lock signal can be accessed via the SDA or STATUS pins selected by decoder registers 2 and 7.

Also incorporated in the demodulator is a Run Length 2 (RL2)correction circuit. Everysymbol detected asRL2 will be pushed back to RL3. To dothis, the phase error of both edges of theRL2 symbol are compared and the correction is executed at the side with the highest error probability.

7.4.2 EFM DEMODULATION The 14-bit EFMdata and subcode words are decoded into

8-bit symbols.

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Page 12

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2000 Jun 26 12

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RCK

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

decoder with integrated DAC (CD10 II)

output from

data slicer

SUBCODE

PROCESSOR

DIGITAL PLL

AND

DEMODULATOR

FIFO

ERROR

CORRECTOR

0: reg D = XX01

V4 SUBCODE

INTERFACE

FADE/MUTE/

INTERPOLATE

CD GRAPHICS

INTERFACE

1: decoder reg A = XX0X 0: decoder reg A ≠ XX1X

1 0

DIGITAL

FILTER

decoder reg 3

KILL

decoder reg C

reg F

1: decoder reg 3 = XX10 (1fs mode) 0: decoder reg 3 ≠ XX10

1 0

KILL V3

SBSY SFSY SUB

PHASE

COMPENSATION

DE-EMPHASIS

FILTER

MICROCONTROLLER

INTERFACE

1: no pre-emphasis detected OR reg D = 01XX (de-emphasis signal at V5) 0: pre-emphasis detected AND reg D ≠ 01XX

SDA

EBU

INTERFACE

decoder reg A

I2S/EIAJ BUS

INTERFACE

decoder

reg 3

1: decoder reg 3 ≠ 101X 0: decoder reg 3 = 101X (CD-ROM modes)

DOBM

1: shadow reg 7 = XX1X 0: shadow reg 7 = XX0X

SCLK

WCLK DATA

ONBOARD

DAC

1 0

1: shadow reg 7 = XX1X 0: shadow reg 7 = XX0X

I2S/EIAJ LOOPBACK INTERFACE

WCLI SCLI SDI

LP RN

neg

1: shadow reg 7 = XXX1 0: shadow reg 7 = XXX0

MGS180

SAA7324

Fig.7 Simplified data flow of decoder functions.

Page 13

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.5 Subcode data processing

7.5.1 Q-CHANNEL PROCESSING The 96-bit Q-channel word is accumulated in an internal

buffer. The last 16 bits are used internally to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go LOW. SUBQREADY-I can bereadvia the SDA or STATUS pins,selectedviadecoder register 2. Good Q-channel data may be read from SDA.

7.5.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)

INTERFACES

Data from all the subcode channels (P-to-W) may be read via the subcode interface, which conforms to EIAJ CP-2401.The interface isenabled and configured as either a 3 or 4-wire interface via decoder register F.

SAA7324

The subcode interface output formats are illustrated in Fig.8, where the RCK signal is supplied by another device such as a CD graphics decoder.

7.5.3 V4 SUBCODE INTERFACE Dataofsubcodechannels,Q-to-W, may be read via pin V4

if selected via decoder register D. The format is similar to RS232 and is illustrated in Fig.9. The subcode sync word is formed by a pause of (200/n) µs minimum. Each subcode byte starts with a logic 1 followed by 7 bits (Q-to-W). The gap between bytes is variable between (11.3/n) µs and (90/n) µs.

The subcode data is also available in the EBU output (DOBM) in a similar format.

handbook, full pagewidth

SBSY

SFSY

RCK

SUB

SFSY

RCK

SUB

SF0 SF1

SF0 SF1 SF2 SF3 SF97 SF0 SF1

SFSY

RCK

SUB

SF2 SF3 SF97 SF0 SF1

P-W P-W P-W

EIAJ 4-wire subcode interface

P-W P-W P-W

EIAJ 3-wire subcode interface

PQRSTUVW

MBG410

Fig.8 EIAJ subcode (CD graphics) interface format.

2000 Jun 26 13

Page 14

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

200/n µs

min

W96 1QRSTUVW 1Q

n = disc speed.

7.6 FIFO and error corrector

The SAA7324 has a ±8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1 (32 symbol)and C2(28 symbol)frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up to two errors on the C1 level and up to four errors on the C2 level.

The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read after (de-interleaving) by C2, to help in the generation of C2 output flags.

The C2 output flags are used by the interpolator for concealment of uncorrectableerrors. They are also output via the EBU signal (DOBM). The EF output will flag bytes in error in both audio and CD-ROM modes.

11.3/n µs

Fig.9 Subcode format and timing on pin V4.

SAA7324

11.3/n µs min 90/n µs max

MBG401

7.6.1 FLAGS OUTPUT (CFLG) The flags output pin CFLG shows the status of the error

corrector and interpolator and is updated every frame (7.35 × n kHz). In the SAA7324 chip a 1-bit flag is present on the CFLG pinas illustrated in Fig.10. This signal shows the status of the error corrector and interpolator.

The first flag bit, F1, is the absolute time sync signal, the FIFO-passed subcode sync and relates theposition of the subcode sync to the audio data (DAC output). This flag mayalso be used in asuperFIFO or in thesynchronization of different players. The output flags can be made available at bit 4 of the EBU data format (LSB of the 24-bit data word), if selected by decoder register A.

handbook, full pagewidth

n = disc speed.

33.9/n µs

11.3/n µs

F1 F2 F3 F4 F5 F6 F7 F8 F1F8

Fig.10 Flag output timing diagram.

2000 Jun 26 14

33.9/n µs

MBG425

Page 15

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

Table 2 Output ﬂags

F1 F2 F3 F4 F5 F6 F7 F8 DESCRIPTION

0XXXXXXXno absolute time sync 1XXXXXXXabsolute time sync X00XXXXXC1frame contained no errors X01XXXXXC1frame contained 1 error X10XXXXXC1frame contained 2 errors X11XXXXXC1frame uncorrectable X X X 0 0 X X 0 C2 frame contained no errors X X X 0 0 X X 1 C2 frame contained 1 error X X X 0 1 X X 0 C2 frame contained 2 errors X X X 0 1 X X 1 C2 frame contained 3 errors X X X 1 0 X X 0 C2 frame contained 4 errors X X X 1 1 X X 1 C2 frame uncorrectable XXXXX00Xno interpolations XXXXX01Xat least one 1-sample interpolation XXXXX10Xat least one hold and no interpolations XXXXX11Xat least one hold and one 1-sample interpolation

SAA7324

7.7 Audio functions

7.7.1 DE-EMPHASIS AND PHASE LINEARITY When pre-emphasis is detected in the Q-channel

subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to ≤±1° within the band 0 to 16 kHz. With de-emphasis the filter is not phase linear.

If the de-emphasis signal is set to be available at V5, selected via decoder register D, then the de-emphasis filter is bypassed.

7.7.2 DIGITAL OVERSAMPLING FILTER For optimizing performance with an external DAC, the

SAA7324 contains a 2 to 4 times oversampling IIR filter. The filter specification of the 4 times oversampling filter is given in Table 3.

These attenuations do not include the sample-and-hold at theexternal DAC output ortheDAC post filter. Whenusing the oversampling filter, the output level is scaled −0.5 dB down to avoid overflow on full-scale sine wave inputs (0 to 20 kHz).

Table 3 Filter speciﬁcation

PASS BAND STOP BAND ATTENUATION

0 to 9 kHz −≤0.001 dB

19 to 20 kHz −≤0.03 dB

− 24 kHz ≥25 dB

− 24 to 27 kHz ≥38 dB

− 27 to 35 kHz ≥40 dB

− 35 to 64 kHz ≥50 dB

− 64 to 68 kHz ≥31 dB

− 68 kHz ≥35 dB

− 69 to 88 kHz ≥40 dB

7.7.3 C A 1-sample linear interpolator becomes active if a single

sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more thanoneconsecutive non-correctable sample is found,the last good sampleis held. A 1-sample linear interpolation is then performed before the next good sample (see Fig.11).

In CD-ROM modes (i.e. the external DAC interface is selected to be in a CD-ROM format) concealment is not executed.

ONCEALMENT

2000 Jun 26 15

Page 16

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.7.4 MUTE, FULL-SCALE, ATTENUATION AND FADE A digital level controller is present on the SAA7324 which

performs the functions of soft mute, full-scale, attenuation and fade; these are selected via decoder register 0:

• Mute: signal reduced to 0 in a maximum of 128 steps; (3/n) ms

• Attenuation: signal scaled by −12 dB

• Full-scale: ramp signal back to 0 dB level; from mute

takes (3/n) ms

• Fade: activates a 128 stage counter which allows the signal to be scaled up/down by 0.07 dB steps

– 128 = full-scale – 120 = −0.5 dB (i.e. full-scale if oversampling filter

used) –32=−12 dB – 0 = mute.

SAA7324

7.7.5 PEAK DETECTOR The peak detector measures the highest audio level

(absolute value) on positive peaks for left and right channels. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81 to 88 contain the left peak value (bit 88 = MSB) and bits 89 to 96 contain the right peak value (bit 96 = MSB). The values are reset after reading Q-channel data via pin SDA.

Interpolation Hold Interpolation

OK Error OK Error Error Error OK OK

Fig.11 Concealment mechanism.

MGA372

2000 Jun 26 16

Page 17

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

7.8 DAC interface

7.8.1 INTERNAL BITSTREAM DIGITAL-TO-ANALOG CONVERTER (DAC) The onboard bitstream DACoperates at aclock frequency of96fsand is designed foroperation with anaudio input at 1fs.

Optimum performance is dependent on the application circuit used and careful consideration should be given to the recommended application circuits shown in Figs 38 and 39. The onboard DAC is controlled from shadow register 7 (see Section 7.15.3 for definition of shadow registers). This shadow register controls routing of data into the onboard DAC and also controls the DAC output pins, which can be held at zero when the onboard DAC is not required; see Table 4:

Audio data from the decoder part of the SAA7324 can be routed as described in Sections 7.8.1.1 and 7.8.1.2.

Table 4 Shadow register

SHADEN

1 0111 (7H) control of

SHADOW

ADDRESS

XXX0 hold onboard DAC outputs at zero reset

onboard DAC

XXX1 enable onboard DAC outputs − XX0X use external DAC or route audio data into

onboard DAC (loopback mode)

XX1X route audio data into onboard DAC

(non-loopback mode)

reset

−

7.8.1.1 Use onboard DAC

Setting shadow register 7 to XX11 will route audio data fromthe CD10 decoderinto the internalDAC, and enables the DAC output pins (LN, LP, RN and RP). To enable the on-boardDAC,theDAC interface format (set by register 3) must be set to 16-bit 1fsmode, either I2S or EIAJ format. CD-ROM mode can also be used if interpolation is not required. The serialdata output pins for interfacing with an external DAC (SCLK, WCLK, DATA and EF) are set to high-impedance.

7.8.1.2 Loopback external data into onboard DAC

The onboard DAC can also be set to accept serial data inputs from an external source, e.g. an Electronic Shock Absorption (ESA) IC.Thisisknownasloopback mode and is enabled by setting shadow register 7 to XX01.

This enables the serial data output pins (SCLK, WCLK, DATA and EF) so that data can be routed from the SAA7324 to an external ESA system (or external DAC).

The serial data from an external ESA IC can then also be input to the onboard DAC on the SAA7324 by utilising the serial data input interface (SCLI, SDI and WCLI).

In this mode, a wide range of data formats to the external ESA IC can be programmed as shown in Table 5. However, the serial input on the SAA7324 will always expect the input data from the ESA IC to be 16-bit 1fsand the same data format, either I2S-bus or EIAJ, as the serial output format (set by decoder register 3).

2000 Jun 26 17

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.8.2 EXTERNAL DAC INTERFACE Audio data from the SAA7324 can be sent to an external

DAC, identical tothe SAA737x series.This is similar to the ‘loopback’ mode, but in this case the internal DAC outputs can be held at zero. i.e. shadow register 7 is set to XX00. The SAA7324 is compatible with a wide range of external DACs. Eleven formats are supported and are given in Table 5. Figures 12 and 13 show the Philips I2S-bus and the EIAJ data formats respectively. When the decoder is operated in lock-to-disc mode, the SCLK frequency is dependent on the disc speed factor ‘d’.

Table 5 DAC interface formats

1010 f 1011 f 1110 f 0010 f 0110 f 0000 4f 0100 4f 1100 4f 0011 2f 0111 2f 1111 2f

SAMPLE

FREQUENCY

s s s s s

s s s s s s

NUMBER OF

BITS

SCLK (MHz) FORMAT INTERPOLATION

16 2.1168 × n CD-ROM (I2S-bus) no 16 2.1168 × n CD-ROM (EIAJ) no

(1)

16/18

2.1168 × n Philips I2S-bus 16/18 bits 16 2.1168 × n EIAJ 16 bits yes 18 2.1168 × n EIAJ 18 bits yes 16 8.4672 × n EIAJ 16 bits yes 18 8.4672 × n EIAJ 18 bits yes 18 8.4672 × n Philips I2S-bus 18 bits yes 16 4.2336 × n EIAJ 16 bits yes 18 4.2336 × n EIAJ 18 bits yes 18 4.2336 × n Philips I2S-bus 18 bits yes

SAA7324

All formats are MSB first and fs is (44.1 × n) kHz. The polarity of the WCLK and the data can be inverted; selectable by decoder register 7. It should be noted that EF is only a defined output in CD-ROM and 1fsmodes.

When using an external DAC (or when using the onboard DAC in non-loopback mode), the serial data inputs to the onboard DAC (SCLI, SDI and WCLI) should be left unconnected.

(1)

yes

Note

1. Inthis mode thefirst 16 bits containdata, but if anyof the fade,attenuate or de-emphasis filter functions are activated then the first 18 bits contain data.

2000 Jun 26 18

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2000 Jun 26 19

SCLK

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

decoder with integrated DAC (CD10 II)

WCLK

EF (CD-ROM AND Ifs MODES ONLY)

SCLK

WCLK

LSB error flag MSB error flag LSB error flag MSB error flag

15 14

LEFT CHANNEL DATA (WCLK NORMAL POLARITY)

15 1410DATA

MBG424

Fig.12 Philips I2S-bus data format (16-bit word length shown).

LEFT CHANNEL DATA

170DATA

EF (CD-ROM AND Ifs MODES ONLY)

MSB error flag LSB error flag MSB error flag

MBG423

SAA7324

Fig.13 EIAJ data format (18-bit word length shown).

Page 20

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

7.9 EBU interface

The bi-phase mark digital output signal at pin DOBM is in accordance with the format defined by the IEC 958 specification. Three different modes can be selected via decoder register A:

• DOBM pin held LOW

• Data taken before concealment, mute and fade (must

always be used for CD-ROM modes)

• Data taken after concealment, mute and fade.

Table 6 Format

FUNCTION BITS DESCRIPTION

Sync 0 to 3 − Auxiliary 4 to 7 not used; normally zero Error ﬂags 4 CFLG error and interpolation ﬂags when selected by register A Audio sample 8 to 27 ﬁrst 4 bits not used (always zero); 2’s complement; LSB = bit 12, MSB = bit 27 Validity ﬂag 28 valid = logic 0 User data 29 used for subcode data (Q-to-W) Channel status 30 control bits and category code Parity bit 31 even parity for bits 4 to 30

7.9.1 FORMAT The digital audio output consists of 32-bit words

(‘subframes’) transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. The formats are given in Table 6.

Table 7 Description of Table 6

FUNCTION DESCRIPTION

Sync The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.

Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample

(no block start) and sync W: word contains right sample. Audio sample Left and right samples are transmitted alternately. Validity ﬂag Audio samples are ﬂagged (bit 28 = 1) if an error has been detected but was uncorrectable. This

ﬂag remains the same even if data is taken after concealment. User data Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is

asynchronous with the block rate. Channel status The channel status bit is the same for left and right words. Thereforea block of 384 words contains

192 channel status bits. The category code is always CD. The bit assignment is given in Table 8.

Table 8 Bit assignment

FUNCTION BITS DESCRIPTION

Control 0 to 3 copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when

copy permitted; bit 3 is logic 1 when recording has pre-emphasis Reserved mode 4 to 7 always zero Category code 8 to 15 CD: bit 8 = logic 1, all other bits = logic 0 Clock accuracy 28 to 29 set by register A; 10 = level I; 00 = level II; 01 = level III Remaining 6 to 27 and 30 to 191 always zero

2000 Jun 26 20

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.10 KILL circuit

The KILL circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel prior to the digital filter. The output is switched to active LOW when silence has been detected for at least 270 ms, or if mute is active, or in CD-ROM modes. Two modes are available which can be selected by decoder register C:

1. Pin KILL: KILL active LOW indicates silence detected on both left and right channels

2. Pin KILL: KILL active LOW indicates silence detected on left channel. V3 active LOW indicates silence detected on right channel.

It should be noted that when mute is active or in CD-ROM modes the output(s) are switched LOW.

7.11 Audio features off

The audio features can be turned off (selected by decoder register E) which affects the following functions:

• Digital filter, fade, peak detector, KILL circuit (but

outputs KILL, V3 still active) are disabled

• V5 (if selected to be the de-emphasis flag output) and

the EBU outputs become undefined.

SAA7324

It should be noted that the EBU output should be set LOW prior to switchingthe audio features off and after switching the audio features back on, a full-scale command should be given.

7.12 The versatile pins interface

The SAA7324 has four pins that can be reconfigured for different applications. One of these pins, V2/V3, can be programmedas an input (V2) oras an output (V3). Control of the V2/V3 pin is via shadow register 3; see Table 9.

Selection of the V2/V3 pin does not affect the function programmed by decoder register C i.e. the V2 or V3 pin can be changed from V2/V3 function either before or after setting the desired function via decoder register 1100. Selection of, for instance, a V3 function while the V2/V3 pin is set to V2 will not affect the V2 functionality.

The functions of these versatile pins is identical to the SAA737x series. The functions of these versatile pins is programmed by decoder registers C and D, as shown in Table 10.

Table 9 V2 or V3 conﬁguration

SHADEN ADDRESS REGISTER DATA FUNCTION RESET

1 0011 (3H) control of

V2 or V3 pin

Table 10 Pin applications

PIN NAME

V1 63 input 1100 XXX1 external off-track signal input

V2 36 input −−input may be read via decoder status bit;

V3 36 output 1100 XX0X KILL output for right channel

V4 61 output 1101 0000 4-line motor drive (using V4 and V5)

V5 62 output 1101 01XX de-emphasis output (active HIGH)

NUMBER

TYPE

0XXX V2/V3 pin conﬁgured as V2 input reset 1XXX V2/V3 pin conﬁgured as V3 output (open-drain)

− XXX0 internal off-track signal used input may be read

− X01X output = 0

− X11X output = 1

− XX01 Q-to-W subcode output

− XX10 output = 0

− XX11 output = 1

− 10XX output = 0

− 11XX output = 1

DATA

FUNCTION

via decoder status bit; selected via register 2

selected via register 2

2000 Jun 26 21

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.13 Spindle motor control

7.13.1 MOTOR OUTPUT MODES

The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal ±8 frame FIFO and disc speed information are used to calculate the motor control output signals. Several output modes, selected by decoder register 6, are supported:

• Pulse density, 2-line (true complement output),

(1 × n) MHz sample frequency

• PWM output, 2-line, (22.05 × n) kHz modulation

frequency

• PWM output, 4-line, (22.05 × n) kHz modulation

frequency

• CDV motor mode.

MOTO1

22 kΩ

10 nF

+ –

SAA7324

7.13.1.1 Pulse density output mode

In the pulse density mode the motor output pin (MOTO1) is the pulsedensity modulated motor output signal. A 50% duty factor corresponds with the motor not actuated, higher duty factors mean acceleration, lower mean braking. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a (1 × n) MHz internal clock signal. Possible application diagrams are illustrated in Fig.14.

7.13.1.2 PWM output mode (2-line)

In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output. The motor braking signal is pulse-width modulated on the MOTO2 output. The timing is illustratedin Fig.15. Atypical application diagram is illustrated in Fig.16.

+ –

22 kΩ

10 nF

MOTO2

MOTO1

MOTO2

22 kΩ

10 nF

–

22 kΩ

Fig.14 Motor pulse density application diagrams.

t = 45 µs

rep

Accelerate Brake

t 240 ns

dead

MGA363 - 1

MGA366

Fig.15 2-line PWM mode timing.

2000 Jun 26 22

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

10 Ω

MOTO1 MOTO2

100 nF

SAA7324

MGA365 - 2

Fig.16 Motor 2-line PWM mode application diagram.

7.13.1.3 PWM output mode (4-line)

Using two extra outputs from the versatile pins interface, it is possible to use the SAA7324 with a 4-input motor bridge. The timing is illustrated in Fig.17. A typical application diagram is illustrated in Fig.18.

t = 45 µs t 240 ns

rep

MOTO1

MOTO2

Accelerate Brake

dead

t = 240 ns

ovl

MGA367 - 1

Fig.17 4-line PWM mode timing.

2000 Jun 26 23

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

10 Ω

MOTO1

100 nF

SAA7324

MOTO2

MGA364 - 2

Fig.18 Motor 4-line PWM mode application diagram.

7.13.1.4 CDV/CAV output mode

In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin [carrier frequency (300 × d) Hz],where ‘d’ is thedisc speed factor. The PLL frequency signal will be put in pulse-density modulated form (carrier frequency 4.23 × n MHz) on the MOTO2 pin. The integrated motor servo is disabled in this mode.

The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position (half full) will result in a PWM output of 60%.

Inthe lock-to-disc (CAV)mode the CDVmotor mode isthe only mode that can be used to control the motor.

7.13.2 SPINDLE MOTOR OPERATING MODES

The operating modes of the motor servo is controlled by decoder register 1 (see Table 11).

In the SAA7324 decoder there is an anti-windup mode for themotor servo, selected via decoderregister 1.Whenthe anti-windup mode is activated the motor servo integrator will hold if the motor output saturates.

7.13.2.1 Power limit

In start mode 1, start mode 2, stop mode 1 and stop mode 2, a fixed positive or negative voltage is applied to the motor. This voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop.

The following power limits are possible:

• 100% (no power limit), 75%, 50%, or 37% of maximum.

7.13.3 LOOP CHARACTERISTICS The gain and crossover frequencies of the motor control

loop can be programmed via decoder registers 4 and 5. The following parameter values are possible:

• Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32

• Crossover frequency f4: 0.5 × n Hz, 0.7 × n Hz,

1.4 × n Hz and 2.8 × nHz

• Crossover frequency f3: 0.85 × n Hz, 1.71 × n Hz and

3.42 × n Hz.

It should be noted that the crossover frequencies f3and f are scaled withthe overspeed factor ‘n’ whereas the gains are not.

2000 Jun 26 24

Page 25

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

7.13.4 FIFO OVERFLOW

If FIFO overflow occurs during Play mode (e.g.: asa result ofmotor rotational shock),the FIFO willbe automatically reset to 50% and the audio interpolator tries to conceal as much as possible to minimize the effect of data loss.

Table 11 Operating modes

MODE DESCRIPTION

Start mode 1 The disc is accelerated by applying a positive voltage to the spindle motor.No decisions are involved

and the PLL is reset. No disc speed information is available for the microcontroller.

Start mode 2 The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the

disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status signals selectable via register 2 are valid.

Jump mode Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is

possible to read the subcode. It should be noted that in the CD-ROM modes the data, on EBU and

S-bus is not muted.

the I

Jump mode 1 Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large

change in disc speed. Play mode FIFO released after resetting to 50%. Audio mute released. Stop mode 1 Disc is braked by applying a negative voltage to the motor. No decisions are involved. Stop mode 2 The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc

reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal

speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode. Off mode Motor not steered.

MGA362 - 2

fBW

Fig.19 Motor servo mode diagram.

2000 Jun 26 25

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.14 Servo part

7.14.1 DIODE SIGNAL PROCESSING The photo detector in conventional two-stage three-beam

Compact Disc systems normally contains six discrete diodes. Four of these diodes (three for single foucault systems) carry the Central Aperture signal (CA) while the other two diodes (satellite diodes) carry the radial tracking information. The CA signal is processed into an HF signal (for the decoder function) and LF signal (information for the focus servo loop) before it is supplied to the SAA7324.

The analog signals from the central and satellite diodes are converted into a digital representation using Analog-to-Digital Converters (ADCs).

Table 12 Shadow register settings to control diode input current ranges

SHADEN BIT

SHADOW

ADDRESS DATA FUNCTION INITIAL

1010 0000 (0.042).I

signal

magnitude

control for

diodes

D1 to D4

The ADCs aredesigned to convert unipolar currents into a digital code. The dynamic range of the input currents is adjustablewithin a givenrange, which isdependent on the value of the external reference current (I the values programmed in shadow registers A and C. The magnitude of the signal currents for the central aperturediodes D1 to D4 andthe radial diodes R1 and R2 are programmed separately to sixteen separate current ranges.

The maximum input currents with an external 30 kΩ reference current resistor are given in Table 12.

0001 (0.083).I 0010 (0.125).I 0011 (0.167).I 0100 (0.208).I 0101 (0.25).I 0110 (0.292).I 0111 (0.333).I 1000 (0.375).I 1001 (0.417).I 1010 (0.458).I 1011 (0.5).I 1100 (0.542).I 1101 (0.583).I 1110 (0.625).I 1111 (0.667).I

SAA7324

) resistor and

ref

= 1.006 µA (nominal) −

ref

= 2.013 µA (nominal) −

ref

= 3.019 µA (nominal) −

ref

= 4.025 µA (nominal) −

ref

= 5.031 µA (nominal) −

ref

= 6.034 µA (nominal) −

ref

= 7.044 µA (nominal) −

ref

= 8.05 µA (nominal) −

ref

= 9.056 µA (nominal) −

ref

= 10.063 µA (nominal) −

ref

= 11.069 µA (nominal) −

ref

= 12.075 µA (nominal) −

ref

= 13.081 µA (nominal) −

ref

= 14.088 µA (nominal) −

ref

= 15.094 µA (nominal) −

ref

= 16.1 µA (nominal) reset

ref

2000 Jun 26 26

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

SHADEN BIT

SHADOW

signal

magnitude

control for

diodes

R1 and R2

ADDRESS DATA FUNCTION INITIAL

1100 0000 (0.042).I

SAA7324

= 1.006 µA (nominal) −

ref

= 2.013 µA (nominal) −

ref

= 3.019 µA (nominal) −

ref

= 4.025 µA (nominal) −

ref

= 5.031 µA (nominal) −

ref

= 6.034 µA (nominal) −

ref

= 7.044 µA (nominal) −

ref

= 8.05 µA (nominal) −

ref

= 9.056 µA (nominal) −

ref

= 10.063 µA (nominal) −

ref

= 11.069 µA (nominal) −

ref

= 12.075 µA (nominal) −

ref

= 13.081 µA (nominal) −

ref

= 14.088 µA (nominal) −

ref

= 15.094 µA (nominal) −

ref

= 16.1 µA (nominal) reset

ref

7.14.2 SIGNAL CONDITIONING The digital codes retrieved from the ADCs are applied to

logic circuitry to obtain the various control signals. The signals from the central aperture diodes are processed to obtain a normalised focus error signal.

D1 D2–

--------------------D1 D2+

D3 D4–

–=

--------------------D3 D4+

where the detector set-up is assumed to be as shown in Fig.20.

In the eventof single Foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows:

D1 D2–

×=

--------------------D1 D2+

The error signal, FEn, is further processed by a Proportional Integral and Differential (PID) filter section.

A Focus OK (FOK) flag is generated by means of the central aperture signal and an adjustable reference level. This signal is used to provide extra protection for the Track-Loss (TL) generation, the focus start-up procedure and the dropout detection.

The radial or tracking error signal is generated by the satellite detector signals R1 and R2. The radial error signal can be formulated as follows:

REs= (R1 − R2) × re_gain + (R1 + R2) × re_offset where the index ‘s’ indicates the automatic scaling

operation which is performed on the radial error signal. This scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces the radial bandwidth spread. Furthermore, the radial error signal will be made free from offset during start-up of the disc.

The four signals from the central aperture detectors, together with the satellite detector signals generate a Track Position Signal (TPI) which can be formulated as follows:

TPI = sign [(D1 + D2 + D3 + D4) − (R1 + R2) × sum_gain] where the weighting factor sum_gain is generated

internally by the SAA7324 during initialization.

2000 Jun 26 27

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

handbook, full pagewidth

SATELLITE

DIODE R1

SATELLITE

DIODE R2

single Foucault astigmatic focus double Foucault

SATELLITE

DIODE R1

SATELLITE

DIODE R2

SATELLITE

DIODE R1

D1 D2 D3 D4

SATELLITE

DIODE R2

SAA7324

MBG422

Fig.20 Detector arrangement.

7.14.3 FOCUS SERVO SYSTEM

7.14.3.1 Focus start-up

Five initially loaded coefficients influence the start-up behaviour of the focus controller. The automatically generated triangular voltage can be influenced by 3 parameters; for height (ramp_height) and DC offset (ramp_offset) of the triangle and its steepness (ramp_incr).

For protection against false focus point detections two parameters are available which are an absolute level on the CA signal (CA_start) and a level on the FEnsignal (FE_start). When this CA level is reached the FOK signal becomes true.

If the FOK signal is true and the level on the FEnsignal is reached, the focus PID is enabled to switch-on when the next zero crossing is detected in the FEnsignal.

7.14.3.2 Focus position control loop

The focus control loop contains a digital PID controller which has 5 parameters that are available to the user. These coefficients influence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, partof foc_parm1) action of the PID and a digital low-pass filter (foc_pole_noise, part of foc_parm2) following the PID. The fifth coefficient foc_gain influences the loop gain.

7.14.3.3 Dropout detection

This detector can be influenced by one parameter (CA_drop). The FOK signal will become false and the integrator of the PID will hold if the CA signal drops below this programmable absolute CA level. When the FOK signal becomes false it is assumed, initially, to be caused by a black dot.

2000 Jun 26 28

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.14.3.4 Focus loss detection and fast restart

Whenever FOK is false for longer than approximately 3 ms, it is assumed that the focus point is lost. A fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300 ms depending on the programmed coefficients of the microcontroller.

7.14.3.5 Focus loop gain switching

The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. The integrator value of the PID is corrected accordingly. The differentiating (foc_pole_lead) action of the PID can be switched at the same time as the gain switching is performed.

7.14.3.6 Focus automatic gain control loop

The loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. Thisgain control injects asignalintothe loop which isused to correct the loop gain. Since this decreases theoptimum performance, the gain control should only be activated for a short time (for example, when starting a new disc).

7.14.4 RADIAL SERVO SYSTEM

7.14.4.1 Level initialization

During start-up an automatic adjustment procedure is activatedtosetthe values of the radial errorgain(re_gain), offset (re_offset) and satellite sum gain(sum_gain) for TPI level generation. The initialization procedure runs in a radial open loop situation and is ≤300 ms. This start-up time period may coincide with the last part of the motor start-up time period:

• Automatic gain adjustment: as a result of this initializationtheamplitude of the RE signalisadjustedto within ±10% around the nominal RE amplitude

• Offset adjustment: the additional offset in RE due to the limited accuracy of the start-up procedure is less than

±50 nm

• TPI level generation: the accuracy of the initialization

procedure is such that the duty factor range of TPI becomes 0.4 < duty factor < 0.6 (default duty factor = TPI HIGH/TPI period).

7.14.4.2 Sledge control

Themicrocontroller can move thesledge in both directions via the steer sledge command.

SAA7324

7.14.4.3 Tracking control

The actuator is controlled using a PID loop filter with user defined coefficients and gain. For stable operation between the tracks, the S-curve is extended over 0.75 of the track. On request from the microcontroller, S-curve extensionover2.25 tracksis used, automatically changing to access control when exceeding those 2.25 tracks.

Both modes of S-curve extension make use of a track-count mechanism. In this mode, track counting results in an ‘automatic return-to-zero track’, to avoid major music rhythm disturbances in the audio output for improved shock resistance. The sledge is continuously controlled, or provided with step pulses to reduce power consumption using the filtered value of the radial PID output. Alternatively, the microcontroller can read the average voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. Filter coefficients of the continuous sledge control can be preset by the user.

7.14.4.4 Access

The access procedure is divided into two different modes (see Table 13), depending on the requested jump size.

Table 13 Access modes

ACCESS

TYPE

Actuator jump 1 - brake_distance decreasing

Sledge jump brake_distance - 32768 maximum

Note

1. Microcontroller presettable.

The access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity set pointcalculated from the numberof tracks to goanda user programmable parameter indicating the maximum sledge performance.

If the number of tracks remaining is greater than the brake_distance then the sledge jump mode should be activated or, the actuator jump should be performed. The requestedjump size togetherwith the required sledge breaking distance at maximum access speed defines the brake_distance value.

JUMP SIZE

(1)

ACCESS

SPEED

velocity

power to sledge

(1)

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

During the actuator jump mode, velocity control with a PI controller is used for the actuator. The sledge is then continuouslycontrolled using the filtered valueoftheradial PID output. All filter parameters (for actuator and sledge) are user programmable.

In the sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction while the actuator becomes idle (the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated). The actuator can be electronically damped during sledge jump. The gainof the dampingloop is controlled via the hold_mult parameter.

The fast track jumping circuitry can be enabled/disabled via the xtra_preset parameter.

7.14.4.5 Radial automatic gain control loop

The loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. Thisgain control injects asignalintothe loop which isused to correct the loop gain. Since this decreases theoptimum performance, the gain control should only be activated for a short time (for example, when starting a new disc).

This gain control differs from the level initialization. The level initialization should be performed first. The disadvantage of using the level initialization without the gain control is that only tolerances from the front-end are reduced.

7.14.5 OFF-TRACK COUNTING

The Track Position Signal (TPI) is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of ±1⁄4of the track-pitch. In combination with the Radial Polarity flag (RP) the relative spot position over the tracks can be determined.

SAA7324

These signals are, however, afflicted with some uncertainties caused by:

• Disc defects such as scratches and fingerprints

• The HF information on the disc, which is considered as

noise by the detector signals.

In order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a Track Loss signal (TL) and an off-track counter value. These extra conditions influence the maximum speed and this implies that, internally, one of the following three counting states is selected:

1. Protectedstate: used in normalplaysituations. A good protection against false detection caused by disc defects is important in this state.

2. Slow counting state: used in low velocity track jump situations. In this state a fast response is important rather than the protection against disc defects (if the phase relationship between TL and RP of1⁄2π radians is affected too much, the direction cannot then be determined accurately).

3. Fast counting state: used in high velocity track jump situations. Highest obtainable velocity is the most important feature in this state.

7.14.6 DEFECT DETECTION

A defect detection circuit is incorporated into the SAA7324.If a defectis detected, theradial and focuserror signals may be zeroed, resulting in better playability. The defect detector can be switched off, applied only to focus control or applied to both focus and radial controls under software control (part of foc_parm1).

The defect detector (see Fig.21) has programmable set points selectable by the parameter defect_parm.

handbook, full pagewidth

sat1

sat2

−

DECIMATION

FILTER

FAST

FILTER

SLOW

FILTER

Fig.21 Block diagram of defect detector.

2000 Jun 26 30

DEFECT

GENERATION

PROGRAMMABLE

HOLD-OFF

defect output

MBG421

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.14.7 OFF-TRACK DETECTION During active radial tracking, off-track detection has been

realised by continuously monitoring the off-track counter value. The off-track flag becomes valid whenever the off-track counter value is not equal to zero. Depending on the type of extended S-curve, the off-track counter isreset after 0.75 extend or at the original track in the 2.25 track extend mode.

7.14.8 HIGH-LEVEL FEATURES

7.14.8.1 Interrupt mechanism and STATUS pin

The STATUS pin is an output which is active LOW, its output is selected by decoder register 7 to be either the decoder status bit (active LOW) selected by decoder register 2 (only available in 4-wire bus mode) or the interrupt signal generated by the servo part.

Eight signals from the interrupt status register are selectable from the servo part via the interrupt_mask parameter. The interrupt is reset by sending the read high-level status command. The 8 signals are as follows:

• Focus lost: dropout of longer than 3 ms

• Subcode ready

• Subcode absolute seconds changed

• Subcode discontinuity detected: new subcode time

before previous subcode time, or more than 10 frames later than previous subcode time

• Radial error: during radial on-track, no new subcode frame occurs within time defined by the ‘playwatchtime’ parameter; during radial jump, less than 4 tracks have been crossed during time defined by the ‘jumpwatchtime’ parameter

• Autosequencer state change

• Autosequencer error

• Subcode interface blocked: the internal decoder

interface is being used.

Itshouldbe noted that if theSTATUSpinoutputis selected via decoder register 2 and either themicrocontroller writes a different value to decoder register 2 or the decoder interface is enabled then the STATUS output will change.

7.14.8.2 Decoder interface

The decoder interface allows decoder registers 0 to F to be programmed and subcode Q-channel data to be read via servo commands. The interface is enabled/disabled by the preset latch command (and the xtra_preset parameter).

SAA7324

7.14.8.3 Automatic error handling

Three Watchdogs are present:

• Focus: detects focus dropout of longer than 3 ms, sets focus lost interrupt, switches off radial and sledge servos, disables drive to disc motor

• Radial play: started when radial servo is in on-track mode and a first subcode frame is found; detects when maximum time between two subcode frames exceeds the time set by playwatchtime parameter; then sets radial error interrupt, switches radial and sledge servos off, puts disc motor in jump mode

• Radial jump: active when radial servo is in long jump or short jump modes; detects when the off-track counter value decreases by less than 4 tracks between two readings (time interval set by jumpwatchtime parameter); then sets radial jump error, switches radial and sledge servos off to cancel jump.

The focus Watchdog is always active, the radial Watchdogs are selectable via the radcontrol parameter.

7.14.8.4 Automatic sequencers and timer interrupts

Twoautomatic sequencers areimplemented (and must be initialized after power-on):

• Autostart sequencer: controls the start-up of focus, radial and motor

• Autostop sequencer: brakes the disc and shuts down servos.

Whenthe automatic sequencersare not usedit is possible to generate timer interrupts, defined by the time_parameter coefficient.

7.14.8.5 High-level status

Theread high-level status commandcanbeused to obtain the interrupt, decoder, autosequencer status registers and the motor start time. Use of the read high-level status command clears the interrupt status register, and re-enables the subcode read via a servo command.

7.14.9 DRIVER INTERFACE

The control signals (pins RA, FO and SL) for the mechanism actuators are pulse density modulated. The modulating frequency can be set to either

1.0584 (DSD mode) or 2.1168 MHz; controlled via the

xtra_preset parameter. An analog representation of the output signals can be achieved by connecting a 1st-order low-pass filter to the outputs.

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

During reset (i.e. RESET pin is held LOW) the RA, FO and SL pins are high-impedance.

7.14.10 LASER INTERFACE The LDON pin (open-drain output) is used to switch the

laser off and on. When the laser is on, the output is high-impedance. The action of the LDON pin is controlled by the xtra_preset parameter; the pin is automatically driven if the focus control loop is active.

7.14.11 RADIAL SHOCK DETECTOR Theshock detector (see Fig.22)canbeswitched on during

normal track following, and detects within an adjustable frequency whether disturbances in the radial spot position relative to the track exceed an adjustable level (controlled by shock_level).

Every time the radial tracking error exceeds this level the radial control bandwidth is switched to twice its original bandwidth and the loop gain is increased by a factor of 4.

The shock detection level is adjustable in 16 steps from 0% to 100% of the traverse radial amplitude which is sent to an amplitude detection unit viaan adjustable band-pass filter(controlledbysledge_parm1); lower corner frequency can be set at either 0 or 20 Hz, and upper corner frequency at 750 or 1850 Hz. The shock detector is switched off automatically during jump mode.

SAA7324

7.15 Microcontroller interface

Communication on the microcontroller interface can be set-up in two different modes:

• 4-wire bus mode: protocol compatible with SAA7345 (CD6) and TDA1301 (DSIC2) where:

– SCL = serial clock – SDA = serial data – RAB = R/W control anddata strobe (active HIGH) for

writing to decoder registers 0 to F, reading status bit selected via decoder register 2 and reading Q-channel subcode

– SILD = R/W control and data strobe (active LOW) for

servo commands.

• I2C-bus mode: I2C-bus protocol where the SAA7324 behaves as slave device, activated by setting RAB = HIGH and SILD = LOW where:

– I2C-bus slave address (write mode) = 30H – I2C-bus slave address (read mode) = 31H – Maximum data transfer rate = 400 kbits/s.

It should be noted that only servo commands can be used therefore, writing to decoder registers 0 to F, reading decoder status and reading Q-channel subcode data must be performed by servo commands.

handbook, full pagewidth

HIGH-PASS FILTER

(0 or 20 Hz)

LOW-PASS FILTER

(750 or 1850 Hz)

Fig.22 Block diagram of radial shock detector.

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AMPLITUDE DETECTION

SHOCK

OUTPUT

MGC914

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

7.15.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MODE)

7.15.1.1 Writing data to registers 0 to F

The sixteen 4-bit programmable configuration registers, 0 to F (see Table 14), can be written to via the microcontroller interface using the protocol shown in Fig.23.

It should be noted that SILD must be held HIGH; A3 to A0 identifies the register number and D3 to D0 is the data. The data is latched into the register on the LOW-to-HIGH transition of RAB.

7.15.1.2 Writing repeated data to registers 0 to F

The same data can be repeated several times (e.g. for a fade function) by applying extra RAB pulses as shown in Fig.24. It should be noted that SCL must stay HIGH between RAB pulses.

7.15.1.3 Reading decoder status information on SDA

There are several internal status signals, selected via register 2, which can be made available on the SDA line:

SUBQREADY-I: LOW if new subcode word is ready in Q-channel register

MOTSTART1: HIGH if motor is turning at 75% or more of nominal speed

MOTSTART2: HIGH if motor is turning at 50% or more of nominal speed

MOTSTOP: HIGH if motor is turning at 12% or less of nominal speed; can be set to indicate 6% or less (instead of 12% or less) via register E

PLL lock: HIGH if sync coincidence signals are found V1: follows input on pin V1 V2: follows input on pin V2 MOTOR-OV: HIGH if the motor servo output stage

saturates FIFO-OV: HIGH if FIFO overflows SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV +

FIFO-OV + servo interrupt signal + OTD (HIGH if shock detected)

LA-SHOCK: latched SHOCK signal.

The status read protocol is shown in Fig.25. It should be noted that SILD must be held HIGH.

SAA7324

7.15.1.4 Reading Q-channel subcode

To read the Q-channel subcode direct in the 4-wire bus mode, the SUBQREADY-I signal should be selected as status signal. The subcode read protocol is illustrated in Fig.26.

It should be noted that SILD must be held HIGH; after subcode read starts, the microcontroller may take as long as it wants to terminate the read operation. When enough subcodehasbeenread(1 to 96 bits),terminate reading by pulling RAB LOW.

Alternatively, the Q-channel subcode can be read using a servo command as follows:

• Use the read high-level status command to monitor the subcode ready signal

• Sendthe read subcodecommand and read therequired number of bytes (up to 12)

• Send the read high-level status command; to re-enable the decoder interface.

7.15.1.5 Behaviour of the SUBQREADY-I signal

When the CRC of the Q-channel word is good, and no subcode is being read, the SUBQREADY-I status signal will react as shown in Fig.27. When the CRC is good and the subcode is being read, the timing in Fig.28 applies.

If t1(SUBQREADY-I status LOW to end of subcode read) is below 2.6/n ms, then t2= 13.1/n ms (i.e. the microcontroller can read all subcode framesif it completes the read operation within 2.6/n ms after the subcode is ready). If these criteria are not met, it is only possible to guarantee that t3 will be below 26.2/n ms (approximately).

If subcode frames with failed CRCs are present, the t2and t3 times will be increased by 13.1/n ms for each defective subcode frame.

It should be noted that in the lock-to-disc mode ‘n’ is replaced by ‘d’, which is the disc speed factor.

7.15.1.6 Write servo commands

A write data command is used to transfer data (a number of bytes) from the microcontroller, using the protocol shown in Fig.29. The first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte.

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

It should be noted that RAB must be held LOW; the command or data is interpreted by the SAA7324 after the HIGH-to-LOW transition of SILD; there must be a minimum time of 70 µs between SILD pulses.

7.15.1.7 Writing repeated data in servo commands

The same data byte can be repeated by applying extra SILD pulses as illustrated in Fig.30. SCL must be HIGH between the SILD pulses.

7.15.1.8 Read servo commands

A read data command is used to transfer data (status information) to the microcontroller, using the protocol shown in Fig.31. The first byte written determines the type ofcommand.After this byte avariablenumberof bytes can be read. It should be noted that RAB must be held LOW; after the end of the command byte (LOW-to-HIGH transition on SILD) there must be a delay of 70 µs before reading data is started (i.e. the next HIGH-to-LOW transitiononSILD); there must be aminimumtimeof 70 µs between SILD pulses.

7.15.2 M

ICROCONTROLLER INTERFACE (I

Bytes are transferred over the interface in groups (i.e. servo commands) of which there are two types: write data commands and read data commands.

The sequence for a write data command (that requires 3 data bytes) is as follows:

C-BUS MODE)

SAA7324

1. Send START condition

2. Send address 30H (write)

3. Write command byte

4. Write data byte 1

5. Write data byte 2

6. Write data byte 3

7. Send STOP condition.

It should be noted that more than one command can be sent in one write sequence.

Thesequence for aread data command(that reads 2 data bytes) is as follows:

1. Send START condition

2. Send address 30H (write)

3. Write command byte

4. Send STOP condition

5. Send START condition

6. Send address 31H (read)

7. Read data byte 1

8. Read data byte 2

9. Send STOP condition.

It should be noted that the timing constraints specified for the read and write servo commands must still be adhered to.

RAB

(microcontroller)

SCL

(microcontroller)

SDA

(microcontroller)

SDA

(SAA7324)

A3 A2 A1 A0 D3 D2 D1 D0

high-impedance

Fig.23 Microcontroller write protocol for registers 0 to F.

2000 Jun 26 34

MGS181

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

RAB

(microcontroller)

SCL

(microcontroller)

SDA

(microcontroller)

SDA

(SAA7324)

A3 A2 A1 A0 D3 D2 D1 D0

high-impedance

SAA7324

MGS182

RAB

(microcontroller)

SCL

(microcontroller)

SDA

(microcontroller)

SDA

(SAA7324)

Fig.24 Microcontroller write protocol for registers 0 to F (repeat mode).

high-impedance

STATUS

MGS183

Fig.25 Microcontroller read protocol for decoder status on SDA.

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

RAB

(microcontroller)

SCL

(microcontroller)

SDA

(SAA7324)

STATUS

CRC

Q1 Q2 Q3

Qn – 1

Qn – 2 Qn

SAA7324

MGS184

RAB

(microcontroller)

SCL

(microcontroller)

SDA

(SAA7324)

Fig.26 Microcontroller protocol for reading Q-channel subcode.

high-impedance

CRC OK CRC OK

10.8/n ms 15.4/n ms

READ start allowed

2.3/n ms

MGS185

Fig.27 SUBQREADY-I status timing when no subcode is read.

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

RAB

(microcontroller)

SCL

(microcontroller)

SDA

(SAA7324)

Q1 Q2 Q3 Qn

SAA7324

MGS186

handbook, full pagewidth

(microcontroller)

(SAA7324)

(microcontroller)

SILD

SCL

SDA

SILD

SDA

Fig.28 SUBQREADY-I status timing when subcode is read.

D7 D6 D5 D4 D3 D2 D1 D0

command or data byte

high-impedance

microcontroller write (one byte: command or data)

COMMAND DATA1 DATA2 DATA3

MGS187

microcontroller write (full command)

Fig.29 Microcontroller protocol for write servo commands.

2000 Jun 26 37

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

handbook, full pagewidth

SILD

(microcontroller)

SDA

(microcontroller)

COMMAND DATA1

microcontroller write (full command)

SAA7324

MBG413

handbook, full pagewidth

SILD

(microcontroller)

SCL

(microcontroller)

SDA (SAA7324)

SILD

(microcontroller)

SDA (SAA7324)

SDA

(microcontroller)

Fig.30 Microcontroller protocol for repeated data in write servo commands.

D7 D6 D5

COMMAND

D4 D3 D2

data byte

microcontroller read (one data byte)

DATA1 DATA2 DATA3

microcontroller read (full command)

D1 D0

MGS188

Fig.31 Microcontroller protocol for read servo commands.

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

7.15.3 DECODER REGISTERS AND SHADOW REGISTERS To maintain compatibility with the SAA737x series,

decoder registers 0 to F are identical to the SAA7370. However, to control the extra functionality of SAA7324, a new set of registers called shadow registers have been implemented.

These are accessed by using the LSB of decoder register F. This bit is called SHADEN (shadow registers enable) on SAA7324. When this bit is set to logic 1 (i.e. decoder register F set to XXX1), any subsequent addresses will be decoded by the shadow registers. In fact, only four addresses are implemented as shadow registers; 3, 7, A and C. Any other addresses sent while SHADEN = 1 are invalid and have no effect.

7.15.4 SUMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS 0 TO F

Table 14 Registers 0 to F

0 (fade and attenuation)

1 (motor mode)

0000 0000 mute reset

0010 attenuate − 0001 full-scale − 0100 step down − 0101 step up −

0001 X000 motor off mode reset

X 001 motor stop mode 1 −

X010 motor stop mode 2 − X011 motor start mode 1 − X100 motor start mode 2 − X101 motor jump mode − X111 motor play mode −

X110 motor jump mode 1 − 1XXX anti-windup active − 0XXX anti-windup off reset

When SHADEN is set to logic 0 (decoder register F set to XXX0) all subsequent addresses are decodedby the main decoder registers again.

Access to decoder register F is always enabled so that SHADEN can be set or reset as required.

The SHADEN bit and subsequent shadow registers are programmed identically to the main decoder registers, i.e. they can be directly programmed when using the SAA7324 in 4-wire mode or programmed via the servo interface when using 3-wire or I2C-bus modes.

The main decoder registers are given in Table 14. The functions implemented using shadow registers are given in Table 16.

(1)

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

2 (status control to servo part not the STATUS pin)

3 (DAC output)

4 (motor gain)

5 (motor bandwidth)

0010 0000 status = SUBQREADY-I reset

0001 status = MOTSTART1 − 0010 status = MOTSTART2 − 0011 status = MOTSTOP − 0100 status = PLL lock − 0101 status = V1 − 0110 status = V2 − 0111 status = MOTOR-OV − 1000 status = FIFO overﬂow − 1001 status = shock detect − 1010 status = latched shock detect − 1011 status = latched shock detect reset −

0011 1010 I

S-bus; CD-ROM mode − 1011 EIAJ; CD-ROM mode − 1100 I2S-bus; 18-bit; 4fsmode reset 1111 I 1110 I 0000 EIAJ; 16-bit; 4f 0011 EIAJ; 16-bit; 2f 0010 EIAJ; 16-bit; f 0100 EIAJ; 18-bit; 4f 0111 EIAJ; 18-bit; 2f 0110 EIAJ; 18-bit; f

S-bus; 18-bit; 2fsmode −

S-bus; 16-bit; fsmode −

s s

0100 X000 motor gain G = 3.2 reset

X001 motor gain G = 4.0 − X010 motor gain G = 6.4 − X011 motor gain G = 8.0 − X100 motor gain G = 12.8 − X101 motor gain G = 16.0 − X110 motor gain G = 25.6 −

X111 motor gain G = 32.0 − 0XXX disable comparator clock divider reset 1XXX enable comparator clock divider; only if SELLPLL

set HIGH

0101 XX00 motor f

XX01 motor f

XX10 motor f

XX11 motor f

00XX motor f

01XX motor f

10XX motor f

= 0.5 × n Hz reset

= 0.7 × nHz −

= 1.4 × nHz −

= 2.8 × nHz −

= 0.85 × n Hz reset

= 1.71 × nHz −

= 3.42 × nHz −

(1)

−

2000 Jun 26 40

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

6 (motor output conﬁguration)

7 (DAC output and status control)

8 (PLL loop ﬁlter bandwidth)

9 (PLL equalization)

A (EBU output)

B (speed control)

0110 XX00 motor power maximum 37% reset

XX01 motor power maximum 50% −

XX10 motor power maximum 75% −

XX11 motor power maximum 100% −

00XX MOTO1, MOTO2 pins 3-state reset

01XX motor PWM mode −

10XX motor PDM mode −

11XX motor CDV mode −

0111 XX00 interrupt signal from servo at STATUS pin reset

XX10 statusbit from decoder status register at STATUS

pin X0XX DAC data normal value reset X1XX DAC data inverted value − 0XXX left channel ﬁrst at DAC (WCLK normal) reset 1XXX right channel ﬁrst at DAC (WCLK inverted) −

see Table 15 −

1001 0011 PLL loop ﬁlter equalization reset

0001 PLL 30 ns over-equalization − 0010 PLL 15 ns over-equalization − 0100 PLL 15 ns under-equalization − 0101 PLL 30 ns under-equalization −

1010 XX0X EBU data before concealment −

XX1X EBU data after concealment and fade reset

X0X0 level II clock accuracy (<1000 ppm) reset X0X1 level I clock accuracy (<50 ppm) − X1X0 level III clock accuracy (>1000 ppm) −

X1X1 EBU off - output low − 0XXX ﬂags in EBU off reset 1XXX ﬂags in EBU on −

1011 X0XX 33.8688 MHz crystal present, or 8.4672 MHz (or

16.9344 MHz) crystal with SELPLL set HIGH X1XX 16.9344 MHz crystal present − 0XXX single-speed mode reset 1XXX double-speed mode −

XX00 standby 1: ‘CD-STOP’ mode reset XX10 standby 2: ‘CD-PAUSE’ mode − XX11 operating mode −

reset

(1)

−

2000 Jun 26 41

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

C (versatile pins interface)

D (versatile pins interface)

E 1110 00XX audio features disabled −

F (subcode interface and shadow register enable)

1100 XXX1 external off-track signal input at V1 −

XXX0 internal off-tracksignal used (V1 may be read via

status)

XX0X kill-L at KILL output, kill-R at V3 output −

001X V3 = 0; single KILL output reset 011X V3 = 1; single KILL output −

1101 0000 4-line motor (using V4 and V5) −

XX01 Q-to-W subcode at V4 − XX10 V4 = 0 − XX11 V4 = 1 reset 01XX de-emphasis signal at V5, no internal

de-emphasis ﬁlter 10XX V5 = 0 − 11XX V5 = 1 reset

01XX audio features enabled reset

XX0X lock-to-disc mode disabled reset XX1X lock-to-disc mode enabled − XXX0 motor brakes to 12% reset XXX1 motor brakes to 6% −

1111 X0XX subcode interface off reset

X1XX subcode interface on − 0XXX 4-wire subcode reset 1XXX 3-wire subcode − XXX0 SHADEN = 0; shadow registers not enabled;

addresses will be decoded by main decoder

registers

XXX1 SHADEN = 1; shadow registers enabled; all

subsequent addresses will be decoded by

shadow registers, not decoder registers

reset

(1)

−

Note

1. The initial column shows the Power-on reset state.

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

Table 15 Loop ﬁlter bandwidth

8 (PLL loop ﬁlter bandwidth)

1000 0000 1640 × n 525 × n 8400 × n −

1110 6560 × n 1050 × n 33600 × n −

0001 3279 × n 263 × n 16800 × n − 0010 6560 × n 131 × n 33600 × n − 0100 1640 × n 1050 × n 8400 × n − 0101 3279 × n 525 × n 16800 × n − 0110 6560 × n 263 × n 33600 × n − 1000 1640 × n 2101 × n 8400 × n − 1001 3279 × n 1050 × n 16800 × n reset 1010 6560 × n 525 × n 33600 × n − 1100 1640 × n 4200 × n 8400 × n − 1101 3279 × n 2101 × n 16800 × n −

BANDWIDTH

(HZ)

FUNCTION INTERNAL

BANDWIDTH

(HZ)

LOW-PASS

BANDWIDTH

(HZ)

SAA7324

INITIAL

(1)LOOP

Note

1. The initial column shows the Power-on reset state.

7.15.5 SUMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS

Table 16 Shadow register settings

SHADEN BIT

SHADOW

control of versatile and clock pins

ADDRESS DATA FUNCTION INITIAL

0011 XXX0 select CL4 on CL11/4 output reset

XXX1 select CL11 on CL11/4 output − XX0X enable CL11/4 output pin reset XX1X set CL11/4 output pin to

X0XX enable CL16 output pin reset X1XX set CL16 output pin to

0XXX V2/V3 pin conﬁgured as

1XXX V2/V3 pin conﬁgured as

−

high-impedance

−

high-impedance

reset

V2 input

−

V3 output (open-drain)

2000 Jun 26 43

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

SHADEN BIT

SHADOW

control of onboard DAC

7 servo reference pin = 7, V

RIN

A signal magnitude control for diodes D1 to D4

ADDRESS DATA FUNCTION INITIAL

0111 XXX0 hold onboard DAC outputs at

XXX1 enable onboard DAC outputs − XX0X use external DAC or route audio

XX1X route audio data into onboard

X1XX use internal reference for servo

X0XX use external reference for servo

1010 0000 (0.042).I

0001 (0.083).I 0010 (0.125).I 0011 (0.167).I 0100 (0.208).I 0101 (0.25).I 0110 (0.292).I 0111 (0.333).I 1000 (0.375).I 1001 (0.417).I

1010 (0.458).I

1011 (0.5).I 1100 (0.542).I

1101 (0.583).I

1110 (0.625).I

1111 (0.667).I

zero

data into onboard DAC (loopback mode)

DAC (non-loopback mode)

reference voltage

= 1.006 µA (nominal) −

ref

= 2.013 µA (nominal) −

ref

= 3.019 µA (nominal) −

ref

= 4.025 µA (nominal) −

ref

= 5.031 µA (nominal) −

ref

= 6.034 µA (nominal) −

ref

= 7.044 µA (nominal) −

ref

= 8.05 µA (nominal) −

ref

= 9.056 µA (nominal) −

ref

= 10.063 µA

ref

(nominal)

= 11.069 µA

ref

(nominal)

= 12.075 µA (nominal) −

ref

= 13.081 µA

ref

(nominal)

= 14.088 µA

ref

(nominal)

= 15.094 µA

ref

(nominal)

= 16.1 µA (nominal) reset

ref

SAA7324

reset

−

reset

−

2000 Jun 26 44

Page 45

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

SHADEN BIT

SHADOW

signal magnitude control for diodes R1 and R2

ADDRESS DATA FUNCTION INITIAL

1100 0000 (0.042).I

0001 (0.083).I 0010 (0.125).I 0011 (0.167).I 0100 (0.208).I 0101 (0.25).I 0110 (0.292).I 0111 (0.333).I 1000 (0.375).I 1001 (0.417).I

1010 (0.458).I

1011 (0.5).I 1100 (0.542).I

1101 (0.583).I

1110 (0.625).I

1111 (0.667).I

ref

(nominal)

ref

(nominal)

SAA7324

= 1.006 µA (nominal) −

ref

= 2.013 µA (nominal) −

ref

= 3.019 µA (nominal) −

ref

= 4.025 µA (nominal) −

ref

= 5.031 µA (nominal) −

ref

= 6.034 µA (nominal) −

= 7.044 µA (nominal) −

ref

= 8.05 µA (nominal) −

ref

= 9.056 µA (nominal) −

ref

= 10.063 µA

ref

= 11.069 µA

ref

= 12.075 µA (nominal) −

= 13.081 µA

ref

= 14.088 µA

ref

= 15.094 µA

ref

= 16.1 µA (nominal) reset

ref

−

2000 Jun 26 45

Page 46

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

7.15.6 SUMMARY OF SERVO COMMANDS A list of the servo commands are given in Table 17. These are fully compatible with the SAA7370.

Table 17 SAA7324 servo commands

COMMANDS CODE BYTES PARAMETERS

Write commands

Write_focus_coefs1 17H 7 <foc_parm3> <foc_int> <ramp_incr> <ramp_height>

<ramp_offset> <FE_start> <foc_gain>

Write_focus_coefs2 27H 7 <defect_parm> <rad_parm_jump> <vel_parm2>

<vel_parm1> <foc_parm1> <foc_parm2> <CA_drop> Write_focus_command 33H 3 <foc_mask> <foc_stat> <shock_level> Focus_gain_up 42H 2 <foc_gain> <foc_parm1> Focus_gain_down 62H 2 <foc_gain> <foc_parm1> Write_radial coefs 57H 7 <rad_length_lead> <rad_int> <rad_parm_play>

<rad_pole_noise> <rad_gain> <sledge_parm2>

<sledge_parm_1> Preset_Latch 81H 1 <chip_init> Radial_off C1H 1 ‘1CH’ Radial_init C1H 1 ‘3CH’ Short_jump C3H 3 <tracks_hi> <tracks_lo> <rad_stat> Long_jump C5H 5 <brake_dist> <sledge_U_max> <tracks_hi> <tracks_lo>

<rad_stat> Steer_sledge B1H 1 <sledge_level> Preset_init 93H 3 <re_offset> <re_gain> <sum_gain> Write_decoder_reg Write_parameter A2H 2 <param_ram_addr> <param_data>

Read commands

Read_Q_subcode Read_status 70H up to 5 <foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi>

Read_hilevel_status Read_aux_status F0H up to 3 <re_offset> <re_gain> <sum_gain>

(1)

(1)(2)

(3)

D1H 1 <decoder_reg_data>

0H up to 12 <Q_sub1 to 10> <peak_l> <peak_r>

<tracks_lo>

E0H up to 4 <intreq> <dec_stat> <seq_stat> <motor_start_time>

Notes

1. These commands only available when internal decoder interface is enabled.

2. <peak_l> and <peak_r> bytes are clocked out LSB first.

3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled.

2000 Jun 26 46

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Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

7.15.7 SUMMARY OF SERVO COMMAND PARAMETERS

Table 18 Servo command parameters

PARAMETER

foc_parm_1 − focus PID − end of focus lead

foc_parm_2 − focus PID − focus low-pass

foc_parm_3 − focus PID − focus lead length

foc_int 14H focus PID − focus integrator crossover frequency foc_gain 15H focus PID 70H focus PID loop gain CA_drop 12H focus PID − sensitivity of dropout detector ramp_offset 16H focus ramp − asymmetry of focus ramp ramp_height 18H focus ramp − peak-to-peak value of ramp voltage ramp_incr − focus ramp − slope of ramp voltage FE_start 19H focus ramp − minimum value of focus error rad_parm_play 28H radial PID − end of radial lead rad_pole_noise 29H radial PID − radial low-pass rad_length_lead 1CH radial PID − length of radial lead rad_int 1EH radial PID − radial integrator crossover frequency rad_gain 2AH radial PID 70H radial loop gain rad_parm_jump 27H radial jump − ﬁlter during jump vel_parm1 1FH radial jump − PI controller crossover frequencies vel_parm2 32H radial jump − jump pre-deﬁned proﬁle speed_threshold 48H radial jump − maximum speed in fastrad mode hold_mult 49H radial jump 00H electronic damping

brake_dist_max 21H radial jump − maximum sledge distance allowed in fast

sledge_long_brake 58H radial jump FFH brake distance of sledge sledge_Umax − sledge − voltage on sledge during long jump sledge_level − sledge − voltage on sledge when steered sledge_parm_1 36H sledge − sledge integrator crossover frequency sledge_parm_2 17H sledge − sledge low-pass frequencies

sledge_pulse1 46H pulsed sledge − pulse width sledge_pulse2 64H pulsed sledge − pulse height defect_parm − defect detector − defect detector setting shock_level − shock detector − shock detector operation playwatchtime 54H Watchdog − radial on-track Watchdog time

RAM

ADDRESS

AFFECTS POR VALUE DETERMINES

defect detector enabling

focus error normalising

minimum light level

sledge bandwidth during jump

actuator steered mode

sledge gain sledge operation mode

2000 Jun 26 47

Page 48

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

PARAMETER

jumpwatchtime 57H Watchdog − radial jump Watchdog time-out radcontrol 59H Watchdog − enable/disable automatic radial off feature chip_init − set-up − enable/disable decoder interface xtra_preset 4AH set-up 38H laser on/off

cd6cmd 4DH decoder

interrupt_mask 53H STATUS pin − enabled interrupts seq_control 42H autosequencer − autosequencer control focus_start_time 5EH autosequencer − focus start time motor_start_time1 5FH autosequencer − motor start 1 time motor_start_time2 60H autosequencer − motor start 2 time radial_init_time 61H autosequencer − radial initialization time brake_time 62H autosequencer − brake time RadCmdByte 63H autosequencer − radial command byte osc_inc 68H focus/radial

phase_shift 67H focus/radial

level1 69H focus/radial

level2 6AH focus/radial

agc_gain 6CH focus/radial

RAM

ADDRESS

AFFECTS POR VALUE DETERMINES

RA, FO and SL PDM modulating frequency fast jumping circuit on/off

− decoder part commands

interface

− AGC control

AGC

− frequency of injected signal

− phase shift of injected signal

− amplitude of signal injected

− focus/radial gain

2000 Jun 26 48

Page 49

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

I(max)

DD(diff)

I(d)

amb

stg

Notes

1. All V

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

supply voltage note 1 −0.5 +3.6 V maximum input voltage

any input −0.5 V

pins RESET, SDA, SCL, RAB and SILD −0.5 +5.5 V output voltage (any output) −0.5 +3.6 V difference between V

DDA

, V

DDD

and V

pos

−±0.25 V output current (continuous) −±20 mA DC input diode current (continuous) −±20 mA electrostatic handling note 2 −2000 +2000 V

note 3 −200 +200 V ambient temperature −10 +70 °C storage temperature −55 +125 °C

(and V

) connections and VSS(and V

pos

) connections must be made externally to the same power supply.

neg

+ 0.5 V

9 CHARACTERISTICS

VDD= 3.0 to 3.6 V; VSS=0V; T

= −10 to +70 °C; unless otherwise speciﬁed.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

Bitstream DAC output (V

IFFERENTIAL OUTPUTS: PINS LN, LP, RN AND RP

supply voltage 3.0 3.3 3.6 V supply current VDD= 3.3 V; n = 1 mode − 20 − mA

= 3.3 V; n = 2 mode − 25 − mA

= 3.3 V; n = 4 mode − 30 − mA

DDD

= 3.3 V, V

= 3.3 V; VSS=0V, V

pos

neg

=0V; T

amb

=25°C)

S/N signal-to-noise ratio note 1 −85 −90 − dB (THD + N)/S total harmonic distortion

at 0 dB; note 1 −−83 −80 dB

plus noise-to-signal ratio

Servo and decoder analog functions (V

EFERENCE GENERATOR: PIN I

Iref

ref

Iref

reference voltage level 1.14 1.2 1.26 V input reference current − 40 −µA external resistor ±2% − 30 − kΩ

REF

DDA

= 3.3 V; V

SSA

=0V; T

amb

=25°C)

2000 Jun 26 49

Page 50

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Decoder analog front-end (V

OMPARATOR INPUTS: PINS HFIN AND HFREF

C f

clk

th(sw)

i(HFIN)

Servo analog part (V

INS D1 TO D4; R1 AND R2

D(max)

clock frequency note 2 8 − 70 MHz switching voltage threshold − 0.5V input voltage level pin HFIN − 1.0 − V

= 3.3 V; V

DDA

maximum input current for central diode input signal

R(max)

maximum input current for satellite diode input signal

RIN

internally generated reference voltage

externally generated reference voltage applied to V

RIN

(THD + N)/S total harmonic distortion

plus noise-to-signal ratio

S/N signal-to-noise ratio − 55 − dB PSRR power supply ripple

rejection at V

G ∆G

tol

gain tolerance note 7 −20 0 +20 % variation of gain between

channels

channel separation − 60 − dB

Digital inputs

DDA2

DDA

= 3.3 V; V

=0V; T

SSA

=0V; T

=25°C; R

amb

=25°C)

=30kΩ)

Iref

− V

note 3 1.006 − 16.1 µA

note 4 − 0.75 − V

note 4 0.5 − 0.5VDD+ 0.1 V

at 0 dB; note 5 −−50 −45 dB

note 6 − 45 − dB

−−2%

PINS RESET 5 V TOLERANT (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS) V

thr(sw)

switching voltage threshold

−−0.8V

rising

thf(sw)

switching voltage threshold

0.2V

DDD

falling

hys

i(pu)

resL

hysteresis voltage 0.4 −− V input pull-up resistance Vi=0V, V

= 3.3 V − 50 − kΩ

DDD

input capacitance −−10 pF reset pulse width

RESET only 1 −− µs

(active LOW)

PIN V1 (CMOS INPUT WITH PULL-UP RESISTOR) V

thr(sw)

switching voltage threshold

−−0.8V

rising

thf(sw)

switching voltage threshold

0.2V

DDD

falling

2000 Jun 26 50

DDD

−− V

DDD

−− V

Page 51

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

hys

i(pu)

PIN SELPLL (CMOS INPUT WITH PULL-UP RESISTOR) V

i(pu)

PINS TEST1, TEST2 AND TEST3 (CMOS INPUTS WITH PULL-DOWN RESISTORS) V

i(pd)

PINS RCK, WCLI, SDI AND SCLI (CMOS INPUTS) V

PINS SCL, SILD AND RAB (5 V TOLERANT CMOS INPUTS)

Digital outputs

hysteresis voltage − 0.3V input pull-up resistor Vi=0V; V

= 3.3 V − 50 − kΩ

DDD

− V

input capacitance −−10 pF

LOW-level input voltage −0.3 − 0.3V HIGH-level input voltage 0.7V input pull-up resistance Vi=0V; V

= 3.3 V − 50 − kΩ

DDD

− V

DDD

+ 0.3 V

input capacitance −−10 pF

LOW-level input voltage −0.3 − 0.3V HIGH-level input voltage 0.7V input pull-down resistance Vi=V

= 3.3 V − 50 − kΩ

DDD

− V

DDD

+ 0.3 V

input capacitance −−10 pF

LOW-level input voltage −0.3 − 0.3V HIGH-level input voltage 0.7V input leakage current Vi= 0 to V

DDD

−5 − +5 µA

DDD

− V

DDD

+ 0.3 V

input capacitance −−10 pF

LOW-level input voltage −0.3 − 0.2V HIGH-level input voltage 0.8V input leakage current Vi= 0 to V

DDD

−5 − +5 µA

DDD

− 5.5 V

DDD

input capacitance −−10 pF

PINS V4 AND V5 V

V C t

OL OH

o(r)

o(f)

LOW-level output voltage IOL=4mA 0 − 0.4 V HIGH-level output voltage IOH= −4mA V load capacitance −−100 pF output rise time CL= 20 pF;

0.4 to (V

DDD

− 0.4) V

output fall time CL= 20 pF;

− 0.4) to 0.4 V

DDD

Open-drain outputs

PINS CFLG, STATUS, KILL AND LDON (OPEN-DRAIN OUTPUT) V

o(f)

LOW-level output voltage IOL=1mA 0 − 0.4 V LOW-level output current −−2mA load capacitance −−50 pF output fall time CL= 50 pF;

− 0.4) to 0.4 V

DDD

2000 Jun 26 51

− 0.4 − V

DDD

−−10 ns

−−30 ns

Page 52

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

3-state outputs

PINS EF, SCLK, WCLK, DATA, CL16, RA, FO, SL, SBSY, SFSY, SUB AND CL11/4

o(r)

o(f)

(WHEN CL11/4 IS CONFIGURED AS CL11 OUTPUT) t

PINS MOTO1, MOTO2AND DOBM

o(r)

o(f)

Digital input/output

PIN SDA (5 V TOLERANT CMOS INPUT/OPEN-DRAIN I

o(f)

PIN V2/V3 (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS/OPEN-DRAIN OUTPUT)

thr(sw)

thf(sw)

hys

LOW-level output voltage IOL=1mA 0 − 0.4 V HIGH-level output voltage IOH= −1mA V

− 0.4 − V

DDD

V load capacitance −−35 pF output rise time CL= 20 pF;

0.4 to (V

DDD

output fall time CL= 20 pF;

− 0.4) to 0.4 V

DDD

output 3-state leakage

Vi= 0 to V

− 0.4) V

−−15 ns

−5 − +5 µA

current

output HIGH time (relative

Vo=1.5V 455055%

to clock period)

LOW-level output voltage IOL=4mA 0 − 0.4 V HIGH-level output voltage IOH= −4mA V

− 0.4 − V

DDD

V load capacitance −−100 pF output rise time CL= 20 pF;

0.4 to (V

DDD

output fall time CL= 20 pF;

− 0.4) to 0.4 V

DDD

output 3-state leakage

Vi= 0 to V

− 0.4) V

DDD

−−10 ns

−5 − +5 µA

current

C-BUS OUTPUT)

LOW-level input voltage −0.3 − +0.2V HIGH-level input voltage 0.8V 3-state leakage current Vi= 0 to V

DDD

−5 − +5 µA

DDD

− 5.5 V

DDD

input capacitance −−10 pF LOW-level output voltage IOL=2mA 0 − 0.4 V LOW-level output current −−6mA load capacitance −−50 pF output fall time CL= 20 pF;

0.85V

DDD

switching voltage threshold

to 0.4 V

−−15 ns

−−0.8V

DDD

V rising

switching voltage threshold

0.2V

DDD

−− V

falling hysteresis voltage − 0.3V

DDD

− V

2000 Jun 26 52

Page 53

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I(pu)

o(f)

Crystal oscillator

INPUT: PIN CRIN (EXTERNAL CLOCK) V

OUTPUT: PIN CROUT; SEE FIGS 3 AND 4 f

xtal

Notes

1. Assumes use of external components as shown in the application diagram (Figs 38 or 39).

2. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode.

3. Themaximum input currentdepends on the valueof the externalresistor connected to I registers A and C:

a) With R b) With R

4. V

RIN

5. Measuring bandwidth: 200 Hz to 20 kHz, f

6. f

ripple

7. Gain of the ADC is defined as G a) Digital output = the number of pulses at the digital output in counts/s and Ii= the DC input current in µA. b) The maximum input current depends on R c) The gain tolerance is the deviation from the calculated gain.

input pull-up resistance Vi=0V; V

= 3.3 V − 50 − kΩ

DDD

input capacitance −−10 pF LOW-level output voltage IOL=1mA 0 − 0.4 V LOW-level output current −−1mA load capacitance −−25 pF output fall time CL= 20 pF;

− 0.4) to 0.4 V

DDD

LOW-level input voltage −0.3 − +0.2V HIGH-level input voltage 0.8V

−−15 ns

− VDD+ 0.3 V input leakage current −10 − +10 µA input capacitance −−10 pF

crystal frequency ±100 ppm 8 8.4672 35 MHz mutual conductance at

17 −− mA/V

start-up feedback capacitance −−2pF output capacitance −−7pF

andthe settings ofshadow

ref

=30kΩ, minimum I

Iref

=30kΩ, maximum I

Iref

= (0.025). I

max

= (0.4). I

max

⇒ (0.025) × (40 µA) = 1 µA.

ref

⇒ (0.4) × (40 µA)=16µA.

ref

can be set to an internal source or an externally applied reference voltage using shadow register 7.

= 1 kHz.

i(ADC)

= 1 kHz, V

= 0.5 V (p-p).

ripple

ADC=fsys/Imax

(counts/µA); thus digital output = Ii× G

and on shadow registers A and C.

Iref

ADC

where:

2000 Jun 26 53

Page 54

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)

VDD= 3.0 to 3.6 V; VSS=0V; T

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Subcode interface timing (single speed × n); see Fig.32; note 1

NPUT: PIN RCK

CLKH

CLKL

d(SFSY-RCK)

input clock HIGH time 2/n 4/n 6/n µs input clock LOW time 2/n 4/n 6/n µs input clock rise time −−80/n ns input clock fall time −−80/n ns

delay time SFSY to RCK 10/n − 20/n µs OUTPUTS: PINS SBSY, SFSY AND SUB (CL=20PF) T

cy(block)

W(SBSY)

cy(frame)

W(SFSY)

SFSYH

SFSYL

d(SFSY-SUB)

d(RCK-SUB)

h(RCK-SUB)

block cycle time 12.0/n 13.3/n 14.7/n ms

SBSY pulse width −−300/n µs

frame cycle time 122/n 136/n 150/n µs

SFSY pulse width (3-wire mode only) −−366/n µs

SFSY HIGH time −−66/n µs

SFSY LOW time −−84/n µs

delay time SFSY to SUB (P data) valid −−1/n µs

delay time RCK falling to SUB −−0µs

hold time RCK to SUB −−0.7/n µs

= −10 to +70 °C; unless otherwise speciﬁed.

amb

Note

1. The subcode timingis directly relatedto the overspeed factor ‘n’ innormal operating mode.‘n’ is replaced by the disc speed factor ‘d’, in lock-to-disc mode.

2000 Jun 26 54

Page 55

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

0.8 V

W(SBSY)

W(SFSY)

cy(frame)

handbook, full pagewidth

SBSY

SFSY (4-wire mode)

SFSY (3-wire mode)

SFSY

SFSYL

SFSYH

cy(block)

SAA7324

RCK

SUB

d(SFSY−RCK)

d(SFSY−SUB)

h(RCK−SUB)

– 0.8 V

d(RCK−SUB)

Fig.32 Subcode interface timing diagram.

0.8 V

– 0.8 V

MGL718

2000 Jun 26 55

Page 56

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

11 OPERATING CHARACTERISTICS (I2S-BUS TIMING)

VDD= 3.0 to 3.6 V; VSS=0V; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

S-bus timing (single-speed × n); see Fig.33; note 1

CLOCK OUTPUT: PIN SCLK (CL=20PF) T

output clock period sample rate = f

clock HIGH time sample rate = f

clock LOW time sample rate = f

OUTPUTS: PINS WCLK, DATA AND EF (CL=20PF) t

set-up time sample rate = f

hold time sample rate = f

= −10 to +70 °C; unless otherwise speciﬁed.

amb

sample rate = 2f sample rate = 4f

s s

− 472.4/n − ns

− 236.2/n − ns

− 118.1/n − ns

166/n −−ns 83/n −−ns 42/n −−ns 166/n −−ns 83/n −−ns 42/n −−ns

95/n −−ns 48/n −−ns 24/n −−ns 95/n −−ns 48/n −−ns 24/n −−ns

Note

1. The I

S-bus timing is directly related to the overspeed factor ‘n’ in the normal operating mode. In the lock-to-disc

mode ‘n’ is replaced by the disc speed factor ‘d’.

SCLK

WCLK

DATA

clock period T

V – 0.8 V

0.8 V

Fig.33 I2S-bus timing diagram.

V – 0.8 V

0.8 V

MBG407

2000 Jun 26 56

Page 57

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)

VDD= 3.0 to 3.6 V; VSS=0V; T

SYMBOL PARAMETER CONDITIONS

Microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to F; reading Q-channel subcode and decoder status); see Figs 34 and 35; note 1

NPUTS SCL AND RAB

I t

EAD MODE (C

R t

dRD

input LOW time 480/n + 20 − 2400/n + 20 − ns input HIGH time 480/n + 20 − 2400/n + 20 − ns rise time − 480/n − 480/n ns fall time − 480/n − 480/n ns

=20PF)

delay time RAB to SDA valid

propagation delay SCL to SDA

dRZ

delay time RAB to SDA

high-impedance WRITE MODE (CL=20PF) t

suD

suCR

dWZ

set-up time SDA to SCL note 2 20 − 720/n − 20 − 720/n − ns

hold time SCL to SDA − 960/n + 20 − 4800/n + 20 ns

set-up time SCL to RAB 240/n + 20 − 1200/n + 20 − ns

delay time SDA

high-impedance to RAB Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 36 and 37; note 3

= −10 to +70 °C; unless otherwise speciﬁed.

amb

NORMAL MODE LOCK-TO-DISC MODE

MIN. MAX. MIN. MAX.

− 50 − 50 ns

720/n − 20 960/n + 20 720/n + 20 4800/n + 20 ns

− 50 − 50 ns

0 − 0 − ns

UNIT

INPUTS SCL AND SILD t

input LOW time 710 − 710 − ns

input HIGH time 710 − 710 − ns

rise time − 240 − 240 ns

fall time − 240 − 240 ns READ MODE (CL=20PF) t

dLD

delay time SILD to SDA

− 25 − 25 ns

valid t

propagation delay SCL to

− 950 − 950 ns

SDA t

dLZ

delay time SILD to SDA

− 50 − 50 ns

high-impedance t

sCLR

hCLR

set-up time SCL to SILD 480 − 480 − ns

hold time SILD to SCL 830 − 830 − ns

2000 Jun 26 57

Page 58

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

SYMBOL PARAMETER CONDITIONS

WRITE MODE (CL=20PF) t

sCL

hCL

dPLP

set-up time SDA to SCL 0 − 0 − ns

hold time SCL to SDA 950 − 950 − ns

set-up time SCL to SILD 480 − 480 − ns

hold time SILD to SCL 120 − 120 − ns

delay between two SILD

pulses t

dWZ

delay time SDA

high-impedance to SILD

Notes

1. The 4-wire bus mode microcontroller interface timing for writing to decoder registers 0 to F, and reading Q-channel subcode and decoder status, is a function of the overspeed factor ‘n’. In the lock-to-disc mode the maximum data rate is lower.

2. Negative set-up time means that the data may change after clock transition.

3. If a 16.9344 MHz crystal is used and SELPLL = 0 then the timings are divided-by-2 until the microcontroller has written X1XX to register B.

NORMAL MODE LOCK-TO-DISC MODE

UNIT

MIN. MAX. MIN. MAX.

70 − 70 −µs

0 − 0 − ns

RAB

SCL

SDA (SAA7324)

high-impedance

dRD

VDD − 0.8 V

0.8 V

VDD − 0.8 V

0.8 V

VDD − 0.8 V

0.8 V

dRZ

MGS189

Fig.34 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information).

2000 Jun 26 58

Page 59

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

handbook, full pagewidth

RAB

V – 0.8 V

0.8 V

SCL

SDA

(microcontroller)

suD

suCR

V – 0.8 V

0.8 V t

dWZ

high-impedance

SAA7324

V – 0.8 V

0.8 V

MBG405

handbook, full pagewidth

Fig.35 4-wire bus microcontroller timing; write mode (decoder registers 0 to F).

− 0.8 V

SILD

SCL

SDA

(SAA7324)

0.8 V

sCLR

0.8 V

dLD

hCLR

− 0.8 V

dLZ

MGS190

Fig.36 4-wire bus microcontroller timing; read mode (servo commands).

2000 Jun 26 59

Page 60

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

handbook, full pagewidth

SILD

SCL

SDA

(microcontroller)

– 0.8 V

0.8 V

- 0.8 V

0.8 V

sCL

dWZ

hCL

SAA7324

dPLP

– 0.8 V

MBG416

Fig.37 4-wire bus microcontroller timing; write mode (servo commands).

2000 Jun 26 60

Page 61

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2000 Jun 26 61

LDON

1 nF

DDA

2.2 Ω

10 kΩ 10 kΩ

220 pF

MECHANISM

AND

AMPLIFIER

(TDA1300)

(4)

RFE

(1) For crystal oscillator see Figs 3 and 4. (2) 1.5 nF capacitors connected between

pinsLN and LP, andRN and RPmust be placed as near to the pins as possible. Thisalso applies tothe 220 nF and47 µF capacitors connected between pins V and V

. Power supplies and V

pos

reference inputs (1⁄2V operational amplifiers must be low noise.

DDD

) for DAC

neg

DDD

(3) For single speed applications, use 47 pF

capacitors, for double speed use 22 pF capacitors.

(4) The connections to TDA1300 are shown

for single Foucault mechanisms.

220 pF

22 nF

1 kΩ

100 nF

33 µF

220 pF

33 pF

220 pF

(1)

1/2 V

MOTOR

INTERFACE

47 pF 22 kΩ

100 nF

30 kΩ

100 nF

220 pF

33 pF

(2)

DDD

(3)

2.2 Ω

LDONV1V5V4MOTO2

64 63 62 61 60 59 58 57 56 55

HFREF

HFIN

ISLICE

SSA1

DDA1

ref

RIN

SSA2

CROUT

CRIN

17 18 19 20

neg

100 nF

33 µF

220

DDA2

2.2 Ω

DDA

kΩ

10 kΩ

220

1.5

(2)

22kΩ11

left output

47 µF

kΩ

220

33 µF 33 µF

21 22 23 24 25 26 27 28 29

pos

DDD

100 nF

MOTO1

22kΩ22

kΩ

10 kΩ

1.5 nF

right output

ook, full pagewidth

to power

DDD

amplifiers

SSD3VDDD2(C)

SLFORA

SAA7324

TEST1

SELPLL

kΩ

2.2 Ω

100

54 53 52 51

CL16

DATA

220

11 kΩ

CFLG

WCLK

1/2 V

to DOBM

transformer

DDD

DDD1(P)

SCLK

DDD

SSD2

DOBM

30 31 32

TEST2

(2)

to external

DAC or ESA

CL11/4

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

KILL

MGS191

SBSY SFSY SUB RCK TEST3 STATUS SILD RAB SCL SDA RESET SCLI SDI WCLI V2/V3

SSD1

to CD graphics

4.7 kΩ

100 nF

4.7 kΩ

to ESA

serial data

loopback

DDD

to microcontroller interface

13 APPLICATION INFORMATION

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

decoder with integrated DAC (CD10 II)

SAA7324

Fig.38 Typical application diagram (for current mechanisms).

Page 62

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2000 Jun 26 62

PWRON

RFFB

TZA1024

(4)

(5)

RFEQO CMFB

V I

VCOM

OEIC

(4)

DIN

(4)

ΣD1-D4

D1 D2 D3 D4

S1 S2

LP FILTER

(1) For crystal oscillator see Figs 3 and 4. (2) 1.5 nF capacitors connected between pins

LN and LP, and RN and RP must be placed as near to the pins as possible. This also applies to the 220 nF and 47 µF capacitors connected between pins V

reference inputs (1⁄2V

DDD

operational amplifiers must be low noise.

neg

and V

. Power supplies and

pos

) for DAC

DDD

(3) For single speed applications, use 47 pF

capacitors,fordouble speed use 22 pF capacitors.

(4) For connections between OEIC and TZA1024,

refer to TZA1024 device specification.

(5) Components for LP filter and V → I conversion

depend on the OEIC and the current range set on SAA7324.

(5)

10 kΩ

DDA

2.2 Ω

1 kΩ

220 pF

100 nF

3 nF

100 nF

33 µF

220 pF

33 pF

INTERFACE

220 pF

(1)

1/2 V

MOTOR

47 pF

22 kΩ

100 nF

30 kΩ

33 pF

DDD

HFREF

(3)

HFIN

ISLICE

SSA1

DDA1

ref

RIN

D1 D2 D3 D4 R1 R2

SSA2

CROUT

CRIN

100 nF

33 µF

220

(2)

ok, full pagewidth

DDD

2.2 Ω

100 nF

LDONV1V5

64 63 62 61 60 59 58 57 56 55

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

17 18 19 20

DDA2

2.2 Ω

DDA

kΩ

10 kΩ

neg

220

1.5

(2)

kΩ

220

33 µF 33 µF

left output

SSD3VDDD2(C)

MOTO2

MOTO1

SAA7324

21 22 23 24 25 26 27 28 29

pos

1.5 nF

µF

DDD

22kΩ22

kΩ

10 kΩ

right output

SELPLL

to power

amplifiers

SLFORA

TEST1

kΩ

100

54 53 52 51

CL16

DATA

220

11 kΩ

2.2 Ω

CFLG

WCLK

1/2 V

to DOBM

transformer

DDD

DDD1(P)

SCLK

DDD

SSD2

DOBM

30 31 32 EF

TEST2

(2)

to external

DAC or ESA

CL11/4 49

KILL

MGS192

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

SBSY SFSY SUB RCK TEST3 STATUS SILD RAB SCL SDA RESET SCLI SDI WCLI V2/V3

SSD1

to CD graphics

4.7 kΩ

100 nF

4.7 kΩ

to ESA

serial data

loopback

DDD

to microcontroller interface

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

decoder with integrated DAC (CD10 II)

SAA7324

Fig.39 Typical application diagram (for voltage mechanisms).

Page 63

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

14 PACKAGE OUTLINE

QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm

48 33

SAA7324

SOT393-1

w M

pin 1 index

w M

0.25

0.45

0.23

0.30

0.13

DIMENSIONS (mm are the original dimensions)

max.

3.00

0.25

0.10

2.75

2.55

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0 5 10 mm

(1)

(1) (1)(1)

14.1

13.9

v M

scale

17.45

0.8

16.95

v M

17.45

16.95

1.03

0.73

detail X

0.16 0.100.161.60

1.2

0.8

(A )

Zywv θ

1.2

0.8

o o

OUTLINE VERSION

SOT393-1 134E07 MS-022

IEC JEDEC EIAJ

REFERENCES

2000 Jun 26 63

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27 00-01-19

Page 64

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

15 SOLDERING

15.1 Introduction to soldering surface mount packages

Thistextgives a very briefinsighttoa complex technology. A more in-depth account of soldering ICs can be found in our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011). There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering isnot always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.

15.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied tothe printed-circuit board byscreen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating,soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.

15.3 Wave soldering

Conventional single wave soldering is not recommended forsurfacemount devices (SMDs) or printed-circuitboards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

SAA7324

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• Forpackageswith leads on four sides,thefootprintmust be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

15.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

If wave soldering is used the following conditions must be observed for optimal results:

2000 Jun 26 64

Page 65

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

15.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

PACKAGE

BGA, SQFP not suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e)equal toor larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4) (5)

SOLDERING METHOD

(1)

suitable

suitable suitable

2000 Jun 26 65

Page 66

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc

SAA7324

decoder with integrated DAC (CD10 II)

16 DATA SHEET STATUS

DATA SHEET STATUS

Objective speciﬁcation Development This data sheet contains the design target or goal speciﬁcations for

Preliminary speciﬁcation Qualiﬁcation This data sheet contains preliminary data, and supplementary data will be

Product speciﬁcation Production This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

17 DEFINITIONS Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device atthese or at any otherconditionsabove those given inthe Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make norepresentationorwarranty that such applications will be suitable for the specified use without further testing or modification.

PRODUCT

STATUS

DEFINITIONS

product development. Speciﬁcation may change in any manner without notice.

published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

18 DISCLAIMERS Life support applications  These products are not

designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result inpersonal injury. Philips Semiconductorscustomersusingor selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes  Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for theuseof any of these products,conveysnolicence or title under any patent, copyright, or mask work right to these products,and makes no representationsorwarranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

(1)

19 PURCHASE OF PHILIPS I

Purchase of Philips I components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

2000 Jun 26 66

C COMPONENTS

C components conveys a license under the Philips’ I2C patent to use the

Page 67

Philips Semiconductors Product speciﬁcation

Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)

NOTES

SAA7324

2000 Jun 26 67

Page 68

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2000

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Printed in The Netherlands 753503/02/pp68 Date of release: 2000 Jun 26 Document order number: 9397 750 06991