Datasheet saa5284 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA5284

Multimedia video data acquisition
circuit

Objective specification
Supersedes data of 1997 Mar 03
File under Integrated Circuits, IC22

1998 Feb 05

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 MAIN FUNCTIONAL BLOCKS
6 BLOCK DIAGRAM
7 PINNING INFORMATION

7.1 Pinning

7.2 Pin description
8 FUNCTIONAL DESCRIPTION

8.1 Power supply strategy

8.2 Clocking strategy

8.3 Power-on reset

8.4 Analog switch

8.5 Analog video-to-data byte converter

8.6 Packet filtering

8.7 Packet buffer

8.8 FIFO

8.9 Host interface

8.10 Interrupt support

8.11 DMA support

8.12 I2C-bus interface
9 LIMITING VALUES
10 QUALITY & RELIABILITY
11 CHARACTERISTICS
12 TIMING
13 APPLICATION INFORMATION

13.1 Hardware application circuit for ISA card

13.2 Hardware application circuit for PCI application

13.3 Software application information
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction

15.2 Reflow soldering

15.3 Wave soldering

15.4 Repairing soldered joints
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
18 PURCHASE OF PHILIPS I2C COMPONENTS

1998 Feb 05 2

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

1 FEATURES

• High performance multi-standard data slicer

• Intercast (Intel Corporation) compatible

• Teletext (WST, Chinese teletext) (625 lines)

• Teletext (US teletext, NABTS and MOJI) (525 lines)

• Wide Screen Signalling (WSS), Video Programming

Signal (VPS)

• Closed Caption (Europe, US)

• Data broadcast, PDC (packet 30 and 31)

• User programmable data format (programmable framing

code)

• 2 kbytes data cache on-chip to avoid data loss and
reduce host CPU overhead

• Filtering of packets 30 and 31 WST/NABTS

• Choice of clock frequencies, direct-in clock or crystal

oscillator

• Parallel interface, Motorola, Intel and digital video bus

2

C-bus control

• I

• Data transport by digital video bus

• Choice of programmable interrupt, DMA or polling

driven

• Data type selectable video line by video line, with
Vertical Blanking Interval and Full Field mode

• Single IC with few external components and small
footprint QFP44 package

• Optimized for EMC.

2 GENERAL DESCRIPTION

The SAA5284 is a Vertical Blanking Interval (VBI) and Full
Field (FF) video data acquisition device tailored for
application on PC add-in cards, PC mother-boards, set-top
boxes and as a SAA5250 replacement. The IC in
combination with a range of software modules will acquire
most existing formats of broadcast VBI and FF data.

These associated software modules are available under
licence. Scope is provided for acquiring some as yet
unspecified formats. The SAA5284 incorporates all the
data slicing, parallel interface, data filtering and control
logic. It is controlled either by a parallel interface or

2

C-bus. It can output ASCII VBI data as pixels on the

I
digital video bus where no parallel port is available. It is
available in a QFP44 package.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD

V

sync(p-p)

V

i(CVBS)(p-p)

supply voltage 4.5 5.0 5.5 V
supply current − 72 95 mA
sync voltage (peak-to-peak value) 0.1 0.3 0.6 V
input voltage on pin CVBS0 and CVBS1

0.7 1.0 1.4 V

(peak-to-peak value)
f
T

xtal

amb

crystal frequency; see note 1 − 12.0 − MHz

operating ambient temperature −20 − +70 °C

Note

1. Selectable: 12, 13.5, 15 or 16 MHz.

4 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA5284GP QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm);

SOT205-1

body 14 × 14 × 2.2 mm

1998 Feb 05 3

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

5 MAIN FUNCTIONAL BLOCKS

1. Input clamp and sync separator

2. Analog-to-digital converter

3. Multi-standard data slicer and clock regenerator

4. Packet filtering; (8 and 4) Hamming correction

5. On-chip data cache

6. Line selectable data type

6 BLOCK DIAGRAM

handbook, full pagewidth

CVBS0
CVBS1

V

DDAVSSAVDDXVDDDVSSD3

15
14

17 6

16

41 40 1

SAA5284

ANALOG

SWITCH

RESET

PACKET BUFFER AND

FRONT END CONTROL

REGISTERS

7. 12, 13.5, 15 and 16 MHz clock or oscillator options

8. FIFO access to data

9. Interrupt and DMA support

10. Multi-standard parallel interface

11. I

12. Power-on reset.
Figure 1 shows a block diagram of the SAA5284.

VPOIN0 HREF

VPOIN1

2

C-bus interface

LLC

LLC2

WR

(1)

DMACK

RD

(1)

DMARQ

33 34424323938 36 37

MULTI-STANDARD
HOST INTERFACE

(1)

30 to 28
20 to 27

35

CS0

44

CS1

31

INT

32
10
11

5

8

3

(1)

RDY
SEL0
SEL1
DENB
A2 to A0
D7 to D0

(1)

(1)

13

I

REF

BLACK

(1) Multi-functional pins, see Chapter 7.

12

ANALOG

VIDEO TO

DATA BYTE

CONVERTER

(DATA

DEMODULATOR)

OSCILLATOR

AND TIMING

789 18 19

OSCOUT OSCGND

OSCIN

PACKET

FILTERING (e.g.

WST packets

30/31)

PACKET BUFFER RAM

2 kbyte

(45 packets)

V

SSD1

V

SSD2

Fig.1 Block diagram.

1998 Feb 05 4

FIFO

I2C-BUS

INTERFACE

400 kHz

SLAVE

data path
control

3

4

SDA

SCL

MGG740

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

7 PINNING INFORMATION

7.1 Pinning

handbook, full pagewidth

RESET

HREF

SDA

SCL
DENB
V

DDX

OSCOUT

OSCIN

OSCGND

SEL0
SEL1

(1)

DDD

LLC

CS1

LLC2

44

43

42

1
2
3
4

5
6
7

8

9

10
11

12

13

14

REF

I

CVBS1

BLACK

SSD3

V

V

41

40

SAA5284

15

16

DDA

V

CVBS0

VPOIN0

VPOIN1
39

38

17

18

SSA

SSD1

V

V

DMACK
37

19

SSD2

V

DMARQ

CS0

36

35

21

20

(1)

(1)

D7

D6

(1)

RD
34

(1)

33

WR

(1)

RDY

32
31

INT

(1)

30

A2

(1)

A1

29

(1)

28

A0

(1)

D0

27

(1)

D1

26

(1)

D2

25

(1)

24

D3

(1)

D4

23

22

(1)

D5

MGG739

(1) Multi-functional pin.

Fig.2 Pin configuration.

7.2 Pin description Table 1 QFP44 package

The IC has a total of 44 pins; many of these are multi-functional due to the multiple host block modes of operation.

SYMBOL PIN I/O DESCRIPTION

RESET 1 I reset IC
HREF 2 I video horizontal reference signal (digital video mode only)

2

SDA 3 I/O serial data port for I

C-bus, open-drain
SCL 4 I serial clock input for I2C-bus
DENB 5 O data enable bar (for external buffers)
V

DDX

6 − +5 V supply
OSCOUT 7 O oscillator output
OSCIN 8 I oscillator input

1998 Feb 05 5

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

SYMBOL PIN I/O DESCRIPTION

OSCGND 9 − oscillator ground
SEL0 10 I parallel interface format select 0
SEL1 11 I parallel interface format select 1
BLACK 12 I/O video black level storage; connected to V
I

REF

13 I reference current input; connected to V
CVBS1 14 I analog composite video input 1
CVBS0 15 I analog composite video input 0
V
V
V
V
D7
D6
D5
D4
D3
D2
D1
D0
A0
A1
A2

DDA
SSA
SSD1
SSD2

(1)
(1)
(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)

16 − analog +5 V supply
17 − analog ground supply
18 I digital ground supply 1
19 I digital ground supply 2
20 I/O data bus 7/video data output 7
21 I/O data bus 6/video data output 6
22 I/O data bus 5/video data output 5
23 I/O data bus 4/video data output 4
24 I/O data bus 3/video data output 3
25 I/O data bus 2/video data output 2
26 I/O data bus 1/video data output 1
27 I/O data bus 0/video data output 0
28 I address input 0/video data input 7
29 I address input 1/video data input 6
30 I address input 2/video data input 5

INT 31 O interrupt request

(1)

RDY
WR
RD

(1)

(1)

32 O ready/DTACK (data acknowledge)/VBI, open-drain
33 I Intel bus Write/Motorola bus R/W/video data input 4

34 I Intel bus Read/Motorola bus LDS/video data input 3
CS0 35 I chip select 0; active LOW
DMARQ 36 O DMA request
DMACK

(1)

37 I DMA acknowledge/video data input 2
VPOIN0 38 I video data input 0
VPOIN1 39 I video data input 1
V
V

SSD3
DDD

40 − digital ground supply 3

41 − digital +5 V supply
LLC 42 I full rate digital video clock input
LLC2 43 I half rate digital video clock input
CS1 44 I chip select 1; active LOW

via 100 nF capacitor

SSA

via 27 kΩ resistor

SSA

Note

1. These pins have two functions, depending on the interface mode.

1998 Feb 05 6

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

8 FUNCTIONAL DESCRIPTION

8.1 Power supply strategy

There are three separate +5 V (V

1. V

supplies the critical noise-sensitive analog

DDA

) connections to the IC:

DD

front-end sections: ADC and sync separator, to reduce
interference from the rest of the front-end

2. V

supplies all sections which take standing DC

DDX

current

3. V

supplies the rest of the logic.

DDD

8.2 Clocking strategy

The master frequency reference for the IC is a
12, 13.5, 15 or 16 MHz crystal oscillator. The tolerance on

−6

the clock frequency is 500 × 10

(1.5 kHz). Further

specifications of the crystal are given in Table 2.
If preferred, an external 12, 13.5, 15 or 16 MHz (±1.5 kHz)

frequency source may be connected to OSCIN instead of
the crystal.

8.3 Power-on reset

The RESET pin should be held HIGH for a minimum of two
clock cycles. The reset signal is passed through a Schmitt
trigger internally.

Direct addressed registers (i.e. those addressed using the
A0 to A2 pins) are set to 00H after power-up. All other
register bits are assumed to be in random states after
power-up.

The analog video-to-data byte converter is specifically
designed to overcome the most commonly found types of
distortion of a broadcast video signal. It is also fully
multi-standard. The data type to be demodulated is
programmable on a line-by-line basis using 4 register bits
per line for lines 2 to 23 (PAL numbering),
fields 1 and 2, and 4 further bits for all lines combined.

8.6 Packet filtering

If using a slow (e.g. 80C51) microcontroller, it is necessary
to reduce the amount of data acquired by SAA5284 before
downloading to the microcontroller to avoid it being
swamped by unwanted data. Packet filtering is available
for this purpose. A common use of this would be to acquire
only packet 8/30 in 625-line WST. The packet filter
includes optional (8, 4) Hamming correction.

8.7 Packet buffer

This is a 2 kbyte RAM which acts as a buffer for storing
received packets. The first 44 bytes are reserved for
control information. The rest of the RAM is divided into
44-byte rows (or packets), each holding the data received
on one incoming CVBS line. In the case of a WST packet
received, the data stored consists of a Magazine and
Row-Address Group (2 bytes), followed by the 40 bytes of
packet data. When data in other formats than WST is
received, this is stored in the packet buffer in the same
way. In each case, the data is preceded by two information
bytes which record on which line and field the packet was
received, and what the data type is.

8.4 Analog switch

Register bit selection between two video sources.

8.8 FIFO

FIFO hardware is provided to manage the ‘read’ address
for the host processor, i.e. data is read repeatedly from the

8.5 Analog video-to-data byte converter

This section comprises a line and field sync separator, a
video clamp, an ADC and a custom adaptive digital filter
with DPLL based timing circuit.

same 8-bit port, and appears byte-serially in the order of
reception. The read address can be reset to the start of the
packet buffer (the first 44-byte packet), back to the start of
the current packet, or incremented to the start of the next
packet.

Table 2 Crystal characteristics

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

C1 series capacitance − 18.5 − fF
C2 parallel capacitance − 4.9 − pF

R

r

X

a

X

j

X

d

resonant resistance −−50 Ω
ageing −−5×10

−6

adjustment tolerance −−25 × 10−6−
drift −−25 × 10−6−

per year

1998 Feb 05 7

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

8.9 Host interface

The SAA5284 has a multi-standard 8-bit I/O interface.
To reduce the amount of host I/O space used, the parallel
interface has only 3 address inputs (A0, A1 and A2).
An extended addressing (pointer) scheme and the data
FIFO are used to allow access to the full set of SAA5284
registers and the full span of the packet buffer.

As well as the 8 data I/O lines and 3 address lines, there
are the following control signals: RD (read LOW), WR
(write LOW), CS0 (chip select LOW), CS1(second chip
select LOW), INT (interrupt request), DMARQ (DMA
request), DMACK (DMA acknowledge) and RDY (ready).

In order to maintain compatibility with Motorola and Intel

8.10 Interrupt support

The host interface provides comprehensive support for
interrupt generation. The interrupt may be programmed to
occur when a particular number of packets of VBI data are
available in the cache RAM. The interrupts can be further
controlled to occur on a specific line in the TV frame.
The interrupts can also be self masking if required.

8.11 DMA support

Burst and demand mode DMA are supported. In burst
mode, the number of packets to transfer can be defined.
An interrupt can be generated when DMA is finished. This
can be self masking.

type buses, two control signals SEL0 and SEL1 are
provided to configure the host interface. These signals
allow configuration of the host interface to work with the
Motorola or Intel style interfaces.

The host interface has a digital video mode. Digital video
mode may be used to allow the SAA5284 to pass decoded
VBI data into a system using the digital video bus.

8.12 I

The I2C-bus interface functions as a slave receiver or
transmitter at up to 400 kHz. The I2C-bus address is
selectable as 20H or 22H. All functionality is available
using the I2C-bus although with a slower data transfer
speed. It is possible to use the I2C-bus in all modes.

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

2

C-bus interface

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

I(max)

V

O(max)

∆V

DDD−DDA−DDX

I

IOK

I

O(max)

T

stg

T

amb

supply voltage (all supplies) −0.3 +6.5 V
input voltage (any input) −0.3 VDD+ 0.5 V
output voltage (any output) −0.3 VDD+ 0.5 V
supply voltage difference between V

DDD

, V

DDA

and V

DDX

− 0.25 V
DC input or output diode current − 20 mA
output current (any output) − 10 mA
storage temperature −55 +125 °C
operating ambient temperature −20 +70 °C

10 QUALITY & RELIABILITY

In accordance with

“SNW-FQ-611-E”

.

1998 Feb 05 8

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

11 CHARACTERISTICS

T

= −20 to +70 °C; VDD= 4.5 to 5.5 V; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

Power supply

V

DDn

I

DD(tot)

I

DDD

I

DDA

supply voltage 4.5 5.0 5.5 V
total supply current − 72 95 mA
digital supply current − 32 42 mA
analog supply current − 40 53 mA

Inputs CVBS0 and CVBS1

V

sync(p-p)

sync voltage

0.1 0.3 0.6 V

(peak-to-peak value)

V

burst(p-p)

colour burst voltage

0 0.3 0.4 V

(peak-to-peak value)

V

i(vid)(p-p)

video input voltage

0.7 1.0 1.4 V

(peak-to-peak value)

V

i(data)(p-p)

teletext data input voltage

0.29 0.46 0.71 V

(peak-to-peak value)

Z

source

V

i(sw)

source impedance −−250 Ω
input switching level of sync

1.5 1.8 2.1 V

separator

Z

i

C

i

Input I

R

IREF

Inputs RESET, HREF, SEL0, SEL1, A0, A1, A2, WR, RD,

V

IL

V

IH

I

LI

C

i

input impedance 2.5 5.0 − kΩ
input capacitance −−10 pF

REF

external resistor to V

SSA

− 27 − kΩ

CS0, CS1, DMACK, VPOIN1, VPOIN0, LLC and LLC2

LOW-level input voltage −0.3 − +0.8 V
HIGH-level input voltage 2.0 − VDD+ 0.5 V
input leakage current Vi= 0 to V

DD

−10 − +10 µA

input capacitance −−10 pF

Input SCL

V

IL

V

IH

I

LI

C

i

t

i(r)

t

i(f)

f

i(SCL)

C

L

LOW-level input voltage −0.5 − +1.5 V
HIGH-level input voltage 3.0 − VDD+ 0.5 V
input leakage current Vi= 0 to V

DD

−10 − +10 µA
input capacitance − 10 pF
input rise time V

V

input fall time V

V

IL(min)
IL(min)
IL(max)
IL(max)

to V
to V

to V
to V

IH(max)
IH(max)

IH(min)
IH(min)

; f
; f
; f
; f

= 100 kHz 50 − 1000 ns

i(SCL)

= 400 kHz 50 − 300 ns

i(SCL)

= 100 kHz 50 − 300 ns

i(SCL)

= 400 kHz 50 − 300 ns

i(SCL)

input clock frequency 0 − 400 kHz
load capacitance −−400 pF

UNIT

1998 Feb 05 9

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

Input/output SDA (open-drain)

V
V
I
C
t

t

V

t
C

IL
IH

LI

i

i(r)

i(f)

OL

o(f)

L

LOW-level input voltage −0.5 − +1.5 V
HIGH-level input voltage 3.0 − VDD+ 0.5 V
input leakage current VI=0toV

DD

−10 − +10 µA
input capacitance − 10 pF
input rise time V

V

input fall time V

V

IL(min)
IL(min)
IL(max
IL(max)

to V
to V

)toV

to V

IH(max)
IH(max)

IH(min)
IH(min)

; f
; f

; f

; f

= 100 kHz 50 − 1000 ns

i(SCL)

= 400 kHz 50 − 300 ns

i(SCL)

= 100 kHz 50 − 300 ns

i(SCL)

= 400 kHz 50 − 300 ns

i(SCL)

LOW-level output voltage IOL= 3 mA 0 − 0.4 V

I

= 6 mA 0 − 0.6 V

OL

output fall time between 3 and 1.5 V; IOL=3mA 50 − 250 ns
load capacitance −−400 pF

Input/output BLACK

C

BLACK

storage capacitance to V

SSA

− 100 − nF

Inputs/outputs D7 to D0

V
V
I
C
V
V
C
t
t

IL
IH

LI

i
OL
OH

L

o(r)
o(f)

LOW-level input voltage −0.3 − +0.8 V
HIGH-level input voltage 2.0 − VDD+ 0.5 V
input leakage current VIN= 0 to V

DD

−10 − +10 µA
input capacitance −−10 pF
LOW-level output voltage IOL= +1.6 mA 0 − 0.4 V
HIGH-level output voltage IOH= −0.2 mA 2.4 − V

DD

load capacitance −−tbf pF
output rise time into C
output fall time into C

L

L

0.6 to 2.2 V −−tbf ns

2.2 to 0.6 V −−tbf ns

Outputs INT, DENB and DMARQ

V
V
C
t
t

OL
OH

L
o(r)
o(f)

LOW-level output voltage IOL= +1.6 mA 0 − 0.4 V
HIGH-level output voltage IOH= −0.2 mA 2.4 − V

DD

load capacitance −−tbf pF
output rise time into C
output fall time into C

L

L

0.6 to 2.2 V −−tbf ns

2.2 to 0.6 V −−tbf ns
RDY (open-drain); note 1
V

C
t
t

OL

L
o(r)
o(f)

LOW-level output voltage IOL= +1.6 mA 0 − 0.4 V
load capacitance −−tbf pF
output rise time into C
output fall time into C

L

L

0.6 to 2.2 V −−tbf ns

2.2 to 0.6 V −−tbf ns

UNIT

V

V

1998 Feb 05 10

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

UNIT

I2C-bus timings (see note 2 and Fig.8)

f

i(SCL)

t

LOW

t

HIGH

t

SU;DAT

t

HD;DAT

t

SU;STO

t

BUF

t

HD;STA

t

SU;STA

t

r

t

f

SCL input clock frequency f

SCL LOW time f

SCL HIGH time f

data set-up time f

data hold time f

set-up time STOP condition f

bus free time f

hold time START condition f

set-up time repeated START f

rise time (SDA and SCL) f

fall time (SDA and SCL) f

= 100 kHz 0 − 100 kHz

i(SCL)

f

= 400 kHz 0 − 400 kHz

i(SCL)

= 100 kHz 4.7 −− µs

i(SCL)

f

= 400 kHz 1.3 −− µs

i(SCL)

= 100 kHz 4.0 −− µs

i(SCL)

f

= 400 kHz 0.6 −− µs

i(SCL)

= 100 kHz 250 −− ns

i(SCL)

f

= 400 kHz 100 −− ns

i(SCL)

= 100 kHz 0 −− µs

i(SCL)

f

= 400 kHz 0 −− µs

i(SCL)

= 100 kHz 4.7 −− µs

i(SCL)

f

= 400 kHz 0.6 −− µs

i(SCL)

= 100 kHz 4.7 −− µs

i(SCL)

f

= 400 kHz 1.3 −− µs

i(SCL)

= 100 kHz 4.0 −− µs

i(SCL)

f

= 400 kHz 0.6 −− µs

i(SCL)

= 100 kHz 4.7 −− µs

i(SCL)

f

= 400 kHz 0.6 −− µs

i(SCL)

= 100 kHz −−1000 ns

i(SCL)

f

= 400 kHz −−300 ns

i(SCL)

= 100 kHz −−300 ns

i(SCL)

= 400 kHz −−300 ns

f

i(SCL)

Notes

1. ESD protection of this pin falls below the Philips General Quality Specification (GQS). Therefore it is recommended
that a diode is connected from pin RDY to V

DDD

.

2. The I2C-bus interface pins SDA and SCL may pull the data and clock lines below 3 V while the digital power supply
V

is in the range 0.4 to 0.8 V.

DDD

1998 Feb 05 11

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

12 TIMING

handbook, full pagewidth

A2 to A0

t

1

D7 to D0

CS0 or CS1

RD

RDY

(1)

A

(1) Event A occurs when RD + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when RD + CS0 + CS1 = 1 (boolean).

Fig.3 Intel mode interface read cycle timing.

valid address

t

3

t

5

t

0

t

2

valid data

t

4

t

6

(2)

B

3-state3-state

t

7

MGK145

Table 3 Intel-mode interface read cycle timing (12 MHz clock)

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

0

t

1

t

2

t

3

t

4

t

5

t

6

t

7

minimum cycle time 333 833 ns
address set-up time before event A 0 − ns
address hold time after event B 0 − ns
data settling time 88 712 ns
data hold time after event B 0 − ns
time from event A until RDY goes LOW 83 170 ns
RDY LOW time 83 530 ns
event B to next event A time 83 − ns

1998 Feb 05 12

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

handbook, full pagewidth

A2 to A0

t

1

D7 to D0

t

3

CS0 or CS1

WR

RDY

(1) Event A occurs when WR + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when WR + CS0 + CS1 = 1 (boolean).

Fig.4 Intel mode interface write cycle timing.

(1)

A

valid address

t

5

valid data

t

6

t

0

t

2

t

4

t

7

(2)

B

MGK146

Table 4 Intel-mode interface write cycle timing (12 MHz clock)

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

0

t

1

t

2

t

3

t

4

t

5

t

6

t

7

minimum cycle time 333 833 ns
address set-up time 0 − ns
address hold time 0 − ns
data set-up time, note 1 0 − ns
data hold time 0 − ns
RDY set-up time 83 170 ns
RDY LOW time 83 530 ns
event B to next event A time 83 − ns

Note

1. Legacy AT bus PCs may not satisfy this requirement as they are not ISA compatible. An application fix is available

“SAA5284 Users Guide”

in the

.

1998 Feb 05 13

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

handbook, full pagewidth

DMARQ

t

1

DMACK

CS

(same signal

as DMACK)

(1)

RD

D7 to D0

(1) Read data pipelined, so no RD LOW to data valid set-up time.

t

4

t

5

valid data valid data

t

3

t

6

t

7

t

2

MGK147

Fig.5 Intel mode interface DMA cycle timing.

Table 5 Intel-mode interface DMA cycle timing (12 MHz clock)

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

1

t

2

t

3

t

4

t

5

t

6

t

7

DMARQ to DMACK 0 − ns
RD LOW to DMARQ LOW 0 212 ns
cycle time 252 − ns
DMACK to RD active − 0ns
data set-up time 0 90

(1)

data hold time 83 − ns
data hold from DMACK HIGH 0 83 ns

ns

Note

1. This timing will be up to 3 clock cycles for the first read in DMA transfer.

1998 Feb 05 14

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

handbook, full pagewidth

A2 to A0

t

1

D7 to D0

CS1 or CS0

R/W

LDS

DTACK

(1)

A

(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).

Fig.6 Motorola mode interface read cycle timing.

valid address

t

4

t

0

t

2

valid data 3-state3-state

t

3

t

7

t

5

t

6

MGK148

(2)

B

Table 6 Motorola-mode interface read cycle timing (12 MHz clock)

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

0

t

1

t

2

t

3

t

4

t

5

t

6

t

7

minimum cycle time 333 833 ns
address set-up time before event A 0 − ns
address hold time after event B 0 − ns
data hold time from event B 0 − ns
data settling time 88 712 ns
data valid to DTACK LOW 83 170 ns
LDS HIGH to DTACK HIGH 83 212 ns
delay between cycles 83 − ns

1998 Feb 05 15

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

handbook, full pagewidth

A2 to A0

t

1

D7 to D0

CS1 or CS0

R/W

LDS

DTACK

(1)

A

(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).

Fig.7 Motorola mode interface write cycle timing.

t

4

valid address

t

5

t

0

t

2

valid data 3-state3-state

t

3

t

7

t

6

(2)

B

MGK149

Table 7 Motorola-mode interface write cycle timing (12 MHz clock)

SYMBOL DESCRIPTION MIN. MAX. UNIT

t

0

t

1

t

2

t

3

t

4

t

5

t

6

t

7

minimum cycle time 333 417 ns
address set-up time before event A 0 − ns
address hold time after event B 0 − ns
data hold time from event B 0 − ns
data set-up time 0 − ns
DTACK set-up time − 212 ns
LDS HIGH to DTACK HIGH 83 212 ns
delay between cycles 83 − ns

1998 Feb 05 16

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

handbook, full pagewidth

SCL

SDA

handbook, full pagewidth

VPOIN

t

BUF

t

0

t

SU;STA

t

HD;STA

t

HIGH

t

LOW

t

SU;DAT

Fig.8 I2C-bus timing diagram.

t

r

t

f

t

HD;DAT

t

SU;STO

MGG741

VPOOUT

CS0 or CS1

LLC

LLC2

t

1

t

4

t

2

t

3

MGK150

Fig.9 Digital video mode interface timing.

Table 8 Digital video mode interface timing with 13.5 MHz clock and 27 MHz LLC

SYMBOL DESCRIPTION MIN. TYP. MAX. UNIT

t

0

t

1

t

2

t

3

t

4

VPOIN set-up time 4 5 6 ns
VPOOUT set-up time 8 10 22 ns
CS HIGH to VPOOUT 3-state 6 10 25 ns
CS LOW to VPOOUT enabled 9 11 16 ns
clock qualifier set-up time − 1.1 − ns

1998 Feb 05 17

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

13 APPLICATION INFORMATION

13.1 Hardware application circuit for ISA card

A typical application circuit diagram (for the ISA card
application) is shown in Fig.10.

13.2 Hardware application circuit for PCI application

This PCI application is based around the Philips SAA7146
video to PCI bridge IC. SAA7146 has a ‘Data Expansion
Bus Interface’ (DEBI) which is an Intel/Motorola style
16-bit parallel interface. This is used to facilitate
communications to SAA5284.

The application circuit diagram is shown in Fig.11.

13.3 Software application information

PC application software is available providing two levels of
interface. At a low level a VxD based driver offers generic
packet gathering and buffering. Full support is provided for
ISA based applications with facility for PCI based
applications. Higher level support is provided by a series
of DLLs. These perform normal teletext display generation
and page management.

1998 Feb 05 18

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

handbook, full pagewidth

V

= 0 V

SSA

75 Ω

CVBS0

CVBS1

75 Ω

V

SSA

= 0 V

22
pF

100 nF

27 kΩ

100 nF

100 nF

100

nF

12 MHz

22
pF

V

SSD

V

DDA

BLACK

I

REF

CVBS0

CVBS1

OSCIN

(1)

OSCOUT

OSCGND

SDA
SCL

HREF

LLC

LLC2
VPOIN1
VPOIN0

= 0 V

V

SSA

supply decoupling

10

100

µF

nF

V

= +5 V

V

= +5 V

DDA

V

DDA

16 41 6

12

13

15

14

8

7

DDD

V

DDDVDDX

SAA5284

9

3
4
2
42
43
39
38

17 40 18 19 11 10

V

SSAVSSD3VSSD1VSSD2

= 0 V

V

= 0 V

SSD

V

DDD

10

µF

+5 V

SEL1 SEL0 CS1

n.c.

D7

20

D6

21

D5

22

D4

23

D3

24

D2

25

D1

26

D0

27

A0

28

A1

29

A2

30

INT

31

RDY

32

WR

33

RD

34

DMARQ

36

DMACK

37

RESET

1

DENB

5

CS0

35

44

B9
B8
B7
B6
B5
B4
B3
B2

11

19
18
17
16
15
14
13
12

D7
D6
D5

D4
D3
D2
D1
D0

A0
A1
A2

IRQx

(2)

I/O RDY
IOW
IOR
DACKx

(3)

RESET
n.c.

B1

ADDRESS

DECODER

e.g.

PLUS153

or

74 SERIES

LOGIC

B0

9

I0

1

AEN

I1

A3

2

I2

A4

3

I3

A5

4

I4

A6

5

I5

A7

6

I6

A8

7

I7

A9

8

V

SSA

(1) Option of 13.5, 15 and 16 MHz or direct feed from external clock.
(2) A diode to V
(3) Pin DMACK must be connected to V

is recommended for ESD protection.

DDD

DDD

V

SSD

if DMA is not used.

0 V

Fig.10 Application circuit diagram for ISA card.

1998 Feb 05 19

10 20

GND

V

= 0 V V

SSD

DDD

V

CC
= 5 V

MGG742

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1998 Feb 05 20

100

nF

V

V

DDA

SSA

V

= 0 V

SSA

75 Ω

CVBS0

CVBS1

75 Ω

V

= 0 V

SSA

supply decoupling

V

DDD

10

100

µF

nF

V

SSD

22
pF

10

µF

100 nF

27 kΩ

100 nF

100 nF

+5 V

0 V

12 MHz

22
pF

V

SSD

BLACK

I

REF

CVBS0

CVBS1

OSCIN

(1)

OSCOUT

OSCGND

SDA
SCL

HREF

LLC

LLC2
VPOIN1
VPOIN0

= 0 V

V

V

= +5 V

DDA

V

DDA

16 41 6

12

13

15

14

8

7

9

3
4
2
42
43
39
38

17 40 18 19 11 10 44

V

SSAVSSD3VSSD1VSSD2

V

= 0 V

SSA

V

SSD

DDD

= 0 V

handbook, full pagewidth

= +5 V

V

DDDVDDX

SAA5284

SEL1 SEL0 CS1

20
21
22
23
24
25

26
27

28
29

30

35
31
32
33
34
36
37

1
5

D7
D6
D5
D4
D3
D2

D1
D0

A0

1Q

A1

2Q

A2

3Q

CS0
INT
RDY
WR
RD
DMARQ
DMACK
RESET
DENB

16
15

74HCT75

10

13 4

LE LE

n.c.
V

DDD

n.c.

2
3

6
7

5 kΩ

1D
2D

3D
4D

V

DDD

XAD7
XAD6
XAD5
XAD4
XAD3
XAD2
XAD1
XAD0

ALE

XIRQ

RDY

WRN

RDN

RESET

SAA7145
SAA7146

DEBI PORT

132
131
130
129
126
125
124
123

114
118
117
116
115

23

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

MGG744

(1) Option of 13.5, 15 and 16 MHz or LLC2 from the SAA7111 if in 13.5 MHz mode.

Fig.11 Application circuit diagram for PCI application.

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

14 PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm

c

y

X

33 23

34

pin 1 index

44

1

Z

22

E

e

w M

b

p

12

11

A

H

E

E

A

2

A

A

1

detail X

SOT205-1

(A )

3

θ

L

p

L

Z

e

w M

b

p

D

H

D

D

B

v M

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.60

0.25

0.05

2.3

2.1

0.25

UNIT A1A2A3b

cE

p

0.50

0.25

0.35

0.14

(1)

(1) (1)(1)

D

14.1

13.9

eH

14.1

13.9

19.2

1

18.2

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT205-1

IEC JEDEC EIAJ

133E01A

REFERENCES

1998 Feb 05 21

v M

A

B

E

19.2

18.2

LL

p

2.0

1.2

0.152.35 0.10.3

H

D

EUROPEAN

PROJECTION

Z

D

2.4

1.8

Zywv θ

E

o

2.4

7

o

1.8

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

15 SOLDERING

15.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

15.2 Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

15.3 Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Feb 05 22

Philips Semiconductors Objective specification

Multimedia video data acquisition circuit SAA5284

16 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

18 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1998 Feb 05 23

Philips Semiconductors – a worldwide company

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Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
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Colombia: see South America
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Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

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Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

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20124 MILANO, Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
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Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 655102/00/02/pp24 Date of release: 1998 Feb 05 Document order number: 9397 750 02768