• Complete 625-line teletext decoder in a single
integrated circuit thereby reducing printed-circuit board
area and cost
• Automatic detection of transmitted pages so that only
existing pages will be selected by page-up and
page-down once inventory validated
• Automatic detection of transmitted Fastext links or
service information (packet 8/30)
• On-screen display for user interface (menus, etc.) using
teletext and dedicated menu icons
• Video Programming System (VPS) decoding
• Wide Screen Signalling (WSS) decoding
• 8-page Fastext decoder
• 6-page TOP decoder in addition to capture ofBasic TOP
Table (BTT) and 3 Additional Information Table (AIT)
pages
• 4-page user defined list mode
• Yugoslavian, Cyrillic, Greek/Turkish, Thai,
Arabic/Hebrew, Pan-European and
Arabic/English/French language coverage
• High level command interface via I
control from a low software overhead
• High level command interface is backward compatible to
SAFARI interface
• 625 and 525 line display
• RGB interface to standard colour decoder ICs, push-pull
output drive
• Versatile 8-bit open-drain I/O expander
• Single 12 MHz crystal oscillator for reduced cost
• +5 V power supply.
2
C-bus giving easy
SAA5262 and SAA5263
• Automatic Channel Installation (ACI)
• Enhanced SAFARI interface providing additional
commands.
SAA5263
• Electronic Programme Guide (EPG) feature.
GENERAL DESCRIPTION
The SAA526xPS ICs are single-chip 10-page 625-line
World System Teletext (WST) decoders with a high level
command interface, SAFARI compatible.
It has been designed so that the overall system cost is kept
to a minimum. This has been achieved through the
capability of the device to be driven from a single +5 V
power supply, low cost 12 MHz crystal oscillator and the
high level command interface, which offers the benefit of
low software overhead in the TV microcontroller.
The SAA526xPS offers automatic detection of Fastext or
TOP transmissions. The device also incorporates a facility
to detect the pages in the transmission, which allows only
transmitted pages to be selected by page-up and
page-down.
SAA5262 and SAA5263 provide Automatic Channel
Installation (ACI) information.
SAA5263 provides access to Electronic Programme Guide
(EPG) information.
V01versatile open-drain input/output bit 0 (should be tied HIGH)
V12versatile open-drain input/output bit 1 (should be tied HIGH)
V23versatile open-drain input/output bit 2 (should be tied HIGH)
V34versatile open-drain input/output bit 3 (should be tied HIGH)
V45versatile open-drain input/output bit 4 (should be tied HIGH)
V56versatile open-drain input/output bit 5 (should be tied HIGH)
V67versatile open-drain input/output bit 6 (should be tied HIGH)
V78versatile open-drain input/output bit 7 (should be tied HIGH)
res9reserved
res10reserved
res11reserved
res12reserved
V
SSD1
SCLK114serial clock input 1 (NVRAM)
SDAT115serial data input/output 1 (NVRAM)
SA16slave address input: LOW selects 58H; HIGH selects 60H
FP17field polarity input: LOW selects first half line; HIGH selects second half line at the start of an
HSMODE18horizontal sync mode control input: LOW selects HSYNC on rising edge
VSMODE19vertical sync mode control input. LOW selects VSYNC on rising edge
PDI20power-down imminent input: this input should be pulled LOW to indicate that the system is
PL21phase-lock output: HIGH indicates that the system is phase-locked to the CVBS input
V
SSA
CVBS123CVBS input: this signal is applied via a 100 nF capacitor (nominal input 1 V (p-p)
CVBS224this pin should be connected to ground if unused
BLACK25black level input: a 100 nF capacitor should be connected to V
I
ref
FRAME27Frame output for use in non-interlaced displays: during teletext off, teletext mixed with TV
V
SSD2
COR29contrast reduction: active LOW output which allows selective contrast reduction of the
PON30picture on output: HIGH indicates that a TV picture is present and that the SAA526xPS is in
RGBREF31RGB reference input: drive level reference for RGB outputs
B32blue dot rate character output of the blue colour information: the high voltage level is defined
13digital ground 1
even field
about to lose power
22analog ground
SSA
26reference current input for analog circuits: for correct operation a 27 kΩ resistor should be
connected to V
SSA
picture and subtitles this pin is inactive. In full teletext mode this pin provides a 25 Hz square
wave. FRAME = 1 = odd, FRAME = 0 = even.
28digital ground 2
television picture to enhance a mixed mode display
TV mode, mix mode, subtitle mode or news flash mode
G33green dot rate character output of the green colour information: the high voltage level is
defined by the RGBREF pin (can source 4 mA)
R34red dot rate character output of the red colour information: the high voltage level is defined by
the RGBREF pin (can source 4 mA)
VDS35push-pull output for blanking the TV picture
HSYNC36horizontal sync input: the polarity of this pulse is set by input HSMODE
VSYNC37vertical sync input: the polarity of this pulse is set by input VSMODE
V
DDA
V
DDD(T)
OSCGND40ground for crystal oscillator
XTALI4112 MHz crystal oscillator input
XTALO4212 MHz crystal oscillator output
RESET43reset input
V
DDD(M)
PUINL45power-up in list mode control input: LOW selects auto TOP/Fastext on power-up; HIGH
DISDSR46disable default status row input: LOW enables display of status row
DIS8/3047disable packet 8/30 display input: LOW enables display of packet 8/30
DISLCBD48disable Link Control Byte (LCB) decode input: LOW enables decoding of the LCB in Fastext
SCLK249serial clock input (I
SDAT250serial data input/output (I
ME8/30T51mesh 8/30 and time displays input: HIGH will select a meshed display for the packet 8/30 and
E/
W52East/West language select input: LOW selects West language
38analog supply voltage (+5 V)
39digital supply voltage for teletext circuits (+5 V)
44digital supply voltage for microcontroller (+5 V)
The I2C-bus interface is used to pass control commands and data between the SAA526xPS and the television
microcontroller. The interface uses high level commands, which are backward compatible with the SAFARI interface.
The formats for the I2C-bus transmission are as follows:
33−digit 4
34−digit 5
35−digit 6
36−digit 7
37−digit 8
38−digit 9
39−digit 0
3A−size
3B−up
3C−down
3D−cyan
3E−mix
3F−text
4A0read PAL + line
8900 to 41select list
9100 to 03 or
9200read broadcast status
9300 or 01read network
940read PCS byte
98OSD dataOSD mode on
990OSD mode off
9A0OSD display on
9B0OSD display off
9C0OSD cursor on
9D0OSD cursor off
9E0, row, columnOSD position
9F0 followed by
A000 to FFbitwise parameter or
A100 to FFbitwise parameter
A200 to FFreturns V7to V0 on
A3PWM
B0regdataor text register
B1regdataand text register
B2regdataread text register
B80quick list
DATA
BYTE
00 to 80
20 bytes
No.
PWM
data
COMMAND
DESCRIPTION
force mode
identification
OSD data write
V7 to V0
and V7 to V0
2
C-bus read
I
PWM control
COMMAND
BYTE
(HEX)
SAA5262 and SAA5263 only
B90get time
C00 = disableset ACI mode
C10get ACI status
C20select next ACI channel
C3information type get ACI information
D00get device version
D1page type and
D2page typeget page number
D3page type and
D4page typeget language
D5row 24 controlenable/disable row 24
D6start column
The character sets for the languages Yugoslavian, Cyrillic, Greek/Turkish, Thai, Arabic/Hebrew, Pan-European,
Arabic/English/French and Iranian are available on request.
data set-up time≥250 nsnote 1≥250 ns
data hold time≥0 nsnote 1≥0ns
repeated START set-up time≥4.7 µsnote 1≥4.7 µs
STOP condition set-up time≥4.0 µsnote 1≥4.0 µs
bus free time≥4.7 µsnote 1≥4.7 µs
SDA rise time≤1.0 µsnote 3≤1.0 µs
SDA fall time≤0.3 µs≤0.3 µs; note 4≤0.3 µs
Notes
1. This parameter is determined by the user software. It must comply with the I
2
C-bus specification.
2. This value gives the auto-clock pulse length which meets the I2C-bus specification for the special crystal frequency.
Alternative, the SCL pulse must be timed by software.
3. The rise time is determined by the external bus line capacitance and pull-up resistor. It must be less than 1 µs.
4. The maximum capacitance on bus lines SDA and SCL is 400 pF.
1998 Apr 2220
Page 21
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The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between pins
XTALI and XTALO is basically an inverter biased to the transfer point. A crystal must be used as the feedback element
to complete the oscillator circuitry. It is operated in parallel resonance. XTALI is the high gain amplifier input and XTALO
is the output.
To drive the device externally XTALI is driven from an external source and XTALO is left open-circuit.
handbook, halfpage
(1) The values of C1 and C2 depend on the crystal specification:
Optimization of circuit return paths and minimisation of
common mode noise will be assisted by using a
double-sided PCB with a low inductance ground plane.
On a single-sided PCB a local ground plane under the
whole IC should be present, as shown in Fig.16. This
should be connected by the widest possible connection
back to the PCB ground connection and bulk electrolytic
decoupling capacitor. It should preferably not connect to
other grounds on the way and no wire links should be
present in this connection. The use of wire links increases
ground bounce by introducing inductance into the ground.
The supply pins can be decoupled at the pin to the ground
plane under the IC. This is easily accomplished using
surface mount capacitors, which are more effective than
leaded components at high frequency. Using a device
socket will unfortunately add to the area and inductance of
the external bypass loop.
A ferrite bead or inductor with resistive characteristics at
high frequency may be utilized in the supply line close to
the decoupling capacitor to provide a high impedance.
To prevent pollution by conduction onto signal lines (which
may then radiate) signals connected to the +5 V supply via
a pull up resistor should not be connected to the IC side of
the ferrite component.
OSCGND should be connected only to the crystal load
capacitors and not the local or circuit ground.
Keep physical connection distances to associated active
devices short.
Route output traces with close proximity mutually coupled
ground return paths.
handbook, full pagewidth
under-IC GND plane
GND connection
note: no wire links
other
GND
connections
+5 V
GND
V
DDD(M)
electrolytic decoupling capacitor (2.2 µF)
ferrite components
SM decoupling capacitors (22 to 100 nF)
SSD
V
DDA
V
SSA
V
DDD(T)
V
Fig.16 Power supply and ground connections for SOT247-1.
under-IC GND plane
IC(SAA5290)
MGL414
1998 Apr 2223
Page 24
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There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
260 °C; solder at this temperature must not be in contact
DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I
2
C COMPONENTS
Purchase of Philips I
2
C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands545104/00/01/pp28 Date of release: 1998 Apr 22Document order number: 9397 750 03442
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