Datasheet saa4945h DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA4945H

LIne MEmory noise Reduction IC
(LIMERIC)

Preliminary specification
File under Integrated Circuits, IC02

1997 Jun 10

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

FEATURES

• 2-D adaptive vertically recursive noise reduction

• Noise reduction for Y, U and V signals in 4 : 1 : 1 format

• Single 5 V ±10% power supply

• Communication by means of serial communication

protocol 83C654 (SNERT bus)

• Via SNERT bus, 10 different types of noise reduction
selectable; the noise reduction function can also be
disabled

• Phase relation write enable input/output signal
simultaneously switchable over one clock period w.r.t.
input/output samples

• 8-bit wide data processing for Y, U and V; in unsigned
format (Y signal) and in 2’s complement (U and V
signals)

• One fixed line locked clock operation frequency up to
16 MHz (typical)

• Exactly one line delay.

SAA4945H

GENERAL DESCRIPTION

The SAA4945H, LIMERIC (LIne MEmory noise Reduction
IC) is a 2-D recursive noise reduction filter for both
luminance and colour difference signals. The noise
reduction is automatically adapted to the global noise level
in the image. Ten different preferences of noise reduction
can be set using a synchronous receiver transmitter bus;
SNERT (Synchronous No parity Eight bit Receive
Transmit) bus. Alternatively, the noise reduction can be
switched off. The LIMERIC is generally placed directly
after the ADC in the feature box and works fully in the 1f
(50/60 Hz) domain.

h

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DD

supply voltage (pins 5, 29 and 30) 4.5 5.0 5.5 V

supply current − 70 − mA
P power dissipation − 350 − mW
f

CLK

f

SNERT

T

amb

clock frequency ±7%; note 1 10 16 17.1 MHz

bus clock frequency −−1 MHz

operating ambient temperature 0 − 70 °C

Note

1. Maximum number of clocks per line is 1024.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA4945H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2

1997 Jun 10 2

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

BLOCK DIAGRAM

handbook, full pagewidth

NOISE

UI0, U

VI0, V

16, 15

I1
I1

18, 17

REFORMATTER

REDUCTION

FILTER

(MULTIPLEXED)

N_thr_UV

RAM_UV ∆t

V

DD1

5

V

FORMATTER

DD2

V

29

DD3

SAA4945H

30

36, 37
34, 35

UO0, U
VO0, V

O1

O1

Y

to Y

I0

I7

814 to 7

8

NOISE

REDUCTION

FILTER

N_thr_Y

NOISE

ESTIMATOR

TASTE

NTHR

SNERT

INTERFACE

SDNA

SNCL

N_thr_UV

val

W

YpScale

VRST

RAM_Y

SAA4945H

internal

control

signals

CONTROL

432

2221

19

VaCLK

I

6

GND1WE

20

GND2

23

GND3

TEST

CONTROL

27

GND4

GND5

38 to 44, 1

28

32

GND6

Y

to

O0

YO6, Y

O7

26

TST0

25

TST1

24

TST2

31

WE

O

33

n.c.

MGK170

Fig.1 Block diagram.

1997 Jun 10 3

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

PINNING

SYMBOL PIN TYPE DESCRIPTION

Y

O7

SNDA 2 input/output data from interface SNERT bus
SNCL 3 input clock from interface SNERT bus
VRST 4 input reset in the vertical blanking interval
V

DD1

GND1 6 ground ground 1
Y

I7

Y

I6

Y

I5

Y

I4

Y

I3

Y

I2

Y

I1

Y

I0

U

I1

U

I0

V

I1

V

I0

CLK 19 input master clock
GND2 20 ground ground 2
WE

I

Va 22 input vertical blanking pulse
GND3 23 ground ground 3
TST2 24 input test pin 2
TST1 25 input test pin 1
TST0 26 input test pin 0
GND4 27 ground ground 4
GND5 28 ground ground 5
V

DD2

V

DD3

WE

O

GND6 32 ground ground 6
n.c. 33 − not connected
V

O0

V

O1

U

O0

U

O1

Y

O0

Y

O1

Y

O2

1 output luminance output bit 7

5 supply supply voltage 1

7 input luminance input bit 7 from analog-to-digital converter
8 input luminance input bit 6 from analog-to-digital converter

9 input luminance input bit 5 from analog-to-digital converter
10 input luminance input bit 4 from analog-to-digital converter
11 input luminance input bit 3 from analog-to-digital converter
12 input luminance input bit 2 from analog-to-digital converter
13 input luminance input bit 1 from analog-to-digital converter
14 input luminance input bit 0 from analog-to-digital converter
15 input U input bit 1 from analog-to-digital converter
16 input U input bit 0 from analog-to-digital converter
17 input V input bit 1 from analog-to-digital converter
18 input V input bit 0 from analog-to-digital converter

21 input write enable input

29 supply supply voltage 2
30 supply supply voltage 3
31 output write enable output

34 output V output bit 0
35 output V output bit 1
36 output U output bit 0
37 output U output bit 1
38 output luminance output bit 0
39 output luminance output bit 1
40 output luminance output bit 2

SAA4945H

1997 Jun 10 4

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

SYMBOL PIN TYPE DESCRIPTION

Y

O3

Y

O4

Y

O5

Y

O6

handbook, full pagewidth

41 output luminance output bit 3
42 output luminance output bit 4
43 output luminance output bit 5
44 output luminance output bit 6

O1

O6

YO5YO4YO3YO2YO1Y

Y
44

43

42

41

O0

U

40

39

38

37

UO0VO1V
36

35

O0

34

SAA4945H

Y

O7

SNDA

SNCL
VRST
V

DD1

GND1

Y
Y
Y
Y
Y

22
Va

33
32
31
30
29
28
27
26
25
24
23

MGK169

n.c.
GND6
WE
V

DD3

V

DD2

GND5
GND4
TST0
TST1
TST2
GND3

O

1
2
3
4
5
6
7

I7

8

I6

9

I5

10

I4

11

I3

12

13

I2

I1

Y

Y

14

I0

Y

SAA4945H

15

16

I1

I0

U

U

19

CLK

20

GND2

21

I

WE

17

18

I0

I1

V

V

Fig.2 Pin configuration.

1997 Jun 10 5

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

FUNCTIONAL DESCRIPTION

The digital LIMERIC is an effective low noise reduction IC
for luminance and colour difference signals. Noise filtering
is automatically adapted to the global noise level which is
measured within the picture content. The two dimensional
non-linear noise reduction (one for luminance, one for
chrominance) uses only line memory to function.
Furthermore, up to 10 different preferences can be set by
the user.

As shown in Fig.1, the main components of the device are
the noise reduction filter with the line memories (RAM) and
the noise estimator. Other components shown are the
reformatter, formatter, controller and a SNERT bus
transceiver.

Noise reduction filter

Both luminance and chrominance signals are filtered with
vertical recursion. This is produced as the filter receives
both filtered samples from the previous line, and unfiltered
samples from the current line. A new replacement value is
calculated for each sample read from the line memory.
This in turn, is the filtered response value for the reference
input pixel. The reference pixel is then placed at the centre
of the delay-line into which the current (unfiltered) video
line is shifted. Tables 1 to 6 show this as an ‘O’.

Both luminance and colour difference signals are filtered
using the so-called Discriminating AveragingFilter (DAF),
in which filter coefficients are related to the Absolute
Difference (AD) between samples. The filter uses samples
from both present and previous line (using the line delay)
and the result of the filter is stored back in the line memory.
In this way a vertical recursive structure is realized.

The filter coefficients are set depending on the noise
measured by the noise estimator or the NTHR (SNERT
register F9).

SAA4945H

LUMINANCE FILTER
The taps structure of the luminance filter is as shown in

Table 2.

Table 2 Luminance processing

X . . . . X . . . X . . . X . . . . X ← 5 Y samples from the

filtered line (distance 4 / 5
pixel)

o . O . o ← 3 Y samples from the

incoming line (distance 2
pixels)

A ‘weave’ function is used to reduce any smearing effect
that could occur at edges. As shown in Tables 3 to 6, the
‘weave’ calculates over 4 consecutive lines. The relative
position of the actual pixel changes one position every line.

Table 3 For line 2n

X . . . . X . . . X . . . X . . . . X

o . O . o

Table 4 For line 2n + 1

X . . . . X . . . X . . . X . . . . X

. . o . O . o

Table 5 For line 2n + 2

X . . . . X . . . X . . . X . . . . X

o . O . o

Table 6 For line 2n + 3

X . . . . X . . . X . . . X . . . . X

o . O . o . .

C

HROMINANCE FILTER

The basic signal processing for either U or V is via the
same filter. It is used to process both V and U using a
multiplexed operation.

The taps structure of the chrominance filter is as shown in
Table 1.

Table 1 Chrominance processing

X X X X X ← 5 adjacent R − Y samples from the

filtered line

o O o ← 3 adjacent R − Y samples from the

incoming line

1997 Jun 10 6

Table 7 Weave configuration
Depending on even and odd fields the ‘weave’ has the

following configuration:

ODD FIELDS EVEN FIELDS

XX

XX

XX

XX

XX

XX

XX

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC

SAA4945H

(LIMERIC)

Noise estimator

The threshold value N_thr for the filters is calculated in the noise estimator block (see Fig.3). There are four options for
producing the N_thr value:

1. Pre-filter gain setting (YpScale)

2. W

3. TASTE (TS) scales the N_thr linear

4. NTHR is externally applied when the noise estimator is disabled by the control bit ExThr of the Status Register.

handbook, full pagewidth

selects the sensitivity of the noise estimator

val

PRE-FILTERY

I

YpScale

NOISE ESTIMATOR

W

val

TS0-TS3

Fig.3 Noise estimator.

×

4

NTHR

MUX

ExThr

N_thr

MGK171

SIGNAL DESCRIPTION
Input signals

TO Y

Y

I7

(PINS 7 TO 14)

I0

• Eight bit wide digital luminance input bus

• Unsigned data; dynamic range between 0 and 255

• The maximum number of input samples equals

852 active samples/line.

U

I1

AND U

(PINS 15 AND 16)

I0

• Colour difference signal U

• Data in 2’s complement; dynamic range between

−128 and +127

• Y : U : V format 4 : 1 : 1; see Table 8 for input data

coding

• The maximum number of input samples equals
213 samples/line

• Internal data processing of U signals in unsigned format.

V

I1

AND V

(PINS 17 AND 18)

I0

• Colour difference signal V

• Data in 2’s complement; dynamic range between

−128 and +127

• Y : U : V format 4 : 1 : 1; see Table 8 for input data

coding

• The maximum number of input samples equals
213 samples/line

• Internal data processing of V signals in unsigned format.

1997 Jun 10 7

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

Table 8 Input /output data coding

INPUT BIT INPUT DATA SEQUENCE

YY7Y

Y6 Y
Y5 Y
Y4 Y
Y3 Y
Y2 Y
Y1 Y
Y0 Y

U UI1 U

UI0 U

V VI1 V

VI0 V

WEI(PIN 21)

• Write enable input

• Write enable indicates the time when active input

samples (Y, U and V) are present

• Timing relation (see Fig.4) depending on the logic level
of the Write Enable Select signal (WES) in status
register; to adapt to different external video memories

7Y

0

6Y

0

5Y

0

4Y

0

3Y

0

2Y

0

1Y

0

0Y

0

7U

0

6U

0

7V

0

6V

0

• The number of input samples is a multiple of 4 (see

• Start of new line indicated by write enable signal LOW

• During active line, WE

SAA4945H

7Y

1

6Y

1

5Y

1

4Y

1

3Y

1

2Y

1

1Y

1

0Y

1

5U

0

4U

0

5V

0

4V

0

Fig.4)

for at least 4 consecutive clock periods (see Fig.4)

more than 1 clock cycle.

7Y

2

6Y

2

5Y

2

4Y

2

3Y

2

2Y

2

1Y

2

0Y

2

3U

0

2U

0

3V

0

2V

0

is not allowed to be LOW for

I

7

3

6

3

5

3

4

3

3

3

2

3

1

3

0

3

1

0

0

0

1

0

0

0

1997 Jun 10 8

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

handbook, full pagewidth

CLK

WE

I

(WES = 0 status register)
WE

I

(WES = 1 status register)

line n

Y

to Y

I0

I7

UI0, U

I1

VI0, V

I1

CLK

WE

O

(WES = 0 status register)
WE

O

(WES = 1 status register)

line n + 1

Y

to Y

I0

I7

X X

X

X

X X

SAA4945H

Y

0

Y

0

Y

1

Y

1

X

XX

XX

one sequence; X: non valid data

X

Y

2

Y

2

Y

3

U

. 1,0U0. 3,2U0. 5,4U0. 7,6

0

V

. 1,0V0. 3,2V0. 5,4V0. 7,6

0

Y

3

UI0, U

VI0, V

I1

I1

X

X

Fig.4 Write enable timing.

Va (PIN 22)

• Vertical synchronization signal, active HIGH

• Minimum HIGH period equals one line period

• Vertical synchronization signals converted to system

clock domain internally. So the Va pulse can be
asynchronous.

• See timing diagram Fig.6 and Table 11 for timing
specification.

U

XX

XX

one sequence; X: non valid data

. 1,0U0. 3,2U0. 5,4U0. 7,6

0

V

. 1,0V0. 3,2V0. 5,4V0. 7,6

0

MGK172

CLK (PIN 19)

• Line locked system clock, up to 16 MHz typical

• All clock related signals act on the rising edge of the

system clock.

TST0, TST1

AND TST2 (PINS 26, 25 AND 24)

• Test mode inputs

• Active HIGH, with internal pull-down resistors.

1997 Jun 10 9

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC

SAA4945H

(LIMERIC)

Table 9 Test settings

TST2 TST1 TST0 MODE

0 0 0 application mode

(1)

X
1X

(1)

X

1X

(1)
(1)

X

Note

1. X = don’t care.

SNDA, SNCL

AND VRST (PINS 2, 3 AND 4)

• Serial interface signals

• SNERT bus protocol (Synchronous No parity 8-bit receiver and Transmission bus)

• SNDA is a bidirectional signal with 8-bit wide data and address (LSB first)

• Serial interface signals converted (internally) to system clock domain. To avoid set-up violations these signals are

clocked two times by the system clock before further processing is performed.

• Synchronization of serial address (every even byte) and data (every odd byte) by VRST.

(1)
(1)

X

test mode
test mode

1 test mode

h(D)

t

d(D)

data
valid

T

cy(SNCL)

data
valid

data
valid

handbook, full pagewidth

SNCL

SNDA
(receiver
mode)

SNDA
(transmitter
mode)

LSB

data

valid

data

valid

t

su(i)(D)

data
valid

t

h(Q)

t

Fig.5 Timing diagram of serial interface.

Table 10 Timing characteristics (see Fig.5)

SYMBOL PARAMETER MIN. MAX. UNIT

t

cy(SNCL)

t

su(i)(D)

t

h(D)

t

h(Q)

t

d(D)

SNCL cycle time 1 −µs
input set-up time 90 − ns
input hold time 50 − ns
output data hold time 0 − ns
output data delay time − 700 ns

data
valid

MGK173

1997 Jun 10 10

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

Output signals

Y

TO Y

O0

• 8-bit wide digital luminance output bus

• Data format: unsigned, dynamic range between

0 and 255.

U

AND U

O1

• Colour difference signal U

• Data format: 2’s complement, dynamic range between

−128 and +127

• Y : U : V format 4 : 1 : 1; see Table 8.

V

AND V

O1

• Colour difference signal V

• Data format: 2’s complement, dynamic range between

−128 and +127

• Y : U : V format 4 : 1 : 1; see Table 8.

(PINS 38 TO 44 AND 1)

O7

(PINS 37 AND 36)

O0

(PINS 35 AND 34)

O0

SAA4945H

WE

(PIN 31)

O

• Write enable output

• Write enable indicates the time when active samples (Y,

U and V) are present

• Timing relation (see Fig.6) depending on write enable
select signal (WES) in status register; to adapt to
different external video memories

• The number of output samples is a multiple of 4

• The write enable output sequence is a copy of the write

enable input sequence of the previous line (see Fig.6)
with a shift of one line

• The last line in field is not processed.

handbook, full pagewidth

Va

VRST

WE

I

WE

O

internal flag
to mask
WE

O

t

Va(min)H

t

su(Va)

t

(WE-VRST)LH

L(n−1) L(n) L(0) L(2)L(1)

L(n−2) L(n−1) L(0) L(1)

1 clk cycle

t

(Va-WE)LH

t

(Va-VRST)LH

MGK174

Fig.6 Timing diagram for WEO blanking and Va.

1997 Jun 10 11

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

Table 11 Va versus VRST

SYMBOL PARAMETER MIN. UNIT

t

Va(min)H

t

su(Va)

t

(Va-WE)LH

t

(Va-VRST)LH

t

(WE-VRST)LH

LIST OF SNERT BUS ADDRESSES USED IN LIMERIC
TASTE register
Table 12 TASTE register usage

USE ACTION

Purpose to set 4 different types of noise reduction
Address F3
Read/write write
Range 0 to 4; 0 = noise filtering disabled

minimum Va HIGH time 64 µs
set-up Va to negative edge of WE

I

Va LOW to WEI HIGH time 0 µs
Va LOW to VRST HIGH time 0 µs
WEI LOW to VRST HIGH time 64 µs

SAA4945H

0 µs

Table 13 TASTE register content

MSB LSB REMARK

0000ts3ts2ts1ts0see Table 14

Table 14 TASTE setting

TS3 TS2 TS1 TS0 FUNCTION

0000noise filtering disabled
0001not applicable
0010noise reduction; TASTE 1
0011not applicable
0100noise reduction; TASTE 2
0101not applicable
0110noise reduction; TASTE 3
0111not applicable
1000noise reduction; TASTE 4
1001not applicable
1010not applicable
1011not defined
1100not defined
1101not defined
1110not defined
1111not defined

1997 Jun 10 12

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC

SAA4945H

(LIMERIC)

Status register
Table 15 Status register usage

USE ACTION

Purpose internal settings
Address F4
Read/write write

Table 16 Status register content

MSB LSB

Tctrl3 Tctrl2 Tctrl1 X ExThr Wv DEM WES

Table 17 Status register description

BIT NAME DESCRIPTION

0 WES Write Enable Select

0: data coincides with write enable (both input and output)
1: data is delayed over one clock period with respect to the write enable (both input and output)

see Fig.4

1 DEM Demo Mode

0: demo mode disabled
1: demo mode on; the noise reduction circuit is switched on for the left half of the screen - the noise

reduction is disabled (split screen function) for the right half of the screen

2 Wv Weave

0: enable weave
1: disable weave

3 ExThr External Threshold control bit

0: N_thr calculated by noise estimator

1: value of N_thr from register F9 is used
4 X don’t care
5 Tctrl1 Test control 1

0: normal operation

1: test mode
6 Tctrl2 Test control 2

0: normal operation

1: test mode
5 Tctrl3 Test control 3

0: normal operation

1: test mode

1997 Jun 10 13

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

W

register (wanted value)

val

Table 18 W

Purpose register for setting up noise estimator
Address F5
Read/write write
Range 0 to 255

Table 19 W

MSB LSB CONDITIONS

W

val7

Noise threshold register
Table 20 Noise threshold register usage

Purpose register for setting the NTHR value for the noise filter externally
Address F9
Read/write write
Range 0 to 255

register usage

val

USE ACTION

register

val

W

val6

W

val5

W

val4

W

val3

W

val2

W

val1

W

val0

USE ACTION

Tctrl2 = 0

SAA4945H

Table 21 Noise threshold register content

MSB LSB

NTHR[7] NTHR[6] NTHR[5] NTHR[4] NTHR[3] NTHR[2] NTHR[1] NTHR[0]

Noise estimator setting register
Table 22 Noise estimator setting register usage

USE ACTION

Purpose register for general setting of the noise estimator
Address FA
Read/write write

Table 23 Noise estimator setting register

MSB LSB

YpScale1 YpScale0 000000

Table 24 Noise estimator setting description

YpScale1 YpScale0 DESCRIPTION

0 0 noise estimator pre-filter gain setting= 1
0 1 noise estimator pre-filter gain setting= 0.5
1 0 noise estimator pre-filter gain setting= 0.25
1 1 noise estimator pre-filter bypassed

1997 Jun 10 14

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC

SAA4945H

(LIMERIC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD1

V

DD2

V

I

T

stg

T

amb

P

tot

P

O(pin)

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

supply voltage 1 −0.5 +6.5 V
supply voltage 2 −0.5 +6.5 V
input voltage −0.5 +6.5 V
storage temperature −55 +150 °C
operating ambient temperature −40 +85 °C
total power dissipation − 150 mW
output power dissipation per output pin − 100 mW

thermal resistance from junction to ambient in free air 65 K/W

1997 Jun 10 15

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC

SAA4945H

(LIMERIC)

CHARACTERISTICS

V

=5V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

I

DD

T

amb

T

stg

P power dissipation − 350 − mW

CLK

f

CLK

δ duty cycle 40 − 60 %
V

IL

V

IH

C

L

Y

to YI0, UI1, UI2, VI1, VI0, WEI and Va

I7

V

IL

V

IH

I

I

t

su(i)(D)

t

h(D)

Y

to YO0, UO1, UO2, VO1, VO0 and WE

O7

V

OL

V

OH

t

h(Q)

t

d(D)

SNDA and SNCL

f

SNERT

V

IL

V

IH

V

OL

V

OH

TST0, TST1 and TST2

V

IL

V

IH

=25°C; unless otherwise specified.

amb

supply voltage (pins 5, 29 and 30) 4.5 5.0 5.5 V
supply current − 70 − mA
operating ambient temperature 0 − 70 °C
storage temperature −50 − +150 ° C

clock frequency ±7%; note 1 10 16 17.1 MHz

LOW-level input voltage −−0.8 V
HIGH-level input voltage 2 −−V
load capacitance 10 −−pF

LOW-level input voltage −−0.8 V
HIGH-level input voltage 2.0 −−V
input current VI=0to5V −−±20 µA
set-up time 6 −−ns
hold time 7 −−ns

O

LOW-level output voltage IOL= 1.6 mA −−0.4 V
HIGH-level output voltage IOH= 0.4 mA 2.4 −−V
output hold CL=15pF 7 −−ns
output delay CL=15pF −−32 ns

bus clock frequency −−1 MHz
LOW-level input voltage −−0.8 V
HIGH-level input voltage 2.0 −−V
LOW-level output voltage −−0.4 V
HIGH-level output voltage 2.4 −−V

LOW-level input voltage −−0.8 V
HIGH-level input voltage 2.0 −−V

Note

1. Maximum number of clocks per line is 1024.

1997 Jun 10 16

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

22

Z

E

SAA4945H

SOT307-2

e

w M

b

p

pin 1 index

44

1

w M

b

0.25

p

D

H

D

cE

p

0.40

0.25

0.20

10.1

0.14

D

9.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12

11

Z

D

B

v M

0 2.5 5 mm

scale

(1)

(1) (1)(1)

eH

H

D

10.1

9.9

12.9

0.8 1.3

12.3

v M

H

E

E

A

B

LLpQZywv θ

E

12.9

12.3

0.95

0.55

A

2

A

A

1

detail X

0.85

0.75

0.15 0.10.15

Q

(A )

3

θ

L

p

L

Z

E

D

1.2

0.8

1.2

0.8

o

10

o

0

OUTLINE

VERSION

SOT307-2

IEC JEDEC EIAJ

REFERENCES

1997 Jun 10 17

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-02-04

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC
(LIMERIC)

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

“Quality

(order code 9398 510 63011).

SAA4945H

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Jun 10 18

Philips Semiconductors Preliminary specification

LIne MEmory noise Reduction IC

SAA4945H

(LIMERIC)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1997 Jun 10 19

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547047/20/01/pp20 Date of release: 1997 Jun 10 Document order number: 9397 750 01608