Datasheet saa2013 DATASHEETS (Philips)

Download

Page 1

INTEGRATED CIRCUITS

DATA SH EET

SAA2013

Adaptive allocation and scaling for PASC coding in DCC systems

Preliminary speciﬁcation File under Integrated Circuits, IC01

Philips Semiconductors

May 1994

Page 2

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

FEATURES

• Wide operating voltage range: 2.7 to 5.5 V

• Low power consumption: 13 mW; 3.0 V

• Low power decode mode: 1 mW; 5.0 V

• Sleep mode for low power and low Electromagnetic

Interference (EMI)

• Sophisticated allocation algorithm

• Optimum sound quality

• Three-wire L3 bus microcontroller interface

• Stereo or 2-channel mono recording

• Small surface mounted package (QFP; SOT307).

ORDERING INFORMATION

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

SAA2013H 44 QFP

GENERAL DESCRIPTION

The SAA2013 performs the adaptive allocation and scaling function in the Precision Adaptive Sub-band Coding (PASC) system. It is not required in playback only applications, and is only used during recording. To complete the PASC processor, a SAA2003 stereo filter and codec is required.

(1)

SAA2013

PACKAGE

plastic SOT307-2

Note

1. When using reflow soldering it is recommended that the Dry Packing instructions in the

Pocketbook”

are followed. The pocketbook can be ordered using the code 9398 510 34011.

“Quality Reference

May 1994 2

Page 3

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

BLOCK DIAGRAM

handbook, full pagewidth

L3MODEM

L3CLKM

L3DATAM

L3MODEC

L3CLKC

L3DATAC

DD1

14 24 40

3 4

MICROCONTROLLER

9 10 11

DD2

SFC BUS

DD3

BUS

SAA2013

ALLOCATION AND SCALE FACTOR

FS256

CONTROL

AND

SYNC

FRESET

FDIR

COMPUTATION

37 36 35 34

COMPENSATION

DELAY

FSYNC

FDAI

SAA2013

FDCL

FDWS

SLEEP

CLK24

RESET

FDAO

6 25 44

SS1

SS2

SS3

Fig.1 Block diagram.

222120

NODONE RESOL0 RESOL1

MGB355

May 1994 3

Page 4

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

PINNING

SYMBOL PIN DESCRIPTION TYPE

TEST10 1 test input; connect to V TEST11 2 test input; connect to V L3MODEM 3 microcontroller interface mode input I L3CLKM 4 microcontroller interface clock input I L3DATAM 5 microcontroller interface data 3-state input/output I/O V

SS1

6 supply ground − TEST12 7 test output; do not connect O TEST13 8 test output; do not connect O L3MODEC 9 codec interface mode output O L3CLKC 10 codec interface clock output O L3DATAC 11 codec interface data 3-state input/output I/O TEST1 12 test output; do not connect O TEST2 13 test output; do not connect O V

DD1

14 supply voltage − TEST3 15 test mode input; connect to V TEST4 16 test mode input; connect to V TEST5 17 test input; connect to V TEST6 18 test input; connect to V TEST7 19 test input; connect to V NODONE 20 nodone state selection input; connect to V RESOL0 21 resolution selection 0 input I RESOL1 22 resolution selection 1 input I RESET 23 reset input; active HIGH I V V

DD2 SS2

24 supply voltage −

25 supply ground − CLK24 26 24.576 MHz clock input I LOWPWR 27 low power decode select input I POR 28 power on reset input I TEST8 29 test input; connect to V SLEEP 30 sleep mode select input I FDWS 31 ﬁltered data word select I FDCL 32 ﬁltered data clock I FDAO 33 ﬁltered data output O FDAI 34 ﬁltered data input I FSYNC 35 sub-band synchronization on ﬁltered I FRESET 36 reset signal input from SAA2003 I FDIR 37 ﬁltered data direction input I TEST9 38 test input; connect to V FS256 39 system clock input; 256 × sample frequency (f V

DD3

40 supply voltage −

SS SS

SS SS SS

DD DD

S bus I

I I

I I I I I I

May 1994 4

Page 5

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

SYMBOL PIN DESCRIPTION TYPE

n.c. 41 not connected − n.c. 42 not connected − n.c. 43 not connected − V

SS3

handbook, full pagewidth

44 supply ground −

TEST10 TEST11

L3MODEM

L3CLKM

L3DATAM

SS1 TEST12 TEST13

L3MODEC

L3CLKC

L3DATAC

SS3

n.c.

1 2 3 4 5 6 7 8

9 10 11

DD3

n.c.

SAA2013

FS256

TEST9

FDIR 37

FRESET

FSYNC

FDAI 34

33 32 31 30 29 28 27 26 25 24 23

FDAO FDCL FDWS SLEEP TEST8 POR LOWPWR CLK24 V

SS2

DD2

RESET

DD1

TEST1

TEST2

TEST3

TEST4

Fig.2 Pin configuration.

May 1994 5

TEST5

TEST6

TEST7

RESOL0

NODONE

RESOL1

MGB356

Page 6

May 1994 6

FUNCTIONAL DESCRIPTION

coding in DCC systems

RAM

41464

analog

output

analog

input

IEC958

analog CC

L output

analog CC

R output

DAC

TDA1305

SFC3 SAA2003 STEREO

FILTER CODEC

ADAS3

SAA2013

ADAPTIVE

ALLOCATION

baseband

I S

ADC

SAA7366

DIGITAL

AUDIO I/O

TDA1315

filtered I S

AUDIO IN/OUT PASC PROCESSOR

sub-band

I S

BUFFER

64K x 4

DRP

SAA2023

SAA3323

DRIVE

PROCESSOR

search data

TAPE DRIVE PROCESSING

speed control

WRAMP

TDA1381

WRITE AMP.

RDAMP

TDA1380

READ AMP.

FIXED HEAD

CAPSTAN

DRIVE

TAPE

MECHANICS

DRIVERS

detect switch

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

Fig.3 DCC system block diagram.

handbook, full pagewidth

SYSTEM

MICROCONTROLLER

SYSTEM CONTROL

MBD620

SAA2013

Page 7

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

PASC processor

The PASC processor is a dedicated Digital Signal Processor (DSP) engine which efficiently codes digital audio data at a bit rate of 384 kbits/s without affecting the sound quality. This is achieved using an efficient adaptive data notation and by only encoding the audio information which can be heard by the human ear.

The audio data is split into 32 equal sub-bands during encoding. For each of the sub-bands a masking threshold is calculated. The samples from each of the sub-bands are included in the PASC data with an accuracy that is determined by the available bit-pool and by the difference between the signal power and the masking threshold for that sub-band. In decode, the sub-band signals are reconstructed into the full bandwidth audio signal.

The stereo filter codec performs the splitting (encoding) and reconstruction (decoding), including the necessary formatting functions. During encoding, the adaptive allocation and scaling circuit calculates the required accuracy (bit allocation) and scale factors of the sub-band samples.

Decode/encode control

SAA2013

to determine the operation mode. When FDIR is HIGH, SAA2013 is in decode mode. When FDIR is LOW the SAA2013 is in encode mode. See Fig.4.

Reset

When used with low-power mode disabled (LOWPWR = VSS), and with the SLEEP input LOW, SAA2013 is reset if the RESET pin is held HIGH for at least 5 periods of the CLK24 clock, see Fig.5. SAA2013 defaults to decode mode. When in low-power mode, the RESET pin is disabled.

Sleep mode

Sleep mode is entered by taking the SLEEP input HIGH with the LOWPWR pin connected to V FS256 are stopped internally to the SAA2013, the 3-state buffers will have a high impedance, and outputs will freeze in the same state as just before the sleep mode became active (clocks stopped). To come out of sleep mode, the SLEEP input must be taken LOW again. To clear data present from before sleep was entered, this should be followed by a reset, see Fig.5.

; CLK24 and

Selection of decode or encode is controlled using FRESET and FDIR. FRESET causes a general reset. The FDIR signal is sampled at the falling edge of the FRESET signal

handbook, full pagewidth

FRESET

FDIR

Fig.4 FDIR and FRESET timing.

MGB357

May 1994 7

Page 8

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

handbook, full pagewidth

Low-power decode mode

Low-power decode mode is made available by connecting the LOWPWR pin to VDD. With LOWPWR = VDD, low-power decode mode is entered 9 cycles of CLK24 after the SLEEP input is taken HIGH. In low-power decode mode, the L3 bus connections are connected straight trough the SAA2013, which is effectively bypassed. The compensation delay connection between pins FDAI and FDAO is no longer needed by the SAA2003, and CLK24 and FS256 are stopped internally to the SAA2013.

SLEEP

RESET

CLK24

Fig.5 SLEEP and RESET timing.

handbook, halfpage

MGB359

150

SAA2013

MGB358

µ1 F

Ω

POR

To get out of low-power decode mode, it is necessary to take SLEEP LOW, FDIR LOW, and FRESET HIGH (in a normal application taking FDIR LOW and FRESET HIGH can be achieved by setting SAA2003 into encode mode), SAA2013 then performs an internal reset, and defaults to normal decode mode. The RESET pin does not reset the circuit from low-power decode mode.

Power-On Reset (POR)

When low-power decode mode is enabled (LOWPWR = V

), a power-on reset circuit is required to

ensure that the internal clocks are connected correctly at power-on. A suitable circuit is shown in Fig.6. This circuit will correctly reset the internal clock connection provided that the nominal value of the VDD supply is reached within 40 ms at power-on.

May 1994 8

Fig.6 POR circuit.

Encode mode

In encode mode the SAA2013 receives sub-band filtered samples from SAA2003 on the FDAI pin. The SAA2013 has to collect a complete frame of sub-band data before the allocation and scale factor information can be calculated. So that the allocation and scale factor information is available in the same time frame as the audio samples at the output, the sub-band filtered samples are delayed by 480 FDWS periods.

One FDWS period is equal to where f

--- f

is the audio

sample rate of 32, 44.1 or 48 kHz. The delayed samples are passed to the codec part of SAA2003 on the FDAO pin.

Page 9

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

For each sub-band frame, SAA2013 calculates the allocation and scale factor index information required by the SAA2003. In order to synchronize the codec part of SAA2003, SAA2013 frequently requests status information from the codec. It monitors sample frequency, emphasis information and stereo mode, and uses the ready-to-receive bit of the codec to determine when to transfer information.

Decode mode

In decode the SAA2003 will transfer samples from FDAI to FDAO with a delay of 480 FDWS periods. Settings and status information can be sent to SAA2003 via SAA2013, but the SAA2013 does not itself act on this information. Transfer of this information is automatically synchronized to the ready-to-receive bit of SAA2003 by SAA2013.

Filtered data interface

The filtered data interface signals are given in Table 2.

SAA2013

Audio sample resolution section

The SAA2013 is designed for operation with audio input sources of 14, 15, 16 or 18-bit resolution.

For optimum audio performance the bit allocation algorithm of the SAA2013 can be varied to suit the bit resolution of the audio source. This is done with the pins RESOL0 and RESOL1 as shown in Table 1.

Table 1 Resolution set by pins RESOL0 and RESOL1.

RESOLUTION RESOL0 RESOL1

16 bits 0 0 18 bits 0 1 14 bits 1 0 15 bits 1 1

Table 2 Filtered data interface signals.

PIN INPUT/OUTPUT FUNCTION FREQUENCY

FDWS input ﬁltered data interface word select f FDCL input ﬁltered data interface bit clock 64f FDAI input ﬁltered data input − FDAO output ﬁltered data output − FSYNC input ﬁltered data sub-band synchronization −

The filtered data interface transfers sub-band filtered samples between the stereo filter codec SAA2003 and SAA2013. The interface is similar to a normal I2S interface, consisting of clock (FDCL), data (FDAI/FDAO) and word select lines (FDWS), except that the samples sent represent signals divided into 32 sub-bands. One frame of data consists of 12 samples from 32 sub-bands for both left and right channels, i.e.: 768 audio samples. Each audio sub-band sample is represented by a 24-bit two’s complement number.

The order in which the samples are sent is shown in Table 3.

For two channel mono, the order is the same, but with Channel 1 samples in the place of left and Channel 2 samples in place of right.

Table 3 Order of samples.

SUB-BAND 001122...3131

Channel L R L R L R ... L R Sample 000000...00

111111...11

222222...22

...........

11 11 11 11 11 11 ... 11 11

The signal FSYNC is used between each PASC frame to indicate the sending of samples for sub-band 0 (Fig.7).

May 1994 9

Page 10

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

channel

andbook, full pagewidth

FDWS

FDCL

FDWS

FSYNC

sub-band

left

23 22 21 20

1 bit

FDCL

FDAO

FDAI FDWS

31 0 1 31 0

32 bits

su1

SAA2013

right

7 bit

MGB360

FSYNC timing

Fig.7 Filtered interface format.

Control interfaces

Two 3-wire control interfaces are provided (referred to as ‘L3’ interfaces). One is connected to the system microcontroller (L3MODEM, L3CLKM, L3DATAM where ‘M’ represents microcontroller), the other to SAA2003 (L3MODEC, L3CLKC, L3DATAC where ‘C’ represents codec). In general, control data is passed between SAA2003 and the microcontroller via SAA2013. This ensures that the microcontroller is buffered from the time-critical SAA2013 to SAA2003 interface during encode.

The SAA2013 does not interpret the data from the microcontroller interface.

Status information from the codec is interpreted to ensure that SAA2013 quickly acts upon the status of SAA2003.

The L3 bus operation is shown in Fig.8. There are three modes:

1. Address.

2. Data.

3. Halt. Each interface operates as either a master or a slave,

where the master provides L3CLK and L3MODE. For the microcontroller to SAA2013 interface, the microcontroller is the master. For the SAA2013 to SAA2003 interface, SAA2013 is the master.

May 1994 10

Page 11

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

handbook, full pagewidth

L3MODE

L3CLK

L3DATA

01234567

Fig.8 L3 bus operation; address mode.

SAA2013

MGB361

handbook, full pagewidth

L3MODE

L3CLK

L3MODE

L3CLK

L3DATA 01234567

MGB362

Fig.9 L3 single byte transfer.

L3DATA

8 9 10 11 12 13 14 15

Fig.10 L3 bus two byte transfer.

May 1994 11

01 2 34 5 67

MGB363

Page 12

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

ADDRESS MODE Address mode is entered by the master pulling L3MODE

LOW. This causes the L3DATA line to act as an input on the slave, and 8 bits of address data are clocked into the slave. If the slave recognizes the address, it will set-up its internal state based on the 2 Least Significant Bits (LSBs) of the address. The slave than expects to send status data or receive control data.

The addresses for SAA2013 are shown in Table 4.

Table 4 SAA2013 addresses.

MSB LSB

0010 0000 WDAT extended settings 0010 0001 RDAT allocation information 0010 0010 WCMD settings 0010 0011 RSTAT status/peak read

L3 OPERA TION

MODE

FUNCTION

SAA2013

HALT MODE Halt mode consists of pulling L3MODE LOW after sending

data. It is used for marking the end of a data transfer mode which does not have an internal bit counter.

SAA2013 interface modes

The SAA2013 may be used to read and write from or to SAA2003. Information is transferred via a set of transit registers within SAA2013.

ECODE OPERATION

D During decode, the SAA2013 does not perform allocation.

Therefore no allocation and scale factor indices are sent to SAA2003. Settings and extended settings may still be sent to SAA2003, and SAA2013 monitors the status of the codec by reading status from it after every occurrence of FSYNC. Peak level data can also be transferred from SAA2003.

The interface may be reset by sending an address of all zeros (‘00000000’). This may be used to allow inter-operation with other devices sharing the L3CLK and L3DATA lines (e.g. SAA7345 CD decoder).

ATA MODE

In data mode, bytes of data are clocked into (e.g. control) or out of (e.g. status) the slave. A single byte transfer is shown in Fig.9. A two byte transfer is shown in Fig.10, between bytes there must be a pause during which the clock remains HIGH.

NCODE OPERATION

In encode, the same information may be sent as for decode, and in addition, allocation/scale factor indices are sent to the codec by SAA2013.

The interface modes are shown in Table 5.

May 1994 12

Page 13

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

Table 5 Interface modes.

MODE

Decode 0 0 extended settings 8 microcontroller to SAA2003

Encode 0 0 extended settings 8 microcontroller to SAA2003

PRIORITY Each type of transfer has a priority. The priorities are:

1. Allocation/scale/settings (highest priority).

2. Status read.

3. Peak read.

4. Extended settings (lowest priority).

LLOCATION AND SCALE FACTOR TRANSFER

ADDRESS

INTERFACE MODE LENGTH (BITS) DIRECTION

BIT 1 BIT 0

01−−− 1 0 settings 16 microcontroller to SAA2003 1 1 status/peak 16 or 48 SAA2003 to microcontroller

0 1 allocation/scale 48 × 16 SAA2013 to SAA2003 1 0 settings 16 microcontroller to SAA2003 1 1 status/peak 16 or 48 SAA2003 to microcontroller

the transit registers, and sent next time that allocation is being sent. In decode, settings are sent as soon as possible subject to the RTRC flag from SAA2003.

Before sending settings the microcontroller should read the status of SAA2013 to examine the Ready-To-Receive bit Settings (RTRS). After the settings have been received by SAA2013, RTRS will be made logic 0, until the settings have been sent to SAA2003. Only after RTRS is logic 1 again may the microcontroller send new settings.

The allocation and scale factor information sent from SAA2013 to SAA2003 during encode has the highest priority. The other types of transfer interleaved with the allocation/scale information.

ETTINGS TRANSFER

This is a 16-bit transfer. The microcontroller sends settings to SAA2003. SAA2013 only transfers these without taking notice of the contents. In encode, the settings are held in

Table 6 Status bits.

BIT NAME FUNCTION VALID IN

B15 to B12 bit rate index bit rate indication encode/decode B11 and B10 sample frequency indication 44.1, 48, 32 kHz indication encode/decode B9 RTRS (settings) 1 = ready; 0 = not ready encode/decode B8 RTRE (external settings) 1 = ready; 0 = not ready encode/decode B7 and B6 MODE sub-band signal mode

identiﬁcation B5 SYNC synchronization indication encode/decode B4 CLKOK 1 = OK; 0 = not OK encode/decode B3 and B2 Tr0 and Tr1 transparent bits encode/decode B1 and B0 EMPHASIS emphasis indication encode/decode

TATUS READ

S Status and peak information may be read from SAA2003

by the microcontroller. The status bits are defined in Table 6.

encode/decode

May 1994 13

Page 14

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

Since the two bytes of status information are sampled separately, the bytes may result from different sub-band frames.

The only valid bit rate code for the SAA2013 is 1100. The sample frequency indication is shown in Table 7.

Table 7 Sample frequency indication.

BIT 11 BIT 10 SAMPLE FREQUENCY

0 0 44.1 kHz; default 0 1 48.0 kHz 1 0 32.0 kHz 1 1 do not use

Ready-to-receive S or E indicates whether the SAA2013 is ready-to-receive new settings or extended settings from the microcontroller. This should be checked before sending new information.

For details of the MODE, SYNC, CLKOK and transparent bits, refer to the

The emphasis indication can be used to apply the correct de-emphasis. In encode SAA2013 will correct the calculated allocation if50⁄15µs emphasis is applied. When “CCITT J.17” emphasis is applied, the bit allocation remains the same as when no emphasis is applied.

“SAA2003 data sheet”

SAA2013

is possible that peak data may contain an additional delay of 1 column (667 µs minimum at 48 kHz, 1 ms maximum at 32 kHz). If the microcontroller attempts to read peak level data with a delay of less than 1 column, the peak level data from the previous reading will be repeated. Normally the microcontroller should allow at least 1 ms between reads. There is also a delay required between peak data words (Fig.13).

If the SAA2013 does not have peak data available (for instance the microcontroller attempts two reads in very quick succession), it will return all peak data bits set to logic 0. The microcontroller can detect if valid peak data has been returned by inspecting bits T16 and T32. If both bits are set to logic 0 the data is not valid.

handbook, halfpage

MSB LSB

00100011

STATUS MSB

PEAK BYTE 1

PEAK BYTE 3

STATUS LSB

PEAK BYTE 0

PEAK BYTE 2

MGB364

The 2 bytes of the status are ‘sampled’ at different moments. So the information may not result from the same sub-band frame.

When making repeated status reads (for instance reading the RTRS/RTRE flags before sending settings or extended settings), the microcontroller must send an address before each status read, to ensure that the byte counter in the interface is reset to logic 0. If this is not done, then the peak data will be read. Conversely, it is important not to send a new address after a status read if the peak data is required.

EAK READ

Peak information is read by clocking a further 4 bytes of data after a status read. The data format is shown in Figs 11 and 12. Bits B17 to B31 contain a 15-bit unsigned peak, LSB first, channel indicated by bit B16. Bits B33 to B47 contain a 15-bit unsigned peak, channel indicated by bit B32.

The peak data is delayed by 1 read period. If for example the microcontroller reads peak level data every 50 ms, the peak data sourced by SAA2013 will be 50 ms old. Also it

Fig.11 Peak level read format; SAA2013 to

microcontroller.

handbook, halfpage

channel

indicator

bits 17 to 31

LSB

15-bit peak

bits 33 to 47

MSB

channel

indicator

LSB

15-bit peak

Fig.12 Peak level format.

MSB

MGB365

May 1994 14

Page 15

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

PEAK 1

15.625 s

HALT

PEAK 2

MGB366

handbook, full pagewidth

L3MODEC

STATUS

BYTES

Fig.13 Peak data timing.

EXTENDED SETTINGS This is a single byte transfer, valid during decode and encode. The sequence of operations is:

1. Microcontroller reads status from SAA2013, waiting for the flag RTRE to be set.

2. When RTRE is logic 1, the microcontroller writes address bit 0 is logic 0, bit 1 is logic 0.

3. One byte of extended settings is clocked into the transit register (SAA2013).

4. When it is possible (i.e. subject to RTRC being HIGH, and assuming that allocation or status is not waiting), the byte is transferred from the transit register to the SAA2003.

handbook, full pagewidth

L3MODEC

L3CLKC

L3DATAC (ADAS-SFC)

Fig.14 L3 interface timing; SAA2013 to SAA2003 (address mode).

MGB367

May 1994 15

Page 16

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

andbook, full pagewidth

L3MODEC

L3CLKC

L3DATAC SFC-ADAS)

L3DATAC (ADAS-SFC)

su1

SAA2013

MGB368

handbook, full pagewidth

L3MODEM

L3CLKM

L3DATAM (microcontrollerADAS)

Fig.15 L3 interface timing; SAA2013 to SAA2003 (data mode).

su1

MGB369

Fig.16 L3 interface timing; microcontroller to SAA2013 (address mode).

May 1994 16

Page 17

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

handbook, full pagewidth

L3MODEM

L3CLKCM

L3DATAM (microcontrollerADAS)

L3DATAM (ADASmicrocontroller)

su1

SAA2013

MGB370

handbook, full pagewidth

Fig.17 L3 interface timing; microcontroller to SAA2013 (data mode).

L3MODEM/ L3MODEC

L3CLKM/ L3CLKC

L3DATA/ L3DATAC (OUTPUT)

MGB371

Fig.18 L3 interface timing; microcontroller to SAA2013 and SAA2013 to SAA2003 (halt mode).

May 1994 17

Page 18

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

handbook, full pagewidth

CLK24

SAA2013

c24

MGB372

handbook, full pagewidth

CLK24

DATA

Fig.19 Input timing CLK24.

t , t

MGB373

Fig.20 Input signal timing for FSYNC, FRESET, FDIR, FDWS, L3MODEM, L3CLKM, L3DATAM and L3DATAC.

May 1994 18

Page 19

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

handbook, full pagewidth

FS256

FDAO

SAA2013

MGB374

handbook, full pagewidth

FDCL

FDAO (FDAI)

FDAI, FDWS

Fig.21 Output signal timing FDAO.

su1

MGB375

Fig.22 Filtered data interface timing.

May 1994 19

Page 20

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

Current consumption

The typical current consumption is shown in Fig.23.

MBD697

V (V)

handbook, halfpage

(mA)

234 6

SAA2013

=25°C.

amb

Fig.23 Typical current consumption.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

stg

amb

supply voltage −0.5 +6.5 V input voltage −0.5 VDD + 0.5 V input current − 20 mA output voltage −0.5 +6.5 V output current − 20 mA storage temperature −65 +150 °C operating ambient temperature −40 +85 °C electrostatic handling

Human Body Model (HBM) note 1 −2000 +2000 V Machine Model (MM) note 2 −200 +200 V

Notes

1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

2. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

May 1994 20

Page 21

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

CHARACTERISTICS

= 2.7 to 5.5 V; VSS = 0 V;T

< 4.5 V.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

stb

supply voltage 2.7 5.0 5.5 V supply current VDD= 3.0 V 4 5 6 mA

standby current VDD= 5.0 V −−400 µA

Inputs

LOW level input voltage 0 − 0.3V HIGH level input voltage 0.7V input leakage current VI=0toV input capacitance −−10 pF

Outputs

LOW level output voltage IOL= 4 mA 0 − 0.4 V HIGH level output voltage IOH= −4mA VDD− 0.4 − V load capacitance −−30 pF

Inputs/outputs

LOW level input voltage 0 − 0.3V HIGH level input voltage 0.7V 3-state leakage current VI=0toV input capacitance −−10 pF LOW level output voltage IOL= 4 mA 0 − 0.4 V HIGH level output voltage IOH= −4mA VDD− 0.4 − V load capacitance −−30 pF

Clock input CLK24

input frequency see Fig.19 − 24.576 − MHz rise time −−7ns fall time −−7ns HIGH time 10 −− ns LOW time 10 −− ns

Clock input FS256

input frequency fs=48kHz − 12.288 − MHz

rise time −−7ns fall time −−7ns HIGH time 35 −− ns LOW time 35 −− ns

= −40 to 85 °C; unless otherwise speciﬁed; IOL and IOH derated by 75% for

amb

= 5.0 V 7 10 12 mA

= 44.1 kHz − 11.2896 − MHz

=32kHz − 8.192 − MHz

−10 − +10 µA

− V

V V

May 1994 21

Page 22

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Inputs FSYNC, FRESET, FDIR, FDWS, L3MODEM, L3CLKM, L3DATAM and L3DATAC; referenced to CLK24 rising edge; see Fig.20; SLEEP = RESET = POR = logic 0

Inputs FDAI, FDCL, FDWS, FRESET and FDIR; referenced to FS256 rising edge; SLEEP = RESET = POR = logic 0

Output FDAO; referenced to FS256 rising edge; see Fig.21; SLEEP = RESET = POR = logic 0

set-up time 15 −− ns hold time 20 −− ns rise time −−200 ns fall time −−200 ns

hold time CL= 7.5 pF 0 −− ns delay time CL=30pF −−30 ns output delay time after FDCL

see Fig.22 2T

c256

− 10

(1)

−− ns

HIGH output delay time after FDCL

see Fig.22 −−3T

c256

+60

(1)

HIGH

Input FDCL; see Fig.22

FDCL period 280 4T FDCL HIGH time T FDCL LOW time T

Inputs FDAI and FDWS; see Fig.22

t t

su1 h1

set-up time before FDCL HIGH 3T hold time after FDCL HIGH T

Input FRESET; see Fig.4

FRESET HIGH time 1280 −− ns FDIR set-up time before

FRESET LOW

FDIR hold time after FRESET LOW

SLEEP and RESET timing; see Fig.5; LOWPWR = logic 1

RESET hold time after SLEEP LOW

CLK24 disable after SLEEP HIGH

(1)

− ns

c256 c256

c256

+35 +35

+60

+20

c256

(1)

−− ns

(1)

−− ns

(1)

−− ns

(1)

−− ns

0 210 − ns

(2)

c24

(2)

370 − ns

210 − ns

370 − ns

May 1994 22

Page 23

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

L3 interface timing; microcontroller to SAA2013

ADDRESS MODE; SEE FIG.16 t

L3MODEM LOW to L3CLKM

LOW t t t

cH cL su1

L3CLKM HIGH time 250 −− ns

L3CLKM LOW time 250 −− ns

L3DATAM input set-up time

before L3CLKM HIGH t

L3DATAM input hold time

after L3CLKM HIGH t

L3CLKM HIGH before

L3MODEM HIGH DATA MODE; SEE FIG.17 t

L3MODEM HIGH to L3CLKM

LOW delay time t t t

cH cL su1

L3CLKM HIGH time 250 −− ns

L3CLKM LOW time 250 −− ns

L3DATAM input set-up time

before L3CLKM HIGH t

L3DATAM input hold time

after L3CLKM HIGH t

L3CLKM HIGH before

L3MODEM LOW t

L3MODEM HIGH to L3DA T AM

output valid t

L3DATAM output hold time

after L3CLKM HIGH t

L3CLKM HIGH to L3DATAM

output valid delay time

L3MODEM HIGH to L3DA T AM

output enabled delay time t

L3MODEM LOW to L3DATAM

output disabled delay time

between bits 7 and 8; no halt mode used

190 −− ns

30 −− ns

190 −− ns

30 −− ns

190 −− ns

−−380 ns

120 −− ns

−−360 ns

−−530 ns

0 − 50 ns

May 1994 23

Page 24

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

HALT MODE; SEE FIG.18 t

L3 interface timing; SAA2013 to SAA2003

DDRESS MODE; SEE FIG.14

L3MODEM LOW time 190 −− ns

L3MODEM HIGH to L3CLKM

190 −− ns

HIGH delay time

L3CLKM HIGH before

190 −− ns

L3MODEM LOW

L3MODEM HIGH to L3DA T AM

0 − 50 ns

output enabled delay time

L3MODEM LOW to L3DATAM

0 − 50 ns

output disabled delay time

L3MODEC LOW to L3CLKC

190 −− ns

LOW delay time

L3CLKC HIGH time 210 −− ns

L3CLKC LOW time 210 −− ns

L3CLKC HIGH time before

190 −− ns

L3MODEC HIGH

L3MODEC LOW to L3DATAC

−−380 ns

output valid delay time

L3DATAC output hold time

120 −− ns

after L3CLKC HIGH

L3CLKC HIGH to L3DATAC

−−360 ns

output valid delay time

L3MODEC LOW to L3DATAC

0 − 50 ns

output enabled delay time

L3MODEC HIGH to L3DATAC

0 − 50 ns

output disabled delay time

May 1994 24

Page 25

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ATA MODE; SEE FIG.15

D t

L3MODEC HIGH to L3CLKC

LOW t t t

cH cL su1

L3CLKC HIGH time 210 −− ns

L3CLKC LOW time 210 −− ns

L3DATAC input set-up time

before L3CLKC HIGH t

L3DA TAC input hold time after

L3CLKC HIGH t

L3CLKC HIGH time before

L3MODEC LOW t

L3MODEC HIGH to L3DATAC

output valid t

L3DATAC output hold time

after L3CLKC HIGH t

L3CLKC HIGH to L3DATAC

output valid

ALT MODE; SEE FIG.18

L3MODEC LOW time 190 −− ns

L3MODEC HIGH to L3CLKC

HIGH delay time t

L3CLKC HIGH time before

L3MODEC LOW

between bits 7 and 8; no halt mode used

190 −− ns

100 −− ns

30 −− ns

190 −− ns

−−380 ns

120 −− ns

−−360 ns

−−530 ns

190 −− ns

L3 interface delays in bypassed mode; LOWPWR = logic 1

pd1

propagation delay from

L3MODEM to L3MODEC;

L3DATAM to L3DATAC;

L3CLKM to L3CLKC t

pd2

propagation delay from

L3DATAM to L3DATAC;

L3CLKM to L3CLKC t

pd3

propagation delay from

L3DATAM to L3DATAC;

L3MODEM to L3MODEC

Notes

1. T

2. T

is a clock period of FS256.

c256

is a clock period of CLK24.

c24

May 1994 25

−−35 ns

−20 − +4 ns

Page 26

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

PACKAGE OUTLINE

handbook, full pagewidth

seating

plane

pin 1 index

0.1 S

12.9

12.3

SAA2013

1.2 (4x)

0.8

10.1

9.9

12.9

12.3

0.95

0.55

0.85

0.75

0.25

0.14

0 to 10

2.10

1.70

0.15 M

0.8

0.40

0.20

0.15 M A

10.1

9.9

1.85

1.65

MBB944 - 2

0.25

0.05

1.2

0.8

0.40

0.20

(4x)

detail X

Dimensions in mm.

Fig.24 Plastic quad flat-pack, 44-pin (short) (QFP44SL).

May 1994 26

Page 27

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

SOLDERING Plastic quad ﬂat-packs

YWAVE

B During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications.

SAA2013

applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

IRON OR PULSE

Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.)

-HEATED SOLDER TOOL)

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be

For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.

May 1994 27

Page 28

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC

SAA2013

coding in DCC systems

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.

May 1994 28

Page 29

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

NOTES

SAA2013

May 1994 29

Page 30

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

NOTES

SAA2013

May 1994 30

Page 31

Philips Semiconductors Preliminary speciﬁcation

Adaptive allocation and scaling for PASC coding in DCC systems

NOTES

SAA2013

May 1994 31

Page 32

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. (02)805 4455, Fax. (02)805 4466

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. (01)60 101-1236, Fax. (01)60 101-1211

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. (31)40 783 749, Fax. (31)40 788 399

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2327, Fax. (011)829-1849

Canada: INTEGRATED CIRCUITS:

Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave, SCARBOROUGH, ONTARIO, M1B 1M8, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. (02)773 816, Fax. (02)777 6730

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. (032)88 2636, Fax. (031)57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. (9)0-50261, Fax. (9)0-520971

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427

Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H.,

P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213.

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. (01)4894 339/4894 911, Fax. (01)4814 240

Hong Kong: PHILIPS HONG KONG Ltd., Components Div.,

6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729

India: Philips INDIA Ltd, Components Dept,

Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. (01)640 000, Fax. (01)640 200

Italy: PHILIPS COMPONENTS S.r.l.,

Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.3302, Fax. (02)6752 3300.

Japan: Philips Bldg13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. (03)3740 5028, Fax. (03)3740 0580

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880

Mexico: Philips Components, 5900 Gateway East, Suite 200,

EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. (040)783749, Fax. (040)788399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. (09)849-4160, Fax. (09)849-7811

floor, Suite 51,

Norway: Box 1, Manglerud 0612, OSLO,

Tel. (022)74 8000, Fax. (022)74 8341

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546.

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)14163160/4163333, Fax. (01)14163174/4163366.

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. (65)350 2000, Fax. (65)251 6500

South Africa: S.A. PHILIPS Pty Ltd., Components Division,

195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494.

Spain: Balmes 22, 08007 BARCELONA,

Tel. (03)301 6312, Fax. (03)301 42 43

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. (0)8-632 2000, Fax. (0)8-632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. (01)488 2211, Fax. (01)481 77 30

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382.

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319.

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. (0212)279 2770, Fax. (0212)269 3094

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,

P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. (02)70-4044, Fax. (02)92 0601

For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

513061/1500/01/pp32 Date of release: May 1994 Document order number: 9397 731 90011

Philips Semiconductors