Datasheet SA25C020LEMNFX, SA25C020LEMNX, SA25C020LEN, SA25C020LENF, SA25C020LENFX Datasheet (SAIFUN)

Features

•= Saifun NROM™ Cell

•= Serial Peripheral Interface (SPI) Compatible,

Supports SPI Modes 0 (0,0) and 3 (1,1)

•= Byte and Page Write Operation:

– 1024 pages (256 Bytes/Page)
– Single Byte or Page Write Cycle in 10ms Typical

•= Single Supply Voltage: 2.7V to 3.6V

•= 25MHz Clock Rate

•= Block Write Protection: Protect Quarter, Half or Entire Array

•= Write Protect Pin and Write Disable Instructions of Both

Hardware and Software Data Protection

•= 100,000 Erase Cycles (Minimum)

•= More than 20-Year Data Retention

•= Low-power Standby Current (less than 1µA)

•= 8-SOIC Narrow Package

•= MLF Leadless Package

•= Temperature Range:

– Industrial: -40°C to +85°C
– Commercial: 0°C to +70°C

SA25C020

Advanced

Information

2Mb EEPROM with

25MHz SPI Bus

Interface

http://www.saifun.com

Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.

This Data Sheet states Saifun's current technical specifications regarding the Products described herei n. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 1911 Rev: 0 Amendment: 0
Issue Date: 20 July 2003

SA25C020 Advanced Information

SAIFUN

2

General Description

The SA25C020 is a 2Mb (512K X 4) CMOS
non-volatile serial EEPROM. This device
fully conforms to the SPI 4-wire protocol, is
enabled through the Chip Select (CSb) pin,
and uses Clock (SCK), Data-in (SI) and
Data-out (SO) pins to synchronously control
data transfer between the SPI
microcontroller and the Serial EEPROM.

The memory can be written from 1 up to
256 bytes at a time via the Byte / Page
Write (PW) instruction.

The memory consists of 1024 pages or
262,144 bytes.

Each device requires only a 3.0V power
supply (2.7 V to 3.6 V) for both read and
write functions. Internally generated and
regulated voltages are provided for the
program and erase operations. The
SA25C020 does not require a V

The HOLDb pin may be used to suspend
any serial communication without resetting
the serial sequence. In addition, the serial
interface allows a minimal-pin-count
packaging designed to simplify PC board
layout requirements and offers the designer
a variety of low-voltage and low-power
options.

supply.

PP

The SA25C020 is available in a
space-saving, 8-lead narrow SOIC package

The SA25C020 is part of the SPI EEPROM
family. It is designed to work with any SPI­compatible, high-speed microcontroller, and
offers both hardware (WPb pin) and
Software (“block protect”) data protection.
For example, programming a 2-bit code into
the status register prevents program with
top ¼, top ½ or entire array write protection
and enables block write protection.
Separate program enable and program
disable instructions are provided for
additional data protection. Hardware data
protection is provided via the WPb pin to
protect against inadvertent write attempts to
the status register.

Saifun’s SPI Serial EEPROM products are
designed and tested for applications
requiring high endurance and low power
consumption for a continuously reliable
non-volatile solution for all markets.

SA25C020 Advanced Information

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3

Table of Contents

Features........................................................................... 1

General Description ........................................................ 2

Memory Organization...................................................... 5

Connection Diagrams..................................................... 6

Ordering Information ...................................................... 7

Product Specifications ................................................... 8

Absolute Maximum Ratings....................................... 8

ESD/Latch Up Specification (JEDEC 8 Spec) ........... 8

Operating Conditions................................................. 8

DC Characteristics .......................................................... 9

AC Test Conditions ....................................................... 10

Timing Diagrams........................................................... 11

Signal Description......................................................... 13

Chip Select (CSb).................................................... 13

Serial Clock (SCK) .................................................. 13

Serial Input (SI) ....................................................... 13

Serial Output (SO)................................................... 13

Hold (HOLDb).......................................................... 13

Write Protect (WPb) ................................................ 13

Serial Interface Description.......................................... 14

SPI Modes............................................................... 14

Master ............................................................. 14

Slave ............................................................... 14

Transmitter/Receiver ....................................... 14

Serial Opcode.................................................. 14

Invalid Opcode ................................................ 14

Chip Select (CSb)............................................ 15

Hold Condition................................................. 15

Write Protect ................................................... 16

Functional Description ................................................. 17

Instructions.............................................................. 17

Read Status Register (RDSR)................................. 18

Write Enable (WREN) ............................................. 20

Write Disable (WRDI).............................................. 20

Write Status Register (WRSR)................................ 21

Read Data Bytes (READ)........................................ 23

Byte or Page Write (PW) ......................................... 24

Read Electronic Signature (Read_Id) ...................... 26

Powerup and Powerdown........................................ 27

Physical Dimensions..................................................... 28

Contact Information ...................................................... 31

Life Support Policy........................................................ 31

SA25C020 Advanced Information

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4

List of Figures

Figure 1. SA25C020 Block Diagram................................ 5

Figure 2. SOIC 8 (150 mil)/PDIP/MLF Package

(Top View)............................................................. 6

Figure 3. SA25C020 Ordering Information ...................... 7

Figure 4. SPI Mode 0 (0,0) Input Timing........................ 11

Figure 5. SPI Mode 0 (0,0) Output Timing..................... 11

Figure 6. AC Measurements I/O Waveform................... 12

Figure 7. Supported SPI Modes .................................... 14

Figure 8. Hold Condition................................................ 15

Figure 9. SPI Serial Interface ........................................ 17

Figure 10. Read Status Register (RDSR) Instruction

Sequence ............................................................ 19

Figure 11. Write Enable (WREN) Instruction Sequence 20

Figure 12. Write Disable (WRDI) Instruction Sequence. 20

Figure 13. Write Status Register (WRSR) Instruction

Sequence ............................................................ 22

Figure 14. Read (READ) Instruction Sequence ............. 23

Figure 16. Read Electronic Signature (Read Id) Instruction

Sequence ............................................................ 26

Figure 17. 8-pin SOIC Package..................................... 28

Figure 18. 8-pin MLF Leadless Package ....................... 29

Figure 19. Molded Dual-in-line Package (N) Package

Number N08E...................................................... 30

List of Tables

Table 1. Pin Names......................................................... 6

Table 2. DC Characteristics............................................. 9

Table 3. AC Test Conditions.......................................... 10

Table 4. AC Measurements........................................... 12

Table 5. Instruction Set ................................................. 17

Table 6. Status Register Format.................................... 17

Table 7. Read Status Register Definition....................... 18

Table 8. Block Write Protect Bits................................... 21

Table 9. WPBEN Operation .......................................... 21

Table 10. Powerup ........................................................ 27

Figure 15. Byte or Page Write (PW) Instruction

Sequence ............................................................ 25

SA25C020 Advanced Information

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5

Memory Organization

The memory is organized in the following
manner:

•= 262,144 bytes (8 bits each)

•= 1024 pages (256 bytes each)

Array - L

Logic

Each byte or page can be individually
written with the bits programmed from
1 to 0 and from 0 to 1.

PSSRAM

X
D
E
C

Array - R

DATA PATHRD

IO

SI

CSb

SCK

SO

Vcc

GND

Figure 1. SA25C020 Block Diagram

WPb

HOLDb

SA25C020 Advanced Information

SAIFUN

Connection Diagrams

6

CSb

SO

WPb

GND

1

2

SA25C020

3

4

VCC

8

HOLDb

7

SCK

6

SI

5

Figure 2. SOIC 8 (150 mil)/PDIP/MLF Package (Top View)

Table 1. Pin Names

Pin Name Signal Name

CSb Chip Select

SCK Serial Data Clock

SI Serial Data Input

SO Serial Data Output

GND Ground

VCC Power Supply

WPb Write Protect

HOLDb Suspend Serial Input

SA25C020 Advanced Information

SAIFUN

Ordering Information

7

FPPELXXC25SA Letter

Volt ag e Op er at in g

X

Package

Temp. Range

Range

Density

Interface

Blank
X

Blank
F

N
MN
MLF

Blank
E

L

020

C

25

SA

Description

Tube
Tape and Reel

Non Lead Fr ee
Lead Fr ee

8-pi n D IP
8-pi n SOIC ( 150 mil )
8-lead M LF

0 to 70 C

-40 to +85 C

2.7 V to 3.6 V

2 Mb with Wri te Pr otect

CMOS

SPI-2 Wir es

Saifun Non-Volatile
Memory

o

o

Figure 3. SA25C020 Ordering Information

SA25C020 Advanced Information

SAIFUN

Product Specifications

Absolute Maximum Ratings

8

Storage Temperature

All input or output voltages with
respect to Ground

Lead Temperature
(Soldering, 10 seconds)

-65 °C to +150 °C

4.5 V to -0.3 V

+235 °C

ESD/Latch Up Specification (JEDEC 8 Spec)

Human Body Model Minimum 4 KV

Machine Model Minimum 500 V

Charge Device Model Minimum 1 KV

Latch Up

100 mA on all pins +125°C

Operating Conditions

Operating Temperature:
SA25C020
SA25C020 E

Positive Power Supply:
SA25C020

0 °C to +70 °C

-40 °C to +85 °C

2.7 V to 3.6 V

SA25C020 Advanced Information

SAIFUN

DC Characteristics

Applicable over recommended operating range from TAI = -40 ºC to 85 ºC, VCC = 2.7-3.6 V.

Table 2. DC Characteristics

9

Symbol Parameter Test Conditions

Limits

Min Typ* Max

VCC Supply Voltage 2.7 3 3.6

Active Power Supply

I

CC1

Current (Read)

Active Power Supply

I

CC2

Current (Page Write)

Active Power Supply

I

CC3

Current (WRSR)

ISB Standby Current

IIL Input Leakage Current V

IOL Output Leakage Current V

SCK = 0.1VCC/0.9 VCC @
25 MHz

9 12

CSb = VCC 15 mA

CSb = VCC 15 mA

= 3.6 V,

V

CC

CSb = V

IN

IN

CC

= GND to VCC 1

= GND to VCC 1

1

VIL Input Low Voltage -0.3 0.3 VCC

VIH Input High Voltage 0.7 V

VOH Output High Voltage IOH = -0.1 mA

VCC -

0.2

CC

VCC +

0.5

Unit

V

mA

µA

µA
µA

V

V

V

VOL Output Low Voltage IOL = 1.6 mA; VCC = 2.7 V 0.4

*Typical values are at TAI = 25 ºC and 3 V.

V

SA25C020 Advanced Information

SAIFUN

AC Test Conditions

Table 3. AC Test Conditions

10

Symbol Parameter

F

SCK Clock Frequency D.C. 25 MHz

SCK

t

t

t

t

CRT

CFT

WH

WL

Clock Rise Time (Slew Rate) 0.1

Clock Fall Time (Slew Rate) 0.1

SCK High Time 18

SCK Low Time 18 ns

Min Typ Max

tCS CSb High Time 100 ns

**

t

t

t

t

CSS

CSH

HD

CD

**

**

CSb Setup Time 10 ns

**

CSb HOLD Time 10 ns

HOLDb Setup Time 10 ns

HOLDb Hold Time 10 ns

tV Output Valid 0 15 ns

tHO Output Hold Time 0 ns

t

Data in Hold Time 5 ns

HD:DAT

t

Data in Setup Time 5 ns

SU:DAT

**

t

t

t

DIS

t

WPS

t

WPH

LZ

HZ

HOLDb to Output Low Z 15 ns

**

HOLDb to Output High Z 20 ns

**

Output Disable Time 15 ns

**

Write Protect Setup Time 20 ns

**

Write Protect Hold Time 100 ns

tPW* Byte or Page Write 10 15 ms

t

Release SP Mode 1000 ns

RES

Endurance 100K Erase cycles

* 256 bytes in the checkerboard programming formation.

** Value guaranteed by characterization, not 100% tested in production

25 MHz

Unit

V/ns

V/ns

ns

SA25C020 Advanced Information

SAIFUN

Timing Diagrams

All timing diagrams are based on SPI protocol modes 0 and 1.

t

CS

CS

SCK

t

CSH

t

CSS

t

SU:DATtHD:DAT

t

CRT

t

CFT

t

CSH

t

CSS

11

SI

SO

CS

SCK

SO

MSB IN

LSB IN

High Impedance

Figure 4. SPI Mode 0 (0,0) Input Timing

t

WH

t

V

t

HO

t

V

t

HO

t

WL

t

DIS

LSB OUT

Figure 5. SPI Mode 0 (0,0) Output Timing

SA25C020 Advanced Information

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12

Input Levels

0.8Vcc

0.2Vcc

Input and Output

Timing Reference Levels

0.7Vcc

0.3Vcc

Figure 6. AC Measurements I/O Waveform

Table 4. AC Measurements

Symbol Parameter Min Max Unit

C

L

Load Capacitance 30 PF

Input Rise and Fall Times 5 ns

Input Pulse Voltage 0.2 VCC to 0.8 VCC V

Input and Output Timing
Reference Voltages

0.3 VCC to 0.7 VCC V

SA25C020 Advanced Information

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Signal Description

Chip Select (CSb)

This is an active-low input pin to the device
that is generated by the master controlling
the device. A low level on this pin selects
the device, while a high level deselects the
device. All serial communications with the
device are enabled only when this pin is
held low.

Serial Clock (SCK)

This is an input pin to the device that is
generated by the master controlling the
device. It is a clock signal that
synchronizes the communication between
a master and the device. All input
information (SI) to the device is latched on
the rising edge of this clock input, while
output data (SO) from the device is driven
after the falling edge of this clock input.

Serial Output (SO)

This is an output pin from the device that is
used to transfer output data to the
controlling master. Output data is serially
shifted out on this pin after the falling edge
of the SCK.

Hold (HOLDb)

This is an active low input pin to the device
that is generated by the master controlling
the device. When driven low, this pin
suspends any current communication with
the device. The suspended communication
can be resumed by driving this pin high.
This feature eliminates the need to
re-transmit the entire sequence by
enabling the master to resume the
communication from where it was left off.
This pin should be tied high if this feature is
not used. Refer to Hold Condition,
page 15, for additional details.

Serial Input (SI)

This is an input pin to the device that is
generated by the master controlling the
device. The master transfers input
information (instruction, addresses and the
data to be programmed) into the device
serially via this pin. This input information is
latched on the rising edge of the SCK.

Write Protect (WPb)

This is an active low input pin to the device.
This pin allows enabling and disabling of
writes to the device's memory array and
status register. When this pin is held low,
writes to the memory array and status
register are disabled; when it is held high,
they are enabled. Refer to Write Protect,
page 16, for additional details.

SA25C020 Advanced Information

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Serial Interface Description

SPI Modes

These devices can be driven by a
microcontroller with its SPI peripheral
running in either of the two following
modes:

•= CPOL=0, CPHA=0

•= CPOL=1, CPHA=1

CPOL CPHA

CS

0

1

0

CS

1

SO

SI

MSB

In both of these modes, input data is
latched on the rising edge of SCK, and
output data is available from the falling
edge of SCK. The difference between the
two modes, as shown in Figure 7, is the
clock polarity when the bus master is in
Standby mode and is not transferring data,
as follows:

•= SCK remains at 0 for CPOL = 0,

CPHA = 0

•= SCK remains at 1 for CPOL = 1,

CPHA = 1

MSB

Figure 7. Supported SPI Modes

Master

The device that generates the SCK.

Slave

As the SCK pin is always an input, the
SA25C020 always operates as a slave.

Transmitter/Receiver

The SA25C020 has separate pins
designated for data transmission and
reception.

Serial Opcode

The first byte is received after the device is
selected. This byte contains the opcode
that defines the operation to be performed
(for more details, refer to Table 5,
page 17).

Invalid Opcode

If an invalid opcode is received, no data is
shifted into the SA25C020, and the serial
output pin remains in a high impedance
state until a CSb falling edge is detected
again, which reinitializes the serial
communication.

SA25C020 Advanced Information

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15

Chip Select (CSb)

The SA25C020 is selected when the CSb
pin is low. When the device is not selected,
data is not accepted via the SI pin, and the
SO pin remains in a high impedance state.

Hold Condition

The HOLDb pin is used in conjunction with
the CSb pin to select the SA25C020. When
the device is selected and a serial
sequence is underway, HOLDb can be
used to pause the serial communication
with the master device without resetting the
serial sequence.

To enter the hold condition the device must
be selected, with CSb low.

As shown in Figure 8, the Hold condition
starts on the falling edge of the HOLDb
signal, provided that SCK is low. The Hold
condition ends on the rising edge of the
HOLDb signal, provided that SCK is low. If
the falling edge does not coincide with SCK
being low, the Hold condition starts only
after SCK next goes low.

Similarly, if the

rising edge does not coincide with SCK
being low, the Hold condition ends only
after SCK next goes low.

During the Hold condition, SO is high
impedance, and SI and SCK are Don’t
Care. In most cases, the device is kept
selected, with CSb driven low, for the entire
duration of the Hold condition, which
ensures that the internal logic state
remains unchanged from the moment it
enters the Hold condition.

NOTE:

Driving CSb high while HOLDb is still
low is not a legal operation.

SCK

HOLD

Hold

Condition

(Standard Use)

Figure 8. Hold Condition

Hold

Condition

(Non-Standard Use)

SA25C020 Advanced Information

SAIFUN

Write Protect

The WPb pin enables write operations to
the status register when held high. When
the WPb pin is brought low and the
WPBEN bit is 1, all write operations to the
status register are inhibited (for more
details, refer to Table 9, page 21). If WPb
goes low while CSb is still low, the write to
the status register is interrupted. If the
internal write cycle has already been
initiated, WPb going low has no effect on
any write operations to the status register.
The WPb pin function is blocked when the
WPBEN bit in the status register is 0,
which enables the user to install the
SA25C020 in a system with the WPb pin
tied to ground but still able to write to the
status register. All WPb pin functions are
enabled when the WPBEN bit is set to 1.

16

SA25C020 Advanced Information

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17

Functional Description

Instructions

Figure 9 presents a schematic diagram of
the SA25C020 's SPI serial interface.

MASTER:

MICROCONTROLLER

DATA OUT

DATA IN

SERIAL CLOCK

SSO

SS1

SS2

SS3

Figure 9. SPI Serial Interface

SLAVE

SA25C020

SI

SO

SCK

CSb

SI

SO

SCK

CSb

SI

SO

SCK

CSb

SI

SO

SCK

CSb

The SA25C020 's SPI consists of an 8-bit
instruction register that decodes a specific
instruction to be executed. Thirteen
different instructions (called opcodes) are
incorporated in the device for various
operations. Table 5 lists the instruction set
and the format for proper operation. All
opcodes, array addresses and data are
transferred in an MSB-first-LSB-last
fashion. Detailed information about each of
these opcodes is provided for the individual
instruction descriptions in the sections that
follow.

Table 5. Instruction Set

Instruction

Name

WREN 0000 0110

WRDI 0000 0100

RDSR 0000 0101

WRSR 0000 0001

READ 0000 0011

Byte or Page

Write

READ_ID

Instruction

Format

0000 0010

1010 1011

+3 dummy bytes

Operation

Set Write Enable
Latch

Reset Write Enable
Latch

Read Status
Register

Write Status
Register

Read Data from
Memory Array

Write Data to
Memory Array

Read ID

In addition to the instruction register, the
device also contains an 8-bit status register
that can be accessed by RDSR and WRSR
instructions. The byte defines the Block
Write Protection (BP1 and BP0) levels,
Write Enable (WEN) status, Busy/Rdy
(/RDY) status and Hardware Write Protect
(WPBEN) status of the device. Table 6
illustrates the format of the status register.

Table 6. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0

WPBEN X X X BP1 BP0 WEN /RDY

SA25C020 Advanced Information

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18

Read Status Register (RDSR)

The RDSR instruction provides read
access to the status register. The
BUSY/RDY and WREN statuses of the
device can also be determined by this
instruction. In addition, the Block Write
Protection bits indicate the extent of
protection employed. In order to determine
the status of the device, the value of the
/RDY bit can be continuously polled before
sending any write instruction.

Table 7. Read Status Register Definition

Bit Definition

Bit 0 = 0 (/RDY) indicates that the

Bit 0 (/RDY)

Bit 1 (WEN)

Bit 2 (BP0) Block Write Protect Bit 0

Bit 3 (BP1) Block Write Protect Bit 1

Bit 7

(WPBEN)

device is READY.
Bit 0 = 1 indicates that a write
cycle is in progress.

Bit 1 = 0 indicates that the device
is not write enabled.
Bit 1 = 1 indicates that the device
is write enabled.

Write Protect Mode Enable Bit

Bit 7 (WPBEN) is Hardware Write Protect
mode. If this bit is a 1, this mode is enabled
and the status register is write protected.

Bits 6 through 4 are always 0.

Bit 3 (BP1) and Bit 2 (BP0) together
indicate a Block Write Protection previously
sent to the device.

Bits 0 and 1 are 1 during an internal write
cycle.

Bit 1 (WEN) indicates the Write Enable
status of the device. This bit is read by
executing an RDSR instruction. If this bit is
1, the device is write enabled; if it is 0, it is
write disabled.

Bit 0 (/RDY) indicates the Busy/Ready
status of the device. This bit is a read-only
bit and is read by executing an RDSR
instruction. If this bit is 1, the device is busy
doing a Program or Erase cycle; if it is 0,
the device is ready.

SA25C020 Advanced Information

SAIFUN

19

The RDSR command requires the following
sequence:

1. The CSb pin is pulled low to select
the device and the RDSR opcode is
transmitted on the SI pin.

CS

SCK

SI

SO

1 32109876540 14131211

Instruction

High Impedanc e

MSB

Figure 10. Read Status Register (RDSR) Instruction Sequence

2. The data on the SI pin becomes
Don't Care.

3. The data from the status register is
shifted out on the SO pins, with the
D7 bit first and the D0 bit last, as
shown in Figure 10.

15 181716 22212019

Status Register Out

132 07654

Status Register Out

MSB

23

7

132 07654

MSB

SA25C020 Advanced Information

SAIFUN

20

Write Enable (WREN)

The device powers up in the Write Disable
state when V
instructions must be preceded by a WREN
instruction. The instruction sequence is
shown in Figure 11, with SO in high
impedance.

is applied. All programming

CC

CS

SCK

1

Write Disable (WRDI)

To protect the device against inadvertent
writes, the WRDI instruction disables all
programming modes. The WRDI
instruction is independent of the WP pin's
status. The WREN instruction should be
executed after the WRDI instruction to
re-enable all programming modes. The
instruction sequence is shown in Figure 12,
with SO in high impedance.

3276540

Instruction

SI

CS

SCK

SI

Figure 11. Write Enable (WREN) Instruction Sequence

1

Figure 12. Write Disable (WRDI) Instruction Sequence

3276540

Instruction

SA25C020 Advanced Information

SAIFUN

21

Write Status Register (WRSR)

The WRSR instruction enables the user to
select one of four levels of protection. The
SA25C020 is divided into four array
segments. The top quarter, top half or all of
the memory segments can be protected
(for more details, refer to Table 8). The
data within a selected segment is therefore
read-only.

Table 8. Block Write Protect Bits

Level

Status Register Bits

BP1 BP0

0

1/4

1/2

All

0 0 None

0 1 30000 - 3FFFF

1 0 20000 - 3FFFF

1 1 00000 - 3FFFF

The WRSR instruction (as shown in
Table 9) also allows the user to enable or
disable the WPb pin via the WPBEN bit.
Hardware write protection is enabled when
the WPb pin is low and the WPBEN bit is
1, and disabled when either the WP pin is
high or the WPBEN bit is 0. When the
device is hardware write protected, writes
to the status register are disabled.

Array Addresses

Protected

Table 9. WPBEN Operation

WPb WPBEN WEN

X 0 0 Protected Protected Protected

X 0 1 Protected Writeable W riteable

Low 1 0 Protected Protected Protected

Low 1 1 Protected Writeable Protected

High X 0 Protected Protected Protected

High X 1 Protected Writeable Writeable

Protected

Blocks

Un-

protected

Blocks

Status

Register

The WRSR instruction is enabled:

1. When the WPb pin is held high
and the device has been
previously write enabled via the
WREN instruction.

2. When the WPb pin is held low, the
WPBEN bit is 0 and the device
has been previously write enabled
via the WREN instruction.

NOTE:

When the WPBEN bit is hardware write
protected, it cannot be changed back
to 0 while the WPb pin is held low.

SA25C020 Advanced Information

SAIFUN

22

The WRSR command requires the
following sequence:

1. The CSb pin is pulled low to select
the device.

CS

1 32109876540 14131211 15

SCK

Instruction Status Register In

SI

SO

Figure 13. Write Status Register (WRSR) Instruction Sequence

High Impedance

2. The WRSR opcode is then
transmitted on the SI pin, followed
by the data to be programmed.

The instruction sequence is shown in
Figure 13.

132 07654

MSB

SA25C020 Advanced Information

SAIFUN

23

Read Data Bytes (READ)

Reading the memory via the serial SPI link
requires the following sequence:

1. After the CSb line is pulled low to
select the device, the READ
opcode is transmitted via the SI
line, followed by the 3-byte address
to be read (address bits A23 to A18
are Don’t Care).

2. Upon completion, any data on the
SI line is ignored.

3. The data (D7-D0) at the specified
address is then shifted out onto the
SO line. Each bit is shifted out at a
maximum SCK frequency of F

CS

SCK

.

If only one byte is to be read, the CSb line
should be driven high after the data comes
out. The READ sequence can be
continued, as the byte address is
automatically incremented and data
continues to shift out. When the highest
address is reached, the address counter
rolls over to the lowest address, enabling
the entire memory to be read in one
continuous READ cycle. The instruction
sequence is shown in Figure 14.

Driving CSb high terminates the READ
instruction, which can be done at any time
during data output. Any READ instruction
executed while an Erase, Program or
WRSR cycle is in progress is rejected
without having any effect on the cycle in
progress.

SCK

SI

SO

1 32109876540 31302928

Instruction

23 2122 132

High Impedance

24-Bit

Address

Figure 14. Read (READ) Instruction Sequence

3635343332 393837

0

DATA OUT 1 DATA OUT 2

132 07654

7

MSB

MSB

SA25C020 Advanced Information

SAIFUN

24

Byte or Page Write (PW)

The Byte or Page Write instruction allows
bytes to be programmed and erased in the
memory (changing bits from 1 to 0 and
from 0 to 1). In order to program to the
SA25C020, two separate instructions must
be executed. The device must first be write
enabled via the WREN instruction, and
then a Byte or Page Write sequence
(which consists of four bytes plus data)
may be executed. The address of the
memory locations to be written must be
outside the protected address field location
selected by the Block Write Protection
level. During an internal Write cycle, all
commands are ignored except the RDSR
instruction.

A Byte or Page Write instruction requires
the following sequence:

After the CSb line is pulled
low to select the device, the
WRITE opcode is transmitted
via the SI line, followed by the
byte address and the data
(D7-D0) to be written.

Programming starts after the CSb pin is
brought high. The CSb pin's low-to-high
transition must occur during the SCK low
time, immediately after the clock in the D0
(LSB) data bit. The instruction sequence is
shown in Figure 15, page 25.

As soon as CSb is driven high, the
self-timed Write cycle (whose duration is
defined as T

) is initiated. While the Page

PW

Write cycle is in progress, the status
register may be read to check the value of
the Write in Progress (/RDY) bit. The /RDY
bit is 1 during the self-timed Page Write
cycle, and 0 when it is completed. The
Write Enable Latch (WEN) bit is reset at
some unspecified time before the cycle is
completed.

The SA25C020's PW operation is capable
of up to a 256-byte writing, from 1 to 256
bytes at a time (changing bits from 1 to 0
and from 0 to 1), provided that they lie in
consecutive addresses on the same page
of memory. After each byte is received, the
eight low-order address bits are internally
incremented by one. If more than 256
bytes of data are transmitted, the address
counter rolls over and the previously
written data is overwritten. The SA25C020
is automatically returned to the write
disable state at the completion of a Write
cycle.

NOTES:

1. If the device is not write enabled,
the device ignores the PW
instruction and returns to the
standby state when CSb is brought
high. A new CSb falling edge is
required to re-initiate the serial
communication.

2. A PW instruction applied to a page
that is protected by the Block
Protect (BP1, BP0) bits (as
described in Table 7, page 18, and
Table 8, page 21) is not executed.

SA25C020 Advanced Information

SAIFUN

CS

25

SCK

SI

CS

SCK

SI

1 3210987654031302928

Instruction

23 2122 132 0

MSB

4443424140 474645 5251594948 555453

Data Byte 2

132 07654

MSBMSB

24-Bit

Address

Data Byte 3

Data Byte 1

MSB

2072

2074

2073

Data Byte 256

132 07654

MSB

Figure 15. Byte or Page Write (PW) Instruction Sequence

3635343332 393837

2075

132 07654

2079

2078

2077

2076

132 07654

SA25C020 Advanced Information

SAIFUN

26

Read Electronic Signature (Read_Id)

The device features an 8-bit Electronic
Signature, whose value for the SA25C020
is 11h. This can be read using the RES
instruction.

The Read Id instruction always provides
access to the Electronic Signature of the
device (except while a Byte/Page Write or
Write Status Register cycle is in progress).
Any Read Id instruction executed while a
Byte/Page Write or Write Status Register
cycle is in progress is not decoded, and
has no effect on the cycle in progress.

The device is first selected by driving CSb
low. The instruction code is followed by
three dummy bytes, each bit being latched
in on SI during the rising edge of SCK.

CS

The 8-bit Electronic Signature, which
stored in the memory, is then shifted out on
SO, with each bit being shifted out during
the falling edge of SCK. The instruction
sequence is shown in Figure 16.

Driving CSb high after the Electronic
Signature has been read at least once
terminates the Read Id instruction. Sending
additional clock cycles on SCK, while CSb
is driven low causes the Electronic
Signature to be output repeatedly.

When CSb is driven high, the device is put
into Standby mode. The transition to
Standby mode is delayed by t
must remain high for at least t

, and CSb

RES

(max), as

RES

specified in Table 3 on page 10. Once in
Standby mode, the device waits to be
selected, so that it can receive, decode and
execute instructions.

SCK

SI

SO

1 32109876540 31302928

Instruction

23 2122 132 0

MSB

High Impedance

3 Dummy

Bytes

MSB

Software Protect Mode Standby Mode

3635343332 393837

Electonic ID

t

RES

132 07654

Figure 16. Read Electronic Signature (Read Id) Instruction Sequence

SA25C020 Advanced Information

SAIFUN

27

Powerup and Powerdown

The device must not be selected at
powerup or powerdown (that is, CSb must
follow the voltage applied on V
reaches the correct value, as follows:

•= V

(min) at powerup, and then for a

CC

further delay of t

(as described in

PU

Table 10)

•= V

at powerdown

SS

A simple pull-up resistor on CSb can
usually be used to insure safe and proper
powerup and powerdown. To avoid data
corruption and inadvertent write operations
during powerup, a Power On Reset (POR)
circuit is included. The logic inside the
device is held at reset while V
than the POR threshold value (V
operations are disabled and the device
does not respond to any instructions.

The device ignores all instructions until a
time delay of t
moment that V

has elapsed after the

PU

rises above the VWI

CC

threshold. However, correct operation of
the device is not guaranteed if by this time

is still below VCC(min). No Write Status

V

CC

Register, Program or Erase instructions
should be sent until t
minimum V

threshold after VCC.

CC

PU

) until VCC

CC

is less

CC

), all

POR

reaches the

At powerup, the device is in Standby mode
(not SP mode) and the WEN bit is reset.

Normal precautions must be taken for
supply rail decoupling to stabilize the V

CC

feed. Each device in a system should have
the V

rail decoupled by a suitable

CC

capacitor close to the package pins (this
capacitor is generally of the order of

0.1 µF).

All operations are disabled and the device
does not respond to any instructions when

drops at powerdown from the

V

CC

operating voltage to below the V

POR

threshold. (The designer must be aware
that if a powerdown occurs while a Write,
Program or Erase cycle is in progress, data
corruption can result.)

Table 10. Powerup

Symbol Parameter Min. Max. Unit

V

POR

tPU

POR Threshold

V

CC

Value

(min) to CS

low

2.2

2

2.4 V

ms

SA25C020 Advanced Information

SAIFUN

Physical Dimensions

All measurements are in inches (millimeters), unless otherwise specified.

28

Figure 17. 8-pin SOIC Package

SA25C020 Advanced Information

SAIFUN

29

Figure 18. 8-pin MLF Leadless Package

SA25C020 Advanced Information

SAIFUN

30

Figure 19. Molded Dual-in-line Package (N) Package Number N08E

SA25C020 Advanced Information

SAIFUN

Contact Information

International Headquarters United States

Saifun Semiconductors Ltd.
ELROD Building
45 Hamelach St.
Sappir Industrial Park
Netanya 42504
Israel

Tel.: [phone]
Fax: +972- (0) 9-892-8445

Email: [e-mail]
http://www.saifun.com

Saifun Semiconductors Inc.
2350 Mission College Blvd.
Suite 1070
Santa Clara, CA 95054
U.S.A.

Tel: [phone]
Fax: [phone]

31

Revision History

Rev Date Description of Change

0.0 20-July-03 Initial Release

© Saifun Semiconductors Ltd. 2003

Saifun reserves the right, without notice, to change any of the products described in this guide, in order to improve
functionality, reliability or design. Saifun assumes no liability arising from the application or use of any product described in
this guide; and under its patent rights, gives no authorization for the use of this product or associated products. The Buyer
will not hold Saifun responsible for direct or indirect damages and expenses, as well as any claim of injury or death,
associated with the unauthorized use, including claims of manufacture or design negligence.

Saifun and Saifun NROM are trademarks or registered trademarks of Saifun Semiconductors Ltd. Other company and brand
products and service names are trademarks or registered trademarks of their respective holders.

Life Support Policy

Saifun's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Saifun Semiconductors Ltd. As used herein:

1. Life support devices or systems are devices
or systems which, (a) are intended for
surgical implant into the body, or (b) support
or sustain life, and whose failure to perform,
when properly used in accordance with
instructions for use provided in the labeling,
can be reasonably expected to result in a
significant injury to the user.

2. A critical component is any component of
a life support device or system whose
failure to perform can be reasonably
expected to cause the failure of the life
support device or system, or to affect its
safety or effectiveness.