Datasheet N82503, S82503 Datasheet (Intel Corporation)

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

October 1995COPYRIGHT©INTEL CORPORATION, 1996 Order Number: 290421-004

82503

DUAL SERIAL TRANSCEIVER (DST)

82503 PRODUCT FEATURE SET OVERVIEW

Y

Single Component Ethernet* Interface
to Both 802.3 10BASE-T and AUI

Y

Automatic or Manual Port Selection

Y

Manchester Encoder/Decoder and
Clock Recovery

Y

No Glue Interface to Industry-Standard
LAN Controllers
Ð Intel 82586, 82590, 82593 and 82596
Ð AMD 7990 (LANCE*)
Ð National Semiconductor 8390 and

83932 (SONIC*)
Ð Western Digital 83C690
Ð Fujitsu 86950 (Etherstar*)

Y

Diagnostic Loopback

Y

Reset, Low Power Modes

Y

Network Status Indicators

Y

Defeatable Jabber Timer

Y

User Test Modes

Y

10 MHz Transmit Clock Generator

Y

One Micron CHMOS** IV (Px48)
Technology

Y

Single 5-V Supply

INTERFACE FEATURES

TPE

Y

Complies with 10BASE-T, IEEE Std.

802.3i-1990 for Twisted Pair Ethernet

Y

Selectable Polarity Switching

Y

Direct Interface to TPE Analog Filters

Y

On-Chip TPE Squelch

Y

Defeatable Link Integrity (LI)

Y

Support of Cable Lengthsl100m

AUI

Y

Complies with IEEE 802.3 AUI Standard

Y

Direct Interface to AUI Transformers

Y

On-Chip AUI Squelch

A block diagram of a typical application is shown in Figure 1. The 82503 Dual Serial Transceiver is a high-inte­gration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE

802.3 local area network applications (10BASE5, 10BASE2, and 10BASE-T). The component supports both
an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE). It allows OEMs to design a
state-of-the-art media interface that is jumperless and fully automatic. The 82503 includes on-chip AUI and
TPE drivers and receivers; it offers designers a cost-effective, integrated solution for interfacing LAN control­lers to the wire medium.

**CHMOS is a patented process of Intel Corporation.

*Ethernet is a registered trademark of Xerox Corporation.

LANCE is a registered trademark of Advanced Micro Devices.
Etherstar is a registered trademark of Fujitsu Electronics.
Sonic is a registered trademark of National Semiconductor Corporation.

82503 Dual Serial Transceiver (DST)

CONTENTS PAGE

1.0 82503 PRODUCT FEATURES

ААААААААА 3

2.0 PIN DEFINITION ААААААААААААААААААААААА 5

2.1 Power Pins АААААААААААААААААААААААААА 6

2.2 Clock Pins ААААААААААААААААААААААААААА 6

2.3 AUI Pins ААААААААААААААААААААААААААААА 6

2.4 TPE Pins АААААААААААААААААААААААААААА 7

2.5 Controller Interface Pins ААААААААААААА 7

2.6 Mode Pins ААААААААААААААААААААААААААА 8

2.7 LED Pins АААААААААААААААААААААААААААА 9

3.0 82503 ARCHITECTURE АААААААААААААА 10

3.1 Clock Generation ААААААААААААААААААА 10

3.2 Transmit Blocks АААААААААААААААААААА 10

3.3 Receive Blocks ААААААААААААААААААААА 11

3.4 Collision Detection ААААААААААААААААА 13

3.5 Link Integrity ААААААААААААААААААААААА 13

3.6 Jabber Function АААААААААААААААААААА 13

3.7 TPE Loopback ААААААААААААААААААААА 13

3.8 SQE Test Function ААААААААААААААААА 14

3.9 Port Selection АААААААААААААААААААААА 14

3.10 LED Description ААААААААААААААААААА 14

3.11 Polarity Switching ААААААААААААААААА 14

3.12 Controller Interface АААААААААААААААА 15

CONTENTS PAGE

4.0 RESET, LOW POWER AND TEST
MODES

АААААААААААААААААААААААААААААААА 16

4.1 Reset АААААААААААААААААААААААААААААА 16

4.2 Low Power and High Impedance
Modes

ААААААААААААААААААААААААААААААА 16

4.3 Diagnostic Loopback ААААААААААААААА 16

4.4 Customer Test Modes (Continuous
AUI/TPE Transmit) АААААААААААААААААА 16

5.0 APPLICATION EXAMPLE АААААААААААА 17

5.1 Introduction АААААААААААААААААААААААА 17

5.2 Design Guidelines АААААААААААААААААА 17

5.3 Layout Guidelines АААААААААААААААААА 17

6.0 PACKAGE THERMAL
SPECIFICATIONS АААААААААААААААААААААА 19

7.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS АААААААААААААААААААААААААА 20

2

82503

290421– 1

Figure 1. Application Block Diagram

1.0 82503 PRODUCT FEATURES

The 82503 incorporates all the active circuitry re­quired to interface Ethernet controllers to 10BASE-T
networks or the attachment unit interface (AUI). It
supports a direct no-glue interface to Intel’s family of
high-performance LAN controllers (82586, 82590,
82593, and 82596). The 82503 also provides a di­rect no-glue interface to the National Semiconductor
8390 and 83932 (SONIC), the Western Digital
83C690, the Advanced Micro Devices 7990
(LANCE) and 79C900 (ILACC), and the Fujitsu
86950 (Etherstar) controllers.

This component includes three advanced features:
jumperless two-port design capability, automatic port
selection, and polarity switching. The jumperless
TPE or AUI port selection capability allows design­ers maximum ease-of-use and network flexibility. Au­tomatic port selection ensures complete software
compatibility with existing 10BASE2 and 10BASE5
software drivers. The 82503’s polarity switching fea­ture will detect and correct polarity errors on the
twisted pairÐthe most common wiring fault in twist­ed pair networks.

The 82503 contains all the circuitry needed to meet
the 10BASE-T specification, including link integrity, a
jabber timer and internal predistortion. Deselecting
link integrity allows the component to be used in
some prestandard networks. The 82503’s jabber
timer prevents the station from continuously trans­mitting and is defeatable for simple design charac-

terization. The predistortion circuitry eliminates line
overcharge and reduces jitter on 10BASE-T links.

The 82503 can also support twisted pair cable
lengths of up to 200m when placed in TPE Extended
Squelch Mode (XSQ).

This component incorporates six LED drivers to dis­play transmit data, receive data, collision, link integri­ty, polarity faults and port selections, allowing for
complete network monitoring by the user. The trans­mit, receive and collision LEDs indicate the rate of
activity by the frequency of flashing. The 82503 also
has a low power mode. During low power, many of
the 82503’s pins are in a high-impedance state to
facilitate board-level testing.

The 82503’s diagnostic loopback control enables it
to route a transmission signal from the LAN control­ler through its Manchester encoder-decoder circuitry
and back to the LAN controller. This provides effec­tive network node fault detection and isolation capa­bilities. In addition, the 82503 supports diagnostic
test modes that generate continuous tranmission of
data through the twisted pair port, allowing design­ers to measure the analog performance of their de­sign.

The 82503 is available in 44-lead PLCC and 44-lead
QFP packages and is fabricated with Intel’s low­power, high-speed, CHMOS IV technology using a
single 5-V supply.

3

82503

290421– 2

Figure 2. 82503 Functional Block Diagram

4

82503

2.0 PIN DEFINITION

290421– 3

Figure 3. 44-Lead PLCC Pin Configuration

290421– 44

Figure 4. 44-Lead QFP Pin Configuration

5

82503

2.1 Power Pins

Symbol

PLCC QFP

Type Name and Function

Pin Pin

V

SS

(1)

7, 17, 39 1, 11, 33 Supply Digital Ground.

V

CC

(1)

6, 18, 40 44, 12, 34 Supply Digital VCC. A 5-Vg5% Power Supply.

V

CCA

(1)

28 22 Supply Analog VCC. A 5-Vg5% Power Supply.

V

SSA

(1)

29 23 Supply Analog Ground.

NOTE:

1. V

CC

and V

CCA

must be connected to the same power supply. VSSand V

SSA

must be connected to the same ground.

Separate decoupling and noise conditioning (e.g., ferrite beads) should be used.

2.2 Clock Pins

Symbol

PLCC QFP

Type Name and Function

Pin Pin

X1 21 15 I CLOCK CRYSTAL. A 20 MHz crystal input. This pin can be driven

with an external MOS level clock when X2 is left floating.

X2 20 14 O CLOCK CRYSTAL. A 20 MHz crystal output. X1 can be driven with

an external MOS level clock when this pin is left floating.

2.3 AUI Pins

Symbol

PLCC QFP

Type Name and Function

Pin Pin

TRMT 27 21 O TRANSMIT PAIR. A differential output driver pair that drives the

transmit pair of the transceiver cable. The output bit stream is

TRMT

26 20 O

Manchester encoded. Following the last transition, which is positive
at TRMT, the differential voltage is reduced to zero volts.

RCV 31 25 I RECEIVE PAIR. A differentially driven input pair which is tied to the

receive pair of the Ethernet transceiver cable. The first transition on

RCV

30 24 I

RCV is negative-going to indicate the beginning of the frame. The
last transition is positive-going to indicate the end of the frame. The
received bit stream is assumed to be Manchester encoded.

CLSN 25 19 I COLLISION PAIR. A differentially driven input pair tied to the

collision presence pair of the Ethernet transceiver cable. The

CLSN

24 18 I

collision presence signal is a 10 MHz square wave. The first
transition at CLSN is negative-going to indicate the beginning of the
signal; the last transition is positive-going to indicate the end of the
signal.

6

82503

2.4 TPE Pins

Symbol

PLCC QFP

Type Name and Function

Pin Pin

TDH 35 29 O TP TRANSMIT PAIR DRIVERS. These four outputs constitute the

twisted-pair drivers, which have predistortion capabilities. The TDH/

TDH

37 31 O

TDH outputs generate the 10 Mb/s Manchester Encoded data. The

TDL 34 28 O

TDL/TDL

outputs mirror the TDH/TDH outputs except for fat bit

TDL

36 30 O

occurrences (100 ns pulses). During the second half of a fat bit
(either high or low), the TDL/TDL outputs are inverted with respect
to TDH/TDH

outputs. This signal behavior reduces the amount of

jitter by preventing overcharge on the twisted pair medium.

RD 32 26 I TP RECEIVE PAIR. The differential twisted pair receiver. The

receiver pair is connected to the twisted pair medium and is driven

RD

33 27 I

with 10 Mb/s Manchester encoded data.

2.5 Controller Interface Pins

Symbol

PLCC QFP

Type Name and Function

Pin Pin

TxC 93OTRANSMIT CLOCK. A 10 MHz clock output tied directly to the

transmit clock pin of the Ethernet controller. Changes sense
depending on controller selected. Active low for Intel and Fujitsu
controller interfaces, active high for National and AMD interfaces.
Can drive one TTL load.

TxD 16 10 I TRANSMIT DATA. TTL input. NRZ serial data is clocked in on TxD

from the Ethernet controller. Connects directly to the transmit data
pin of the Ethernet controller.

RTS 15 9 I REQUEST TO SEND. TTL input. An active low input signal

synchronous to TxC

which enables data transmission on the active
port. Changes sense depending on controller selected. Active low
for the Intel controller interface, active high for National, AMD, and
Fujitsu interfaces.

RxC 14 8 O RECEIVE CLOCK. A 10 MHz clock output tied directly to the

receive clock pin of the Ethernet controller. This clock is the
recovered clock from incoming data on the active port. Changes
sense depending on controller selected. Active low for Intel and
Fujitsu controller interfaces, active high for National and AMD
interfaces. Can drive one TTL load.

RxD 13 7 O RECEIVE DATA. Received NRZ data (synchronous to RxC) passed

to the Ethernet controller. Connect directly to the receive data pin of
the controller. Can drive one TTL load.

CRS 10 4 O CARRIER SENSE. Output that alerts the Ethernet controller that

data is present on the active port. Connects directly to the carrier
sense pin of the Ethernet controller. Changes sense depending on
controller mode selected. Active low for Intel controller interface,
active high for National, AMD, and Fujitsu interfaces. Can drive one
TTL load.

CDT 12 6 O COLLISION DETECT. Output that indicates presence of a collision.

Connects directly to the collision detect pin of the Ethernet
controller. Changes sense depending on controller selected. Active
low for Intel and Fujitsu controller interfaces, active high for National
and AMD interfaces. Can drive one TTL load.

7

82503

2.6 Mode Pins

Symbol

PLCC QFP

Type Name and Function

Pin Pin

TPE/AUI 2 40 I/O PORT SELECT. TTL input/LED output. If APORT is low,

TPE/AUI

is an input and selects either the TPE port (TPE/AUI
high) or AUI port (TPE/AUI low). If APORT is high, the 82503 will
indicate the port selected by driving TPE/AUI

high (TPE) or low

(AUI). TPE/AUI

can drive an LED pull-up.

APORT 3 41 I AUTOMATIC PORT SELECTION. TTL input. When high, 82503

will automatically select TPE or AUI port based on presence of
valid link beats or frames on the TPE receive input. Mode
selected will be indicated on TPE/AUI

.

APOL/XSQ 4 42 I AUTOMATIC POLARITY CORRECTION/EXTENDED

SQUELCH ENABLE. TTL input. When high, the extended
squelch mode is disabled and automatic polarity correction is
enabled. Both junctions (APOL and XSQ) are enabled when this
pin is at a high impedance state. When low, both functions
become disabled. The presence of a polarity fault on the TPE
receive pair is indicated on POLED regardless of the state of
APOL.

LID 38 32 I LINK INTEGRITY DISABLE. TTL input. If high, link integrity

function is disabled. If low, link integrity function is enabled.

CS0 5 43 I CONTROLLER SELECT. Selects the appropriate interface for

the desired Ethernet controller. When CS0/1

e

0/0, supports

CS1 8 2 I

Intel controllers. When CS0/1

e

0/1, supports Fujitsu

controllers. When CS0/1

e

1/0, supports Western Digital and

National controllers. When CS0/1

e

1/1, supports AMD

controllers. (See Table 2.)

LPBK 11 5 I LOOPBACK. TTL input. An active low input signal that causes

the 82503 to enter diagnostic loopback mode. The twisted pair
or AUI medium will be removed from the circuit, thus isolating
the node from the network. When not connected, this pin
assumes the inactive (high) state. Diagnostic loopback does not
disable the operation of the link integrity processor, link beat
generator, or automatic port selection.

JABD 23 17 I JABBER DISABLE. TTL input. When high, this pin disables the

jabber function. When low, the jabber function is enabled and
the device performs AUI or TP jabber protection for the active
port. If this pin and TEST are asserted during a falling edge of
RESET, the 82503 enters its low power mode; when either this
pin or TEST deasserts, then the 82503 transitions to its normal
operating mode.

TEST 19 13 I TEST MODE ENABLE. TTL input. When TEST is high and

RESET is deasserted, a customer test mode is directly
accessed. When driven low, test mode is disabled. If this pin and
JABD are asserted during a falling edge of RESET, the 82503
enters its low power mode; when either this pin or JABD
deasserts, then the 82503 transitions to its normal operating
mode.

RESET 22 16 I RESET. TTL input. When high, resets internal circuitry. On the

falling edge of RESET, either test mode or low power mode can
be entered depending on the state of JABD and TEST.

8

82503

2.7 LED Pins

Symbol

PLCC QFP

Type Name and Function

Pin Pin

TxLED 42 36 I/O TRANSMIT LED. LED output. Indicates transmit status of the AUI or

TPE port. Normally off (high) output. Turns on to indicate
transmission. Flashes at a rate dependent on the level of transmit
activity. Upon entering a customer test mode, this pin must be
driven high either through an LED, or a resistor.

RxLED 43 37 I/O RECEIVE LED. LED output. Indicates receive status of the AUI or

TPE port. Normally off (high) output. Turns on to indicate reception.
Flashes at a rate dependent on the level of receive activity. Upon
entering a customer test mode, this pin must be driven high either
through an LED, or a resistor.

COLED 44 38 I/O COLLISION LED. LED output. Indicates collision status of the AUI

or TPE port. Normally off (high) output. Turns on to indicate
collision. Flashes at a rate dependent on the level of collision
activity. This pin is also used to determine which customer test
modes are entered.

LILED 41 35 O LINK INTEGRITY LED. LED output. Normally on (low) output which

indicates good link integrity on the TPE port during TPE mode.
Remains on when link integrity function has been disabled. Turns off
during AUI mode or when link integrity fails in TPE mode. Minimum
off time is 100 ms, minimum on time is set by the link integrity
function.

POLED 1 39 O POLARITY INDICATION. LED output. If the 82503 detects that the

receive TPE wires are reversed, POLED will turn on (low) to indicate
the fault. POLED remains on even if APOL/XSQ is high and the
82503 has automatically corrected for the reversed wires.

NOTE:

1. The LED outputs have a weak pull-up capable of sourcing 500 mA. They can sink 10 mA while still meeting TTL levels. All
LEDs can be used as indication pins if no LED is needed. Some of these outputs include pulse width conditioning, which
should be accounted for in software.

9

82503

3.0 82503 ARCHITECTURE

3.1 Clock Generation

A 20 MHz parallel resonant crystal is used to control
the clock generation oscillator, which provides the
basic 20 MHz clock source. An internal divide-by­two counter generates the 10 MHz

g

0.01% clock

required by the IEEE 802.3 specification.

We recommend a crystal that meets the following
specifications be used.

#

Quartz Crystal

#

20 MHzg0.002% at 25§C

#

Accuracyg0.005% over full operating tempera­ture, 0

§

Ctoa70§C

#

Parallel resonant with 20 pF Load Fundamental
Mode

#

Maximum Series Resistance: R

SERIES

e

30X

Several vendors have such crystals; either-off-the
shelf or custom made. Two possible vendors are:

1. M-Tron Industries, Inc.

Yankton, SD 57078

Specifications;
Part No. HC49 with 20 MHz, 50 PPM over 0

§

Cto

a

70§C, and 20 pF fundamental load.

2. Crystek Corporation

100 Crystal Drive
Ft. Myers, FL 33907

Part No. 013212

The accuracy of the Crystal Oscillator frequency de­pends on the PC board characteristics, therefore it is
advisable to keep the X1 and X2 traces as short as
possible. The optimum value of C1 and C2 should
be determined experimentally under nominal operat­ing conditions. The typical value of C1 and C2 is
between 22 pF and 35 pF.

An external 20 MHz MOS-level clock may be applied
to pin X1, if pin X2 is left floating.

3.2 Transmit Blocks

3.2.1 MANCHESTER ENCODER

The 20 MHz clock is used to Manchester-encode
data on the TxD input. This clock is also divided by
two to produce the 10 MHz clock the LAN controller
needs for synchronizing its RTS

and TxD signals.

Data encoding and transmission begins with RTS
asserting. Since the first bit of a transmission is a 1,
the first transition is always negative on the transmit
outputs (TRMT or TD pins). Transmission ends
when RTS

deasserts. The last transition is always
positive at the transmit outputs (TRMT or TD pins)
and may occur at the center of the bit cell if the last
data bit to be transmitted is a 1, or at the boundary
of the bit cell if the last data bit to be sent is a 0.

Immediately after the end of a transmission, all sig­nals on the RCV pair (when AUI mode is selected)
are inhibited for 4 to 5 ms. This dead time is neces­sary for proper operation of the SQE (heartbeat)
test.

3.2.2 AUI CABLE DRIVER

The AUI cable driver (TRMT pair) is a differential
circuit, which interfaces to the AUI cable through a
pulse transformer.

High voltage protection is achieved by using a trans­former to isolate the transmit pins (TRMT pair) from
the transceiver cable. The total transmit circuit in­ductance, including the 802.3 transceiver transform­ers, should be a minimum of 27 mH for Ethernet ap­plications.

3.2.3 TWISTED PAIR CABLE DRIVER

The twisted pair line drivers (TD pairs) begin trans­mitting the serial Manchester bit stream 3 bit times
after RTS

is asserted. The line drivers use a predis­tortion algorithm to improve jitter performance for up
to 100 meters of twisted pair cable. The line drivers
reduce their drive level during the second half of
‘‘fat’’ (100 ns) Manchester pulses and maintain a full
drive level during all ‘‘thin’’ (50 ns) pulses and during
the first half of the ‘‘fat’’ pulses. This reduces line
overcharging during ‘‘fat’’ pulses, a major source of
jitter.

10

82503

290421– 4

Figure 5. TPE Predistortion

3.3 Receive Blocks

3.3.1 MANCHESTER DECODER AND CLOCK
RECOVERY

The 82503 performs Manchester decoding and tim­ing recovery of the incoming data in AUI and TPE
modes.

The Manchester-encoded data stream is decoded to
separate the Receive Clock (RxC

) and the Receive
Data (RxD) from the differential signal. The 82503
uses an advanced digital technique to perform the
decoding function. The use of digital circuitry instead
of analog circuitry (e.g., a phase-lock loop) to per­form the decoding ensures that the decoding func­tion is less sensitive to variations in operating condi­tions.

A high-resolution phase reference is used to digitize
the phase of the incoming data bit-center transition.
The digitizer has a phase resolution of 1/32 of a bit
time.

The digitized phase is filtered by a digital low-pass
filter to remove rapid phase variations, i.e., phase
jitter. Slow phase variations, such as those caused
by small differences between the data frequency
and the clock frequency, are not filtered by the low­pass filter.

The RxC generator digitally sets the phases of the
two RxC

transitions to respectively lead and lag the

bit-center transition by (/4 bit time. RxC

is used to
recover RxD by sampling the incoming data with an
edge-triggered flip-flop.

Lock is achieved by reducing the time constant of
the digital filter to zero at the start of a new frame.
Any uncertainty in the bit-center phase of the first
transition that is caused by jitter is subsequently re­moved by gradually increasing the filter time con­stant during the following preamble. By that time, the
phase of the bit center is output by the filter, and
lock is achieved. Lock is achieved within the first 14
bit times as seen by the AUI inputs. The maximum
bit-cell timing distortion (jitter) tolerated by the Man­chester decoder circuitry is

g

12 ns (preamble),

g

18 ns (data) for AUI, andg13.5 ns for TPE (data

and preamble).

11

82503

290421– 5

Figure 6. Manchester Decoder and Clock Recovery

3.3.2 AUI RECEIVE AND COLLISION BUFFERS

The AUI receive and collision inputs are driven
through isolation transformers to provide high volt­age protection and DC common mode voltage rejec­tion. The incoming signals are converted to digital
levels and passed to the Manchester decoder and
collision detection circuitry.

3.3.3 AUI RECEIVE AND COLLISION
SQUELCH CIRCUITS

Both the receive (RCV) and collision (CLSN) pairs
have the following squelch characteristics.

#

The squelch circuits are turned on at idle.

#

A pulse is rejected if the peak differential voltage
is more positive than

b

160 mV regardless of

pulse width.

#

A pulse is considered valid if its peak differential
voltage is more negative than

b

300 mV and its

width, measured at

b

285 mV, is greater than

25 ns.

#

The squelch circuits are disabled by the first valid
negative differential pulse on either the AUI re­ceive (RCV) or the AUI collision (CLSN) pair.

#

If a positive differential pulse occurs on either the
AUI receive or collision pairs for greater than
160 ns, End of Frame (EOF) is assumed and the
squelch circuitry is turned on.

3.3.4 TPE RECEIVE BUFFER

The TPE receive pins (RD and RD

) are connected to
the twisted pair medium through an analog front
end. The analog front end contains the line coupling

devices and EMI filters necessary to conform to the
10BASE-T standards and local RF regulations. The
input differential voltage range for the TPE receiver
is greater than 500 mV and less than 3.1V differen­tial.

3.3.5 TPE RECEIVE SQUELCH CIRCUITS

The TPE receive buffer distinguishes valid receive
differential data, link test pulses, and the idle condi­tion according to the requirements of the 10BASE-T
standard. Signals at the output of the EMI filter (thus
at the RD and RD

pair) are rejected as follows:

#

All differential pulses of peak magnitude less than
300 mV are rejected.

#

All continuous sinusoids with a differential ampli­tude less than 6.2 V

PP

and a frequency less than

2 MHz are rejected.

#

All sine waves of single cycle duration starting
with phase 0

§

or 180§that have an amplitude less

than 6.2 V

PP

, and a frequency of 2 MHz to
16 MHz are rejected, if the single cycle is pre­ceeded and followed by 4 bit times of silence
(i.e., a signal less than 300 mV).

3.3.6 TPE Extended Squelch Mode

By placing the 82503 into TPE extended squelch
mode, the 82503 can support cable lengths greater
than the 100m specified in the 10Base-T IEEE stan­dard (802.3i-1990). The squelch thresholds for the
signals at the RD/RD

pair are typically reduced by

4.5 dB. This allows Grade 5 twisted-pair cable to be
used to overcome attenuation and multipair cross­talk for cable lengths up to 200 meters.

12

82503

TPE extended squelch mode is enabled by present­ing a high-impedance (

l

100 KX) at the APOL/XSQ
pin. This can be done by floating the APOL/XSQ pin,
tying APOL/XSQ low through a 100 K X resistor, or
driving APOL/XSQ with a three-state buffer. When
driven high or low using a TTL driver or a low imped­ance pull-up or pull-down (

k

2KX) extended
squelch is disabled and the driven level at the
APOL/XSQ pin determines the state of the polarity­correction function (APOL/XSQ

e

1 enables polari-

ty correction, APOL/XSQ

e

0 disables polarity cor­rection). The TPE extended squelch feature is trans­parent to previous steppings of the 82503. Polarity
correction is always enabled when the TPE extend­ed-squelch feature is enabled (APOL/XSQ

e

Z).

The APOL/XSQ pin senses a high-impedance state
by an active-polling circuit implemented at the pin.
Two small polling devices attempt to pull the APOL/
XSQ pin up to V

CC

and down to VSS. If the pin is in a
high-impedance state, the devices will be successful
in pulling the APOL/XSQ pin high and low. If the pin
is driven high or low, the polling devices will not be
able to successfully pull the pin in the opposite di­rection. In this way, an internal state machine can
correctly determine one of three states of the
APOL/XSQ pin. The pin is polled every 25.6 ms.

3.4 Collision Detection

3.4.1 AUI COLLISION DETECTION

Collision detection in the AUI mode is performed by
the attached transceiver, and signalled to the 82503
on the CLSN pair. A 10 MHz

a

25%, orb15%,
square wave with transition times between 35 ns
and 70 ns indicates the collision. The 82503 reports
this to the LAN controller on the CDT

pin.

3.4.2 TPE COLLISION DETECTION

Collision detection in the TPE mode is indicated by
simultaneous transmission and reception on the
twisted pair link segment. The CDT

signal is assert-

ed for the duration of both RTS

and the presence of

received data; CRS

is asserted for the duration of

either RTS

or the presence of received data. During
a collision, the source of RxD will be the received
data. If the received data stream ends before the
transmit data stream, the RxD source will be
changed to transmit data stream until it ends.

3.5 Link Integrity

The 82503 supports the link integrity function as de­fined by 10BASE-T. During long periods of idle on
the transmitter, link test pulses will be transmitted on

to the twisted pair medium as an indication to the
remote MAU that the link is good. These pulses will
be transmitted 8 ms to 24 ms after the end of the
last transmission or link test pulse.

The link integrity function continuously monitors ac­tivity on the receive circuit. If neither valid data nor
link test pulses are received, the link integrity proc­essor declares the link bad, and disables transmis­sion and reception on the media, loopback, and the
SQE test function. Transmission of link test pulses
and monitoring receive activity are not affected. The
idle time required for the link integrity processor to
determine the link is bad is 50 ms to 150 ms.

Once a frame or a sequence of 2 to 10 valid consec­utive link test pulses are detected, the Link Integrity
Processor declares the link is good, and reconnects
the transmitter and receiver.

The link integrity function can be disabled by driving
the LID pin high or by disabling automatic port selec­tion (APORT

e

0) and selecting the AUI port. This
option is intended primarily for use with pre­10BASE-T networks.

3.6 Jabber Function

The 82503 contains a jabber timer to implement the
jabber function. If a transmission continues beyond
the limits specified, the jabber function inhibits fur­ther transmission and asserts the collision indicator,
CDT. The limits for jabber transmission are 20 ms to
150 ms in TPE Mode, and 8 ms to 16 ms in AUI
mode. For both AUI and TPE mode, the transmis­sion inhibit period extends until the 82503 detects
sufficient idle time (between 250 ms and 750 ns) on
the RTS

signal. The jabber function can be disabled

by driving the JABD high.

In TPE mode the link integrity function continues to
operate even if the jabber function is inhibiting trans­mission. Link test pulses continue to be sent and the
receive circuit continues to be monitored. Additional­ly, the link integrity function reconnects to a restored
link without waiting for the transmit input to go idle
when the jabber function is inhibiting transmission.

3.7 TPE Loopback

In TPE mode the 82503 implements the transmit to
receive loopback (DO to DI) mode specified in the
10BASE-T standard. This mode loops back transmit­ted data through the receive path.

This function is required to maintain full compatibility
with coax MAUs where the data loopback is a natu­ral result of the architecture.

13

82503

The transmit to receive loopback function is disabled
when the jabber function or link integrity function is
inhibiting transmission.

3.8 SQE Test Function

The 82503 supports the SQE test function when in
TPE mode or in Diagnostic Loopback mode. The
82503 will assert its CDT

pin within 0.6 msto1.6ms
after the end of a transmission, and it will remain
asserted for 5- to 15-bit times. If the 82503 is in the
TPE mode and is not in diagnostic loopback mode,
the link integrity function will disable the SQE test
function when it detects a bad link.

3.9 Port Selection

The 82503 features both manual and automatic port
selection. To enable automatic port selection, con­nect APORT to V

CC

. The 82503 then starts in TPE
mode and monitors link integrity. If the link is good,
the 82503 stays in TPE mode and pulls TPE/AUI
high to indicate that the TPE port was selected. If
link integrity fails, the 82503 switches to AUI mode
and pulls TPE/AUI

low to indicate that the AUI port

is now active. TPE/AUI

can drive an LED to indicate
port selection (on for AUI, off for TPE mode). Note
that LILED will be on if TPE mode is selected and off
if AUI mode is selected. If link integrity is disabled
while automatic port selection is enabled, the 82503
defaults to TPE mode. If the 82503 changes ports
while RTS

is active, transmission is terminated with
an End of Frame marker on the old port. Transmis­sion of the remaining packet fragment is not allowed
on the new port. Transmissions will begin with a
complete data packet.

The port can be manually selected by driving
APORT low. TPE/AUI

e

0 selects AUI mode, and

TPE/AUI

e

1 TPE mode. When the port is manually
selected, the circuitry for the unused port is powered
down. Changing ports requires 100 ms to allow the
circuitry for the new port to resume normal opera­tion.

Table 1. Port Selection

Configuration

State

LID APORT TPE/AUI

X 0 0 AUI (TPE Port Powered Down)
X 0 1 TPE (AUI Port Powered Down)
01 X*Automatic Port Selection
11 X*TPE

NOTE:

*TPE/AUI

is an output pin when APORTe1.

3.10 LED Description

The 82503 supports six LED pins to indicate the
status of important states; TPE/AUI

, TxLED,
POLED, LILED, RxLED, COLED. Each pin is capable
of directly driving an LED.

3.10.1 TPE/AUI

When automatic port selection is enabled (APORT is
high), TPE/AUI

becomes an LED output and turns
off if TPE mode is selected and on if AUI mode is
selected.

3.10.2 TxLED

Transmit status. This LED is normally off and flashes
at 2.5 Hz, 5 Hz, and 10 Hz to indicate respectively a
low, medium, and high rate of transmit activity.

3.10.3 RxLED

Receive LED. This LED is normally off and flashes at

2.5 Hz, 5 Hz, and 10 Hz to indicate respectively a
low, medium, and high rate of receive activity.

3.10.4 COLED

Collision LED. This LED is normally off and flashes
at 2.5 Hz, 5 Hz, and 10 Hz to indicate respectively a
low, medium, and high rate of collision activity.

3.10.5 POLED

Polarity Fault. This LED is normally off and turns on
to indicate a polarity fault in the receive pair of the
10BASE-T link. Operation of this pin is not affected
by the state of the polarity correction function
(APOL/XSQ

e

X).

3.10.6 LILED

Link Integrity status. When Aport is enabled
(APORT

e

1), this LED is normally on (driven low)
to indicate the presence of a valid 10BASE-T link
when the TPE port is active. The LED will turn off
(driven high) when the link fails. When link integrity is
disabled (LID

e

1) while APORT is enabled

(APORT

e

1) this LED is turned on (driven low). If
APORT is disabled (APORT

e

0) and the AUI port is

manually selected (TPE/AUI

e

0) the LED output is

tristated.

3.11 Polarity Switching

In TPE mode, the 82503 monitors receive link beats
and end-of-frame delimiters for a possible receiver

14

82503

290421– 6

Figure 7. Polarity Fault State Diagram

polarity error due to crossed wires. If Pin 4 of the
82503 is high and the TPE receive pins are re­versed, the 82503 will correct the error by reversing
the signals internally, and turn POLED on (low) to
indicate that the fault has been detected and cor­rected. The polarity correction function is defeatable
by driving the APOL/XSQ input low. However, the
polarity fault will continue to be indicated on the
POLED.

3.12 Controller Interface

Connecting the 82503 to one of the Intel Ethernet
controllers (82586, 82590, 82593, 82596) requires
no additional components. Simply drive CS0 and
CS1 both low, and connect TxC

, TxD, RTS, RxC,

RxD, CRS

, CDT, and LPBK

to the corresponding

controller pins.

The 82503 also works with other Ethernet control­lers without additional components, including the
National Semiconductor 8390 and 83932 (SONIC),
Western Digital 83C690, Fujitsu 86950 (Etherstar),
depending on the state of and CS0 and CS1 inputs.

The interface of the 82503 to the AMD 7990
(LANCE) requires external logic to control the LPBK
pin of the 82503. Note that when an AMD LAN con­troller is used to interface to the 82503, the LPBK
pin of the 82503 becomes active high. That is, the
82503 enters diagnostic loopback mode when LPBK
pin is high and is in normal operation mode when
LPBK

pin is low.

The logic sense of the 82503 controller pins will
change and should be connected to the controller
pins according to the following table.

15

82503

Table 2. Controller Interface Selection

Intel

National, WD AMD

Fujitsu

82503

Controller

Controllers Controller

Controllers

Pin

825XX

8390, 83C690, 7990 (LANCE),

86950 (Etherstar)

83832 (SONIC) 79C900 (ILACC)

CS0

(1)

011 0

CS1 0 0 1 1

Pin Pin Sense Pin Sense Pin Sense Pin Sense

TxC TxC Low TXC High TCLK High TCKN Low
TxD TxD High TXD High TX High TXD High
RTS

RTS Low TXE High TENA High TEN High

RxC

RxC Low RXC High RCLK High RCKN Low
RxD RxD High RXD High RX High RXD High
CRS

CRS Low CRS High RENA High XCD High
CDT CDT Low COL High CLSN High XCOL Low
LPBK LPBK Low LPBK High LPBK High

(Note 2)

NOTES:

1. CS0 and CS1 are intended to be static pins only. Switching CS0 and CS1 during network reception or transmission will
produce unpredictable results.

2. Refer to Section 3.12.

4.0 RESET, LOW-POWER AND

TEST MODES

4.1 Reset

When RESET is asserted the device resets its inter­nal circuits. RESET is required after power up, and
before data can be transmitted or received. It is al­lowed any time thereafter, but any existing receive or
transmit activity will be lost, and all state machines
(Link integrity, Jabber, and Polarity Correction) re­turn to their initial states. TEST must be held low for
a device reset to prevent entering a test for low pow­er mode. During RESET, TxC

continues without in-

terruption (in Fujitsu mode both TxC

and RxC run

continuously).

4.2 Low Power and High Impedance

Modes

When RESET is deasserted while both TEST and
JABD are held high, the 82503 enters its low power
and high impedance modes. The majority of internal
circuitry is powered down, and many inputs and out­puts are three-stated. These pins are: APORT,
APOL/XSQ, LID, TPE/AUI

, POLED, LILED, RTS,

LPBK

, RxD, TxD, CRS and CDT. When either JABD
or TEST is deasserted, the device begins a power
on cycle which lasts less than 1 ms. During this cy­cle, all inputs are ignored and all transmissions are
disabled. If RTS

is active when the device returns to
normal operation, the remainder of that packet frag­ment is not transmitted. Normal transmissions are
resumed at the start of the first complete data pack­et.

4.3 Diagnostic Loopback

This is a diagnostic test mode to help in fault isola­tion and detection. Serial NRZ data input on TxD is
Manchester encoded and then looped back through
the Manchester decoder (TMD) appearing at the
RxD output. Collision detect is asserted following
each transmission to simulate the SQE test. Output
cable drivers and input amplifiers are disconnected
from the controller interface pins while in this mode.
The link integrity and polarity fault detection func­tions are not inhibited by diagnostic loopback mode.
If otherwise enabled, they continue to function.

4.4 Customer Test Mode
(Continuous AUI/TPE Transmit)

In this mode, the 82503 continuously transmits data
without the intervention of a LAN controller. Trans­mission is at 10 MHz (11-bit pattern), and can occur
on either the TPE or AUI port. The jabber timer is
disabled in this mode, allowing users to easily test
the 10BASE-T harmonic content specification and
the quality of their analog front end design without
complex software exercisers.

Customer Test ModeÐand Low Power Mode are se­lected at the deassertion of RESET as shown in the
following table. (Note that the 82503 must be in non­loopback mode before it can enter the customer test
mode.)

16

82503

Table 3. Test and Low Power Mode Selection

RESET TEST JABD TxLED

(1)

RxLED

(1)

COLED

(1)

Mode Selected

v

0 X X X X Normal Mode

v

1 0 1 1 1 Cont Tx 10 MHz

v

1 1 X X X Low Power

NOTE:

1. A standard LED connection to these pins is sufficient to pull them to a logic 1.

The port on which the continuous transmit appears
is determined by the APORT and TPE/AUI

pins. If

automatic port selection is enabled (APORT

e

1)
then the TPE port broadcasts the continuous trans­mit. If manual port selection is enabled (APORT

e

0), then TPE/AUI selects the port (1 for TPE, 0 for
AUI). Test mode is disabled when TEST is deassert­ed and the device is reset.

5.0 APPLICATION EXAMPLE

5.1 Introduction

The 82503 is designed to work directly with the Intel
LAN controllers (82586, 82590, 82593, and 82596),
as well as AMD’s Am7990, National Semiconduc­tor’s 8390, Western Digital’s 82C690, and Fujitsu’s

86950. The serial interface signals connect directly
between one of the aforementioned LAN controllers
and the 82503 without the need for external logic.

This example is targeted toward interfacing the
82503 to the Intel 82596 in a two-port (TPE/AUI)
application.

5.2 Design Guidelines

AUI Pulse Transformer

In order to meet the 16V fault tolerance specification
of 802.3 a pulse transformer is recommended for the
transmit, receive and collision pairs. The transformer
should be placed between the TRMT, RCV, and
CLSN pairs of the 503, and the DO, DI, and CI pairs
respectively, of the AUI (DB-15 connector). The
pulse transformer should have a parallel inductance
of 75 mH minimum (100 mH recommended).

Several vendors stock such transformers. Two pos­sible vendors are:

1. Pulse Engineering (P/N PE-64103)

2. Valor Electronics (P/N LT6003)

Terminating Resistors

The terminating resistors used across the receive
and collision pairs are recommended to be 78.7 X

g

1%.

Analog Front-End

The 82503 provides six TPE pins (TDH, TDH

, TDL,

TDL

, RD, and RD) that connect to the Analog Front
End through a resistor summing network (Figure 7).
AFE solutions can be made discretely or purchased
from several manufacturers. Two different solutions
are described in Application Note 356. The example
shown here uses a Pulse Engineering AFE package
PE65434 which includes EMI filter, isolation trans­former, and common mode choke. The output of the
AFE connects directly to the 10BASE-T connector
(RJ-45).

Decoupling

It is recommended that 0.01 mF X7R and 0.001 mF
NPO decoupling capacitors be placed between the
V

CCA

and V

CCD

of the 82503 to V

SSA

and V

SSD

.

Clock Generation

The clock input to the 82503 can be from a clock
oscillator or a crystal. If a clock oscillator is used, X1
should be driven, and X2 left floating. If a crystal
oscillator is used, refer to Section 3.1 for crystal
specifications.

A complete 82596/82503 TPE/AUI Ethernet Solu­tion is shown at the end of this section.

5.3 Layout Guidelines

General

The analog section, as well as, the entire board itself
should conform to good high-frequency practices
and standards to minimize switching transients and
parasitic interaction between various circuits. To
achieve this, the following guidelines are presented.

17

82503

290421– 7

Figure 8. Application Example Schematic

18

82503

Make power supply and ground traces as thick as
possible. This will reduce high-frequency cross cou­pling caused by the inductance of thin traces.

Connect logic and chassis ground together.

Separate and decouple all of the analog and digital
power supply lines.

Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling.

Use high-loss magnetic beads on power supply dis­tribution lines.

Crystal

The crystal should be adjacent to the 82503 and
trace lengths should be as short as possible. The X1
and X2 traces should be symmetrical.

82503 Analog Differential Signals

The differential signals from the 82503 to the trans­formers, analog front end, and the connectors
should be symmetrical for each pair and as short as
possible. Differential signal layout should be per­formed to a characteristic impedance of 78X (for
AUI) or 100X (for TPE).

As a general rule, the trace widths should be one to
three times the distance between the PCB layers to
eliminate excessive trace inductance.

The differential signals should also be isolated from
the high speed logic signals on the same layer as
well as on any sublayers of the PCB.

Group each of the circuits together, but keep them
separate from each other. Separate their grounds.

In layout, the circuitry from the connectors to the
filter network, should have the ground plane re­moved from beneath it. This will prevent ground
noise from being induced into the analog front end.

All trace bends should not exceed 45 degrees.

6.0 PACKAGE THERMAL

SPECIFICATIONS

The 82503 Dual Serial Transceiver is specified for
operation when case temperature (T

C

) is within the

range of 0

§

Ctoa85§C. The case temperature can
be measured in any environment, to determine if the
82503 is within the specified operating range. The
case temperature should be measured at the center
of the top surface opposite the pins.

The acceptable operating ambient temperature (T

A

)

is guaranteed as long as T

C

is not violated. The am-

bient temperature can be calculated from the i

ja

and ijcfrom the following equations:

T

J

e

T

C

a

Pci

jc

T

J

e

T

A

a

Pci

ja

T

A

e

T

C

b

Pc(i

ja

b

ijc)

Values for ijaand ijcare given in Table 4 for the 44­lead PLCC and 44-lead QFP packages. Various val­ues for i

ja

at different airflows. Table 5 shows the

maximum T

A

allowable (without exceeding TC)at

various airflows.

Table 4. Thermal Resistance

(

§

C/Watt) ijcand i

ja

ijavs AirflowÐft/min (m/s)

Package ijc0 200 400 600 800 1000

(0) (1.01) (2.03) (3.04) (4.06) (5.07)

44-Lead 19 57 48 43 41 39 37

PLCC

44-Lead 26 98 94 78 70 66 64

QFP

Table 5. Maximum TAat Various Airflows

ijavs AirflowÐft/min (m/s)

Package 0 200 400 600 800 1000

(0) (1.01) (2.03) (3.04) (4.06) (5.07)

44-Lead 66 71 73 74 75 76

PLCC

44-Lead 49 51 59 63 65 66

QFP

19

82503

7.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS

ABSOLUTE MAXIMUM RATINGS

Case Temperature Under Bias ААААААА0§Ctoa85§C

Storage Temperature ААААААААААb65§Ctoa140§C

All Output and Supply Voltages АААААb0.5V toa7V

All Input Voltages АААААААААААААb1.0V toa6.0V

(1)

NOTICE: This is a production data sheet. The specifi­cations are subject to change without notice.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

DC CHARACTERISTICS (T

C

e

0§Ctoa85§C, V

CC

e

5Vg5%, V

CCA

e

5Vg5%)

Symbol Parameter Min Max Units Test Conditions

VIL(TTL)

(2)

Input Low Voltage

b

0.3 0.8 V

VIH(TTL)

(2)

Input High Voltage 2.0 V

CC

V

I

LI

(2)

Input Leakage Current

g

10 mA 0.0VsV

I

s

VCC, RESETe1

VOL(MOS)

(3)

Output Low Voltage 0.45 V I

OL

e

4mA

VOH(MOS) Output High Voltage 3.9 V I

OH

eb

500 mA

VOL(LED)

(4)

Output Low Voltage 0.45 V I

OL

e

10 mA

VOH(LED) Output High Voltage 3.9 V I

OH

eb

500 mA

I

LP

Leakage Current, Low

g

10 mA 0.0VsV

I

s

V

CC

Power Mode

(5)

R

DIFF

Input Differential Resistance

(6)

10 kX dc

V

IDF

(TPE)

(7)

Input Differential Accept

g

0.500

g

3.1 VP5 MHzsfs10 MHz

Input Differential Reject

g

0.300 V

P

Input Differential Accept (XSQ) (Note 8)

g

3.1 V

P

Input Differential Reject (XSQ)

g

0.180 V

P

RS(TPE)

(8)

Output Source Resistance 6 13 XlI

LOAD

l

e

25 mA

V

IDF

(AUI)

(9)

Input Differential Accept

g

0.300

g

1.5 V

P

Input Differential Reject

g

0.160 V

P

V

ODF

(AUI)

(10)

Output Differential Voltage

g

0.450

g

1.20 V

NOTES:

1. The voltage levels for RCV, CLSN, and RD pairs are

b

0.75V toa8.5V.

2. TTL Input Pins: TxD, RTS

, TPE/AUI, APORT, APOL/XSQ, LID, CS0, CS1, LPBK, JABD, TEST, RESET.

3. MOS Output Pins: TxC

, RxD, RxC, CRS, CDT.

4. LED Pins: TPE/AUI

, TxLED, RxLED, COLED, POLED, LILED. VOLmeasured 10 ns after falling edge of TxC.

5. Pins: APORT, APOL/XSQ, LID, TPE/AUI

, POLED, LILED, RTS, LPBK, RxD, TxD, CRS,

CDT

, CS0, CS1, JABD, TEST, and RESET.

6. Pins: RD to RD

, RCV to RCV, and CLSN to CLSN.

7. TPE Input Pins: RD, and RD

. See Section 3.3.4 and Section 3.3.5.

8. Typically it is

b

4.5 dB below normal squelch level.

9. TPE Output Pins: TDH, TDH

, TDL, and TDL.RSmeasures VCCor VSSto Pin.

10. AUI Input Pins: RCV, and CLSN pairs.

11. AUI Output Pins: TRMT pair.

20

82503

DC CHARACTERISTICS (T

C

e

0§Ctoa85§C, V

CC

e

5Vg5%, V

CCA

e

5Vg5%) (Continued)

Symbol Parameter Min Max Units Test Conditions

I

OSC

(AUI) AUI Output Short Circuit Current

g

150 mA Short Circuit to VCCor GND

VU(AUI) Output Differential Undershoot

b

100 mV

V

ODI

(AUI) Differential Idle Voltage

(11)

g

40 mV

ICC(HOT) Power Supply Current

(12)

65 mA APORTe1

I

CC

Power Supply Current 75 mA APORTe1

I

CC

Power Supply Current 60 mA APORTe0

I

CCSB

Standby Supply Current

(13)

1 mA Low Power Mode, 20 mA Typical

PD (HOT) Power Dissipation

(12)

0.38 W APORTe1, Continuous Transmission
on AUI

PD Power Dissipation 0.40 W APORTe1, Continuous Transmission

on AUI

PD

SB

Standby Power Dissipation

(13)

5.25 mW Low Power Mode, 105 mW Typical

C

IN

(14)

Input Capacitance 10 pF at fe1 MHz

NOTES:

11. Measured 8.0 ms after last positive transition of data packet.

12. I

CC

HOT measurements made at T

C

ea

85§C. Additionally, TRMT, TRMT, TDH, TDH, TDL, TDL are loaded with 20 pF

and load resistors removed.

13. Pins CS0 and CS1 connected to V

CC

or VSSthrough a 2.5 kX (or less) resistor. I

CCSB

is typically at 20 mA after 30s

from power down assertionÐnot tested.

14. Characterized, not tested. (Controller interface and mode pins only.)

AC TIMING CHARACTERISTICS

290421– 8

Figure 9. MOS Input Voltage Levels

(TTL Compatible) for Timing Measurements

(TxD, RTS, TPE/AUI, APORT, APOL/XSQ,

LID, LPBK

, JABD, TEST, and RESET).

290421– 9

Figure 10. Voltage Levels for MOS Level

Output Timing Measurements

(TxC, RxD, RxC, CRS, and CDT).

290421– 10

Figure 11. Voltage Levels for Differential Input

Timing Measurements (RCV and CLSN Pairs).

290421– 11

Figure 12. Voltage Levels for TRMT Pair

Output Timing Measurements.

21

82503

AC TIMING CHARACTERISTICS (Continued)

290421– 12

Figure 13. Voltage Levels for

TDH, TDL, TDH

, and TDL.

290421– 13

Figure 14. Voltage Levels for Differential Input

Timing Measurements (RD Pair).

AC MEASUREMENT CONDITIONS

1. T

C

e

0§Ctoa85§C, V

CC

e

5Vg5%.

2. The AC MOS, TTL and differential signals are referred to in Figures, 8, 9, 10, 11, 12, and 13.

3. AC loads

a. MOS: 20 pF total capacitance to ground.

b. AUI Differential: a 10 pF total capacitance from each terminal to ground and a load resistor of 78X

g

1%

in parallel with a 27 mH

g

1% inductor between terminals.

c. TPE: 20 pF total capacitance to ground.

4. All parameters become valid 200 ms after the supply voltage and input clock has stabilized, or after RESET
deasserts.

CLOCK TIMING

(15)

Symbol Parameter Min Typ Max Units

t

1

X1 Cycle Time 49.995 50.005 ns

t

2

X1 Fall Time 5 ns

t

3

X1 Rise Time 5 ns

t

4

X1 Low Time 15 ns

t

5

X1 High Time 15 ns

NOTE:

15. Refers to External Clock Input.

290421– 14

Figure 15. X1 Input Voltage Levels for Timing Measurements

22

82503

Controller Interface Timings (Intel Mode)

TRANSMIT TIMINGS (Intel)

Symbol Parameter Min Typ Max Units

t

10

TxC Cycle Time 99.99 100.01 ns

t

11

TxC High/Low Time 40 ns

t

12

TxC Rise/Fall Time 5 ns

t

13

TxD and RTS Rise/Fall Time 10 ns

t

14

TxD Setup Time to TxC

v

45 ns

t

15

TxD Hold Time from TxC

v

0ns

t

16

RTS Setup Time to TxC

v

45 ns

t

17

RTS Hold Time from TxC

v

0ns

290421– 15

Figure 16. Transmit Timing (Intel)

23

82503

RECEIVE TIMING (Intel)

Symbol Parameter Min Typ Max Units

t

20

RxC Cycle Time 96 100 ns

t

21

RxC High Time 36 ns

t

22

RxC Low Time 40 ns

t

23

RxC Rise/Fall Time 5 ns

t

24

RxC Delay from CRS

v

1100 1400 ns

t

25

RxD Rise/Fall Time 5 ns

t

26

RxD Setup from RxC

v

30 ns

t

27

RxD Hold from RxC

v

30 ns

t

28

CRS Deassertion Hold Time from RxC High 10 40 ns

290421– 16

Figure 17. Receive Timing (Intel)

24

82503

Controller Interface Timings (National Mode)

TRANSMIT TIMINGS (National)

Symbol Parameter Min Typ Max Units

t

30

TXC Cycle Time

(16)

99.99 100.01 ns

t

31

TXC High/Low Time 40 50 ns

t

32

TXC Rise/Fall Time at 20% to 80% 5 ns

t

33

TXD Setup Time to TXC

u

20 ns

t

34

TXD Hold Time from TXC

u

0ns

t

35

TXE Setup Time to TXC

u

20 ns

t

36

TXE Hold Time from TXC

u

0ns

NOTE:

16. All delay and width measurements on TxC are made at 1.5V.

290421– 17

Figure 18. Transmit Timing (National)

25

82503

RECEIVE TIMINGS (National)

Symbol Parameter Min Typ Max Units

t

40

RxC Cycle Time 96 100 ns

t

41

RxC High/Low Time

(17)

40 50 60 ns

t

42

RxC Rise/Fall Time at 20% to 80% 5 ns

t

43

RXD Rise/Fall Time at 20% to 80% 5 ns

t

44

RXD Setup Time to RxC

u

30 ns

t

45

RXD Hold Time from RxC

u

20 ns

t

46

RxC Delay from CRS

u

1400 ns

t

47

RxC Continuing Beyond CRS

v

5 cycles

NOTE:

17. All delay and width measurements on RXC are made at 1.5V.

290421– 18

Figure 19. Receiving Timings (National)

26

82503

Controller Interface Timing (AMD Mode)

TRANSMIT TIMINGS

(18)

(AMD)

Symbol Parameter Min Typ Max Units

t

50

TCLK Cycle Time 99.99 100.01 ns

t

51

TCLK High Time (@0.8V to 2.0V) 45 50 58 ns

t

52

TCLK Low Time (@2.0V to 0.8V) 45 50 58 ns

t

53

TCLK Rise/Fall Time (@0.8V to 2.0V) 2.5 5 ns

t

54

TX Setup Time to TCLK

u

20 ns

t

55

TX Hold Time from TCLK

u

5ns

t

56

TENA Setup Time to TCLK

u

20 ns

t

57

TENA Hold Time from TCLK

u

5ns

NOTE:

18. Delay times for TX, TENA, and TCLK are measured from 0.8V for falling edges, and 2.0V for rising edges.

290421– 19

Figure 20. Transmit Timings (AMD)

27

82503

RECEIVE TIMINGS

(19)

(AMD)

Symbol Parameter Min Typ Max Units

t

60

RCLK Cycle Time 96 100 ns

t

61

RCLK High Time (@0.8V to 2.0V) 38 50 ns

t

62

RCLK Low Time (@2.0V to 0.8V) 38 50 ns

t

63

RCLK Rise/Fall Time (@0.8V to 2.0V) 2.5 5 ns

t

64

RX Rise/Fall Time (@0.8V to 2.0V) 2.5 5 ns

t

65

RX Hold time from RCLK

u

10 ns

t

66

RX Setup Time to RCLK

u

45 ns

t

67

RENA Deassertion Hold Time from RCLK

u

40 50 80 ns

t

68

RCLK Delay from RENA

u

450 ns

NOTE:

19. Delay times for RX, RENA, and RCLK are measured from 0.8V for falling edges and 2.0V for rising edges.

290421– 20

Figure 21. Receive Timings (AMDÐStart of Frame)

290421– 21

Figure 22. Receive Timings (AMDÐEnd of Frame)

28

82503

Controller Interface Timings (Fujitsu Mode)

TRANSMIT TIMINGS (Fujitsu)

Symbol Parameter Min Typ Max Units

t

70

TCKN Cycle Time 99.99 100.01 ns

t

71

TCKN High/Low Time

(20)

40 50 ns

t

72

TCKN Rise/Fall Time at 20% to 80% 5 ns

t

73

TXD Setup Time to TCKN

v

(20)

20 ns

t

74

TXD Hold Time from TCKN

v

(20)

0ns

t

75

TEN Setup Time to TCKN

v

(20)

20 ns

t

76

TEN Hold Time from TCKN

v

(20)

0ns

NOTE:

20. Timing measurements are referenced at 1.5V level.

290421– 22

Figure 23. Transmit Timings (Fujitsu)

29

82503

RECEIVE TIMINGS (Fujitsu)

Symbol Parameter Min Typ Max Units

t

80

RCKN Cycle Time 96 100 ns

t

81

RCKN High/Low Time

(21)

35 50 60 ns

t

82

RCKN Rise/Fall Time at 20% to 80% 5 ns

t

83

RXD Setup Time from RCKN

v

(21)

20 ns

t

84

RXD Hold Time from RCKN

v

(21)

10 ns

t

85

XCD Assertion Hold Time from RCKN

v

(21)

010 ns

t86XCD Deassertion Hold Time from RCKN

v

(21)

120 ns

t

87

XCD Deassertion Setup Time from RCKN

v

(21)

80 130 ns

t

88

RCKN Delay from XCD

u

(21)

1400 ns

NOTE:

21. Timing measurements are referenced at 1.5V.

290421– 23

Figure 24. Receive Timings (FujitsuÐStart of Frame)

290421– 24

Figure 25. Receive Timings (FujitsuÐEnd of Frame)

30

82503

TPE Timings

TPE TRANSMIT TIMINGS

Symbol Parameter Min Typ Max Units

t

90

TxD to TD Bit Loss at Start of Packet 2 bits

t

91

TxD to TD Steady State Propagation Delay 400 ns

t

92

TxD to TD Startup Delay 600 ns

t

93

TDH and TDL Pairs Edge Skew (@VCC/2) 1.5 3 ns

t

94

TDH and TDL Pairs Rise/Fall Times (@0.5V to V

CC

b

0.5V) 2 5 ns

t

95

TDH and TDL Pairs Bit Cell Center to Center 99 100 101 ns

t

96

TDH and TDL Pairs Bit Cell Center to Boundary 49 50 51 ns

t

97

TDH and TDL Pairs Return to Zero from Last TDH

u

250 400 ns

t

98

Link Test Pulse Width 98 100 102 ns

t

99

Last TD Activity to Link Test Pulse 8 13 24 ms

t

100

Link Test Pulse to Data Separation 190 200 ns

290421– 25

Figure 26. TPE Transmit Timings (Start of Frame)

290421– 26

Figure 27. TPE Transmit Timings (End of Frame)

31

82503

290421– 27

Figure 28. TPE Transmit Timings (Link Test Pulse)

TPE RECEIVE TIMINGS

Symbol Parameter Min Typ Max Units

t

105

RD to RxD Bit Loss at Start of Packet 4 19 bits

t

106

RD to RxD Invalid Bits Allowed at Start of Packet 1 bits

t

107

RD to RxD Steady State Propagation Delay 400 ns

t

108

RD to RxD Start UP Delay 2.4 ms

t

109

RD Pair Bit Cell Center Jitter

g

13.5 ns

t

110

RD Pair Bit Cell Boundary Jitter

g

13.5 ns

t

111

RD Pair Held High from Last Valid Positive Transition 230 400 ns

t

112

CRS Assertion Delay (Intel, NS, and Fuji Mode) 700 ns
(AMD Mode) 1500 ns

t

113

CRS Deassertion Delay 450 ns

290421– 28

Figure 29. TPE Receive Timings (Start of Frame)

32

82503

290421– 29

Figure 30. TPE Receive Timings (End of Frame)

TPE COLLISION TIMINGS

Symbol Parameter Min Typ Max Units

t

115

Onset of Collision (RD Pair and RTS Active) to CDT Assert 900 ns

t

116

End of Collision (RD Pair or RTS Inactive) to CDT Deassert 900 ns

t

117

CDT Assert to RxD Sourced from RD Pair 900 ns

t

118

CDT Deassert (RD Pair Inactive) to RxD Sourced from TxD 900 ns

290421– 30

Figure 31. TPE Collision Timings (Start of Collision)

33

82503

290421– 31

Figure 32. TPE Collision Timings (End of Collision)

TPE LINK INTEGRITY TIMINGS

Symbol Parameter Min Typ Max Units

t

120

Last RD Activity to Link Fault (Link Loss Timer) 50 100 150 ms

t

121

Minimum Received Linkbeat Separation

(20)

25 7ms

t

122

Maximum Received Linkbeat Separation

(21)

25 50 150 ms

NOTES:

20. Linkbeats closer in time to this value are considered noise, and are rejected.

21. Linkbeats further apart in time than this value are not considered consecutive, and are rejected.

290421– 32

Figure 33. TPE Link Integrity Timings

34

82503

AUI Timings

AUI TRANSMIT TIMINGS

Symbol Parameter Min Typ Max Units

t

125

TxD to TRMT Pair Steady State Propagation Delay 200 ns

t

126

TRMT Pair Rise/Fall Times 3 5 ns

t

127

Bit Cell Center to Bit Cell Center of TRMT Pair 99.5 100 100.5 ns

t

128

Bit Cell Center to Bit Cell Boundary of TRMT Pair 49.5 50 50.5 ns

t

129

TRMT Pair Held at Positive Differential at Start of Idle 200 ns

t

130

TRMT Pair Return tos40 mV from Last Positive Transition 8.0 ms

290421– 33

Figure 34. AUI Transmit Timings

AUI RECEIVE TIMINGS

Symbol Parameter Min Typ Max Units

t

135

RCV Pair Rise/Fall Times 10 ns

t

136

RCV Pair Bit Cell Center Jitter in Preamble

g

12 ns

t

137

RCV Pair Bit Cell Center/Boundary Jitter in Data

g

18 ns

t

138

RCV Pair Idle Time after Transmission 8 ms

t

139

RCV Pair Return to Zero from Last Positive Transition 160 ns

t

140

CRS Assertion Delay (Intel, National, Fujitsu Modes) 100 ns
(AMD Mode) 1050 ns

t

141

CRS Deassertion Delay 350 ns

t

142

CRS Inhibited after Frame Transmission 4 4.3 5 ms

290421– 34

Figure 35. AUI Receive Timings

35

82503

AUI COLLISION TIMINGS

Symbol Parameter Min Typ Max Units

t

145

CLSN Pair Cycle Time 80 118 ns

t

146

CLSN Pair Rise/Fall Times 10 ns

t

147

CLSN Pair Return to Zero from Last Positive Transition 160 ns

t

148

CLSN Pair High/Low Times 35 70 ns

t

149

CDT Assertion Time 75 ns

t

150

CDT Deassertion Time 300 ns

t

151

CRS Deassertion Time (Intel Mode Only, RCV Pair Idle) 450 ns

290421– 35

Figure 36. AUI Collision Timings

AUI NOISE FILTER TIMINGS

Symbol Parameter Min Typ Max Units

t

152

RCV Pair Noise Filter Pulse Width Accept (

@

b

285 mV) 25 ns

t

153

CLSN Pair Noise Filter Pulse Width Accept (

@

b

285 mV) 25 ns

290421– 36

Figure 37. AUI Noise Filter Timings

36

82503

LOOPBACK TIMINGS

Symbol Parameter Min Typ Max Units

t

155

TxD to RxD Bit Loss at Start of Packet 16 bits

t

156

TxD to RxD Steady State Propagation Delay 600 ns

t

157

TxD to RxD Startup Delay 2.2 ms

t

158

SQE Test Wait Time 0.6 1.2 1.6 ms

t

159

SQE Test Duration 0.5 0.8 1.5 ms

t

160

LPBK Setup/Hold Times to RTS

(22)

1.0 ms

NOTE:

22. Guarantees proper processing of transmitted packets. Violation of this specification will not result in spurious data trans-

mission. Incoming data packets occuring during transitions on LPBK

will not be accepted.

290421– 37

Figure 38. Loopback Timings

37

82503

JABBER TIMINGS

Symbol Parameter Min Typ Max Units

t

165

Maximum Length Transmission before Jabber Fault (TPE) 20 25 150 ms

t

166

Maximum Length Transmission before Jabber Fault (AUI) 10 13 18 ms

t

167

Minimum Idle Time to Clear Jabber Function 250 420 750 ms

290421– 38

Figure 39. Jabber Timings

LED TIMINGS

Symbol Parameter Min Typ Max Units

t

170

TxLED, RxLED, COLED On Time 50 450 ms

t

171

TxLED, RxLED, COLED Off Time 50 ms

t

172

LILED On Time 50 ms

t

173

LILED Off Time 100 ms

290421– 39

Figure 40. LED Timings

38

82503

MODE TIMINGS

(23, 24)

Symbol Parameter Min Typ Max Units

t

175

Mode Pins Setup to RTS

v

100 ms

t

176

Mode Pins Hold from RTS

u

100 ms

t

177

Mode Pins Setup to RD Active

(25)

100 ms

t

178

Mode Pins Hold from RD Active

(25)

100 ms

NOTES:

23. Guarantees Proper processing of data packets. Violation of these specifications will not affect the integrity of the network.

24. Mode pins are: APORT, APOL/XSQ, LID, JABD, and TPE/AUI

.

25. Any data received within 100 ms of a mode transmission will be considered invalid.

290421– 53

Figure 41. Mode Timings

39

82503

RESET, TEST, AND LOW POWER MODE TIMINGS

Symbol Parameter Min Typ Max Units

t

180

TEST and JABD Setup Time to RESET

v

50 ns

t

181

RESET Pulse Width 300 ns

t

182

Low Power Mode Deactivation from TEST and JABD

v

1ms

290421– 41

Figure 42. Reset Timings (Test Mode)

290421– 43

Figure 43. Reset Timings (Start of Low Power Mode)

290421– 42

Figure 44. Reset Timings (End of Low Power Mode)

40

82503

PACKAGE DIMENSIONS

PLASTIC LEADED CHIP CARRIER

290421– 45

Figure 45. Principle Dimensions and Data

290421– 46

Figure 46. Molded Details

41

82503

290421– 47

Figure 47. Terminal Details

290421– 48

Figure 48. Standard Package Bottom View (Tooling Option 1)

42

82503

290421– 49

Figure 49. Standard Package Bottom View (Tooling Option II)

290421– 50

Figure 50. Detail J. Terminal Detail

43

82503

290421– 51

Figure 51. Detail L. Terminal Details

NOTES:

The above diagrams use a 20-lead PLCC package to show symbols for package dimensions. The table below indicates
dimensions in mm that are specific to the 44-lead PLCC package.

1. All dimensions and tolerances conform to ANSI Y14.5M-1982.

2. Datum plane ÐHÐ located at top of mold parting line and coincident with top of lead, where lead exits plastic body.

3. Datums D–E and F–G to be determined where center leads exit plastic body at datum plane ÐHÐ.

4. To be determined at seating plane ÐCÐ.

5. Dimensions D

1

and E1do not include mold protrusion.

6. Pin 1 identifier is located within one of the two defined zones.

7. Locations to datum ÐAÐ and ÐBÐ to be determined at plane ÐHÐ.

8. These two dimensions determine maximum angle of the lead for certain socket applications. If unit is intended to be

socketed, it is advisable to review these dimensions with the socket supplier.

9. Controlling dimension, inch.

10. All dimensions and tolerances include lead trim offset and lead plating finish.

11. Tweezing surface planarity is defined as the furthest any lead on a side may be from the datum. The datum is estab-

lished by touching the outermost lead on that side and parallel to D–E or F–G.

Symbol Description Min Max

A Overall Height 4.19 4.57

A

1

Distance from Lead Shoulder to Seating Plane 2.29 3.05

D Overall Package Dimension 17.4 17.7

D

1

Plastic Body Dimension 16.5 16.7

D

2

Foot Print 15.0 16.0

E Overall Package Dimension 17.4 17.7

E

1

Plastic Body Dimension 16.5 16.7

E

2

Foot Print 15.0 16.0

CP Seating Plans Coplanarity 0.00 0.10

TCP Tweezing Coplanarity 0.00 0.10

LT Lead Thickness 0.23 0.38

44

82503

44-LEAD QUAD FLATPACK PACKAGE

290421– 52

Figure 52. 44-Lead Quad Flatpack Package

Symbol Description Min Nom Max

A Package Height 2.35

A1 Stand Off 0 0.60

B Lead Width 0.2 0.3 0.4

C Lead Thickness 0.1 0.15 0.2

D

1

Package Body 10

E

1

Package Body 10

e

1

Lead Pitch 0.65 0.8 0.95

D Terminal Dimension 12.0 12.4 12.8

E Terminal Dimension 12 12.4 12.8

L

1

Foot Length 0.38 0.58 0.78

Y Coplanarity 0.1

T Lead Angle 0 10

§

NOTE:

Unless otherwise specified, all units are in millimeters.

45