Datasheet S5T8554B01-D0B0, S5T8554B01-S0B0, S5T8554B02-L0B0, S5T8557B01-D0B0, S5T8557B01-S0B0 Datasheet (Samsung)

1 CHIP CODEC S5T8554B/7B

INTRODUCTION

16-CERDIP

The S5T8554B/7B are single-chip PCM encoders and decoders
(PCM CODECs) and PCM line filters. These devices provide all the
functions required to interface a full-duplex voice telephone circuit
with a time-division-multiplex (TDM) system.
These devices are designed to perform the transmit encoding and
receive decoding as well as the transmit and receive filtering
functions in PCM system. They are intended to be used at the
analog termination of a PCM line or trunk.
These devices provide the bandpass filtering of the analog signals
prior to encoding and after decoding. These combination devices
perform the encoding and decoding of voice and call progress tones
as well as the signalling and supervision information.

16-DIP-300A

8−DIP−300

FEATURES

• Complete CODEC and filtering system

• Meets or exceeds AT&T D3/D4 and CCITT specifications
µ-Law: S5T8554B, A-Law: S5T8557B

• On-chip auto zero, sample and hold, and precision voltage references

• Low power dissipation: 60mW (operating), 3mW (standby)

• ± 5V operation

• TTL or CMOS compatible

• Automatic power down

ORDERING INFORMATION

Device Package Operating Temperature

S5T8554B02-L0B0
S5T8557B02-L0B0

S5T8554B01-D0B0
S5T8557B01-D0B0

S5T8554B01-S0B0
S5T8557B01-S0B0

16-CERDIP −25°C to 125°C

16-DIP-300A −25°C to +70°C

16-SOP-BD300 −25°C to +70°C

1

S5T8554B/7B 1 CHIP CODEC

X

PIN CONFIGURATION

+

V

GNDA

1

BB

2

VFXI

16

-

VFXI

15

VFRO

V

FS

D

BCLKR/CLKSEL

MCLKR/PDN

3

4

CC

5

R

6

R

7

8

KT8554/7

S5T8554B/7B

14

13

12

11

10

9

PIN DISCRIPTION

Pin No Symbol Description

1 V

BB

2 GNDA Analog ground.
3 VFRO Analog output of the receive power Amp.
4 V
5 FS
6 D

CC

R

R

7 BLCKR/

CLKSEL

VBB = −5V ± 5%

VCC = +5 V ± 5%
Receive frame sync pulse. 8kHz pulse train
PCM data input.
Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock

in normal operation and BCLKX is used for both TX and RX directions.
Alternately direct clock input available, vary from 60kHz to 2.048MHz.

GS

X

TS

X

FSXS

D

X

BCLK

MCLK

X

8 MCLKR/

9 MCLK

10 BLCK

11 D
12 FS
13 TS
14 GS
15 VFXI
16 VFXI

2

PDN

X

When MCLKR is connected continuously high, the device is powered down.
Normally connected continuously low, MCLKX is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.

Must be 1.536MHz/1.544MHz or 2.048MHz.

X

May be vary from 64kHz to 2.048MHz but BCLKX is externally tied with MCLKX in

X

normal operation.
PCM data output.

X
X

TX frame sync pulse. 8kHz pulse train.
Changed from high to low during the encoder timeslot. Open drain output.
Analog output of the TX input amplifier. Used to set gain through external resistor.

X

−

Inverting input stage of the TX analog signal.

+

Non-inverting input stage of the TX analog signal.

1 CHIP CODEC S5T8554B/7B

ABSOLUTE MAXIMUM RATING

Characteristic Symbol Value Unit

Positive Supply Voltage V
Negative Supply Voltage V
Voltage at Any Analog Input or Output V
Voltage at Any Digital Input or Output V

CC

BB
I (A)
I (D)

VCC + 0.3 ~ VBB - 0.3 V

VCC + 0.3 ~ GNDA - 0.3 V

7 V

−7 V

Operating Temperature Range Ta −25 ~ +125 °C
Storage Temperature Range T
Lead Temperature (Soldering, 10 secs) T

STG

LEAD

−65 ~ +150 °C
300 °C

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;
typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

POWER DISSIPATION

Power-Down Current I
Power-Down Current I

CC (DOWN)
BB (DOWN)

Active Current I
Active Current I

DIGITAL INTERFACE

CC (A)
BB (A)

No Load − 0.5 1.5 mA
No Load − 0.05 0.3 mA
No Load − 6.0 9.0 mA
No Load − 6.0 9.0 mA

Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I
Output Low Voltage V

IL

IH
IL
IH
OL

GNDA≤ VIN ≤ VIL, all digital input −10 − 10 µA
VIH ≤ VIN ≤ V
DX, IL = 3.2mA

SIGR, IL = 1.0mA
TSX, IL = 3.2mA, open drain

Output High Voltage I

O (HZ)

DX, IH = −3.2mA
SIGR, IH = −1.0mA

Output Current in High

I

O (HZ)

DX, GNDA ≤ VO ≤ V

Impedance State (Tri -state)

ANALOG INTERFACE WITH RECEIVE FILTER

Output Resistance R

O

Pin VFRO − 1 3 Ω

− − − 0.6 V

− 2.2 − − V

CC

−10 − 10 µA

− − 0.4

0.4

0.4

2.4

− − V

2.4

CC

−10 − 10 µA

V
V
V

V

3

S5T8554B/7B 1 CHIP CODEC

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;
typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Load Resistance R
Load Capacitance C
Output DC Offset Voltage V

OO (RX)

L
L

VFRO = ± 2.5V 600 − − Ω

− − − 500 pF

− −200 − 200 mV

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER

Input Leakage Current I

LKG

Input Resistance R
Output Resistance R
Load Resistance R
Load Capacitance C
Output Dynamic Range V

OD (TX)

Voltage Gain G

I

O

L
L

V

-2.5V≤V≤+2.5V, VFXI+ or VFXI- −200 − 200 nA

-2.5V≤V≤+2.5V, VFXI+ or VFXI- 10 − − MΩ
Closed loop, unity gain − 1 3 Ω
GS
GS

X
X

10 − − kΩ

− − 50 pF
GSX, RL≤10KW ± 2.8 − − V
VFXI+ to GSX 5,000 − − V/N

Unity Gain Bandwidth BW − 1 2 − MHz
Offset Voltage V
Common-Mode Voltage V

IO (TX)

CM (TX)

CMRRXA > 60dB −2.5 − 2.5 V

− −20 − 20 mV

Common-Mode Rejection Ratio CMRR DC Test 60 − − dB
Power Supply Rejection Ratio PSRR DC Test 60 − − dB

4

1 CHIP CODEC S5T8554B/7B

TIMING CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;
typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Frequency of Master Clock f

Rise Time of Bit Clock t
Fall Time of Bit Clock t
Holding Time from Bit Clock

t

Low to Frame Sync
Holding Time from Bit Clock

t

High to Frame Sync
Set-Up Time from Frame Sync

t

SU (FBCL)

to Bit Clock Low
Delay Time from BCLKX High

t

to Data Valid
Delay Time to TSX Low t

Delay Time from BCLKX Low to

D (TSXL)

t

Data Output Disabled
Delay Time to Valid Data from

FSX or BCLKX, Whichever
Comes Later

MCK

Depends on the device used
and the BCLKR/CLKSEL Pin.
MCLKX and MCLK

R (BCK)

F (BCK)tPB
H (LFS)

H (RFS)

tPB = 488ns − − 50 nS

Long frame only 0 − − nS

Short frame only 0 − − nS

Long frame only 80 − − nS

D (HDV)

Load = 150pF plse 2 LSTTL
loads

Load = 150pF plse 2 LSTTL
loads

D (LDD)

t

D (VD)

CL = 0pF to 150pF 20 − 165 nS

− 1.536

− nS

1.544

R

2.048

= 488ns − − 50 nS

0 − 180 nS

− − 140 nS

− 50 − 165 nS

Set-Up Time from DR Valid to
BCLK

Hold Time from FS

R/X

Low

Low to

R/X

DR Invalid
Set-Up Time from FS

BCLK

R/X

Low

R/X

to

Width of Master Clock High t
Width of Master Clock Low t
Rise Time of Master Clock t
Fall Time of Master Clock t
Set-Up Time from BCLKX High

t
(and FSX In Long Frame Sync
Mode) to MCLKX Falling Edge

t

SU (DRBL)

t

H (BLDR)

t

SU (FBLS)

W (MCKH)

W (MCKL)

R (MCK)
F (MCK)

SU (BHMF)

− 50 − − nS

− 50 − − nS

Short frame sync pulse (1 or 2
bit clock periods long) (Note 1)

MCLKX and MCLK
MCLKX and MCLK
MCLKX and MCLK
MCLKX and MCLK

R
R
R
R

First bit clock after the leading
edge FS

X

50 − − nS

160 − − nS
160 − − nS

− − 50 nS

− − 50 nS

− − − −

5

S5T8554B/7B 1 CHIP CODEC

TIMING CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;
typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Period of Bit Clock t
Width of Bit Clock High t
Width of Bit Clock Low t
Hold Time from BCLK

to FS

X/R

Low

X/R

Low

Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FSX or FSR)

Minimum Width of the Frame

CK
W (BCKH)
W (BCKL)

t

H (BLFL)

t

H (3rd)

t

WFL

VIH = 2.2 160 − − nS
VIL = 0.6V 160 − − nS
Short frame sync pulse (1 or 2

bit clock periods long) (Note 1)
Long frame sync pulse

(From 3 to 8 bit clock periods
long)

64K bit/s operating mode − − − nS

− 485 488 15,725 nS

− − − nS

100 − − nS

Sync Pulse (Low Level)

NOTE: For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high.

6

1 CHIP CODEC S5T8554B/7B

TIMING DIAGRAM

t

TSx

MCLK
MCLK

t

t

R(MCK)

R
X

F(MCK)

t

W(MCKH)

D(TSXL)

t

W(MCK) t

t

SU(BHMF)

CK

BCLK

FS
D

X

BCLK

FS

D

X

t

H(HFS)

t

X

SU(FBLS)

1 2 3 4 5 6 7 8

t

H(BLFL)

t

D(HDV)

t

D(LDD)

1 2 3 4 5 6 7 8

R

t

H(HFS)

t

R

R

SU(FBLS)

1 2 3 4 5 6 7 8

t

H(BLFL)

t

SU(DRBL)

t

H(BLDR)

1 2 3 4 5 6 7 8

t

H(BLDR)

Figure 1. Short Frame Sync Timing

7

S5T8554B/7B 1 CHIP CODEC

TIMING DIAGRAM (Continued)

t

W(MCKL)

MCLK
MCLK

R
X

t

R(MCK)

t

SU(BHML)

t

F(MCK)

t

W(MCKH)

t

SBFM

t

CK

t

F(BCK)

t

W(BCKH)

t

W(BCKL)

BCLK

FS

D

X

BCLK

FS

D

X

t

H(HFS)

X

1 2 3 4 5 6 7 8

t

t

SU(FBCK)tRB

t

D(VD)

t

D(VD)

t

H(3rd)

CK

t

D(HDV)

t

D(LDD)

9

1 2 3 4 5 6 7 8

t

D(VD)

R

t

H(HFS)

R

R

1 3 4 5 6 7 8

t

t

SU(FBLK)

t

SU(DRBL)

H(3rd)

t

H(BLDL)

1 2 3 4 5 6 7 8

9

t

H(BLDL)

Figure 2. Long Frame Sync Timing

8

1 CHIP CODEC S5T8554B/7B

TRANSMISSION CHARACTERISTICS

(Unless otherwise specified: Ta = 0°C to 70°C, VCC = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz,
VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

AMPLITUDE RESPONSE

Receive Gain, Absolute G

Receive Gain, Relative to
G

V (ARX)

Absolute Receive Gain
Variation with Temperature

Absolute Receive gain
Variation with Supply Voltage

Receive Gain Variations with
Level

Receive Output Drive Level V
Absolute Level V

Max Overload Level V

V (ARX)

G

V (RRX)

∆G

V (ARX)

/∆T
∆G

V (ARX)

/∆V
∆G

V (RXL)

O (RX)
AL

OL (AMX)

Ta=25°C, VCC=5V, VBB=−5V

−0.15 − 0.15 dB
Input = Digital code sequence for
0dBm signal at 1020Hz

f = 0Hz to 3000Hz
f = 3300Hz
f = 3400Hz
f = 4000Hz

−0.15

−0.35

−0.7

− 0.15

0.05
0

−14

dB
dB
dB
dB

Ta = 0°C to 70°C − − ±0.1 dB

VCC=5V ± 5%, VBB=−5V ± 5% − − ±0.05 dB

Sinusoidal test method, reference

−

input PCM code corresponds to an
ideally encoded −10dB0 signal
PCM level = −40dBm0 to +3dBm0
PCM level = −50dBm0 to −10dBm0
PCM level = −55dBm0 to −50dBm0

−0.2

−0.4

−1.2

0.2

0.4

1.2

dB
dB

dB
RL = 600Ω −2.5 − 2.5 V
Norminal 0dBm0 level is 4dBm

− 1.2276 − Vrms

(600Ω) 0dBm0
Max overload level (3.17dBm0):

− 2.501 − V

PK

S5T8554B
Max overload level (3.14dBm0):
S5T8557B

Transmit Gain, Absolute G

Transmit Gain, Relative to
G

V (ARX)

V (ATX)

G

V (RTX)

Ta = 25°C, V

CC

= 5V, V

BB

= −5V

Input at GSX = 0dBm0 at 1020Hz
f = 16Hz

f = 50Hz
f = 60Hz
f = 200Hz
f = 300Hz - 3000Hz
f = 3300Hz
f = 3400Hz
f = 4000Hz
f = 4600Hz and up, measure
response from 0Hz to 4000Hz

−0.15 − 0.15 dB

−1.8

−0.15

−0.35

−0.7

− −40

−30

−26

−0.1

0.15

0.05
0

−

−14

−32

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

9

S5T8554B/7B 1 CHIP CODEC

TRANSMISSION CHARACTERISTICS

(Unless otherwise specified: Ta = 0°C to 70°C, VCC = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz,
VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Absolute Transmit Gain
Variation with Temperature

Absolute Transmit Gain
Variation with Supply Voltage

Transmit Gain Variations with
Level

∆G

V(ATX)

Ta = 0°C to 70°C − − ±0.1 dB

/∆T
∆G

(ATX)

V

VCC = 5V ±5%, VBB = −5V ±5% − − ±0.05 dB

/∆V

− Sinusoldal test method Reference
level = − 10dBm0
VFXI + = − 40dBm0 to +3dBm0
VFX + = − 50dBm0 to − 40dBm0
VFXI + = − 55dBm0 to − 50dBm0

ENVELOPE DELAY DISTORTION WITH FREQUENCY

Receive Delay, Absolute t
Receive Delay, Relative to

t

D (ARX)

D (ARX)

t

D (RRX)

f = 1600Hz − 180 200 µs
f = 500Hz - 1000Hz

f = 1000Hz - 1600Hz
f = 1600Hz - 2600Hz
f = 2600Hz - 2800Hz
f = 2800Hz - 3000Hz

Transmit Delay, Absolute t
Transmit Delay, Relative to

t

D (ATX)

D (ATX)

t

D (RTX)

f = 1600Hz − 290 315 µs
f = 500Hz - 600Hz

f = 600Hz - 800Hz
f = 800Hz - 1000Hz
f = 1000Hz - 1600Hz
f = 1600Hz - 2600Hz
f = 2600Hz - 2800Hz
f = 2800Hz - 3000Hz

−0.2

−0.4

−1.2

−40

−30

− 195

−

−25

−120

70
100
145

120

50

20

55

80
130

0.2

0.4

1.2

90
125
175

220
145

75

40

75
105
155

dB
dB
dB

µs
µs
µs
µs
µs

µs
µs
µs
µs
µs
µs
µs

NOISE

Receive Noise, CMessage
Weighted

Receive Noise, PMessage
Weighted

Transmit Noise, CMessage
Weighted

Transmit Noise, PMessage
Weighted

Noise, Single Frequency N

Positive Power Supply
Rejection, Transmit

10

N

RXC

N

RXP

N

TXC

N

TXP

SF

PSRR

(PTX)

PCM code equals alternating

− 8 11 dBrnc0
positive and negative zero,
S5T8554B

PCM code equals, positive zero,

− −82 −79 dBm0p
S5T8557B

S5T8554B − 12 15 dBrnc0

S5T8557B − 74 −67 dBm0p

f = 0kHz to 100kHz, loop around

− − −53 dBm0
measurement, VFXI + = 0Vrms

VFXI + = 0Vrms, VCC = 5.0VDC +

40 − − dBC

100mVrms f = 0kHz - 50kHz

1 CHIP CODEC S5T8554B/7B

TRANSMISSION CHARACTERISTICS

(Unless otherwise specified: Ta = 0°C to 70°C, VCC = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz,
VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Negative Power Supply
Rejection, Transmit

Positive Power Supply
Rejection, Receive

Negative Power Supply
Rejection, Receive

Spurious Out-of-Band
Signals at the Channel
Output

DISTORTION

Signal to Total Distortion
Transmit or Receive Half­Channel

PSRR

(NTX)

PSRR

(PRX)

VFXI + = 0Vrms, VBB = −5.0VDC +
100mVrms f = 0kHz - 50kHz

PCM code equals positive zero
VCC = 5.0VDC + 100mVrms
f = 0Hz - 4000Hz
f = 4kHz - 25kHz
f = 25kHz - 50kHz

PSRR

(NRX)

PCM code equals positive zero
VBB = 5.0VDC + 100mVrms
f = 0Hz - 4000Hz
f = 4kHz - 25kHz
f = 25kHz - 50kHz

SOS Loop around measurement,

0dBm0, 300Hz - 3400Hz input
PCM applied to DR, Measure
individual image signals at VFRO
4600Hz - 760Hz
7600Hz - 8400Hz
8400Hz - 100,000Hz

THD
THD

TX
RX

Sinusoidal test method
Level = 3.0dBm0
= 0dBm0 to 30dBm0
= −40dBm0 XMT
RCV
= −55dBm0 XMT
RCV

40 − − dBC

− −

40
40
36

dBC

dB
dB

− −

40
40
36

dBC

dB
dB

− −

−32

−40

−32

dB
dB
dB

− −

33
26
29
30
14
15

dBC
dBC
dBC
dBC
dBC
dBC

Single Frequency Distortion,
Transmit

Single Frequency Distortion,
Receive

THD

(TDO)

THD

(RX)

Intermodulation Distortion THD

CROSSTALK

Transmit to Receive

CT
Crosstalk, 0dB0 Transmit
Level

SF

SF

IMD

(TX-RX)

− − − −46 dB

− − − −46 dB

Loop around measurement,
VFXI + = −4dBm0 to −21dBm0,
two frequencies in the range
300Hz - 3400Hz

f = 300Hz - 3400Hz DR = Steady
PCM code

− − −41 dB

− −90 −75 dB

11

S5T8554B/7B 1 CHIP CODEC

TRANSMISSION CHARACTERISTICS

(Unless otherwise specified: Ta = 0°C to 70°C, VCC = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz,
VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.)

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Receive to Transmit
Crosstalk, 0dBm0 Receive

CT

(RX-TX)

− − −90 −70
(Note1)

Level

NOTE: CT

is measured with a - 40dBm0 activating signal applied at VFXI +

(RX-TX)

Encoding Format At DX Output

µ

-Law KT8554 A-Law KT8557

VIN (at GSX) = + Full Scale 10000000 10101010
VIN (at GSX) = 0V 11111111

01111111

11010101
01010101

VIN (at GSX) = -Full Scale 0000000 00101010

dB

12

1 CHIP CODEC S5T8554B/7B

APPLICATION CIRCUIT

+5V -5V

0.1µF 0.1µF

12

V

BB

MCLK

BCLK

BCLKR/CLKSEL

FSXS

FS

D

11

X

D

6

R

9

X

10

X

7

12

5

R

R6

u-low only

FS

DX

DR

CLOCK

X/R

FROM SLIC

TO SLIC

PDN

R4

R1

R3

R2

GS

14

VFXI

15

VFRO

3

VFXI

16

8

4

V

CC

X

S5T8554B/7B

KT8554/7

-

+

MCLKR/PDN

GND

NOTES:

1. Supposing Desired Line Termination Impedance RL = 600ohm
It is 0dBm = 0.77459Vrms

2. TX Gain 20 log (R2/R1), R1 + R2 < 100Kohm, or The Correspondence of 1-CHIP CODEC 0dBm 0 = 4dBm.

SELECTION OF MASTER CLOCK FREQUENCY

BCLKR/CLKSEL S5T8554B S5T8557B

Clocked 1.536 / 1.544MHz 2.048MHz
0 2.048MHz 1.536 / 1.544MHz
1 (or open) 1.536 / 1.544MHz 2.048MHz

13

S5T8554B/7B 1 CHIP CODEC

NOTES

14